JPH09152989A - Data cache memory system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the need for writing operation to a main memory at the time of a cache mishit by performing write-back operation asynchronously with access to a data cache from a CPU. SOLUTION: A hit controller 3 receives input of hit information outputted by a comparator 2 by a cache controller 15 and outputs signals controlling reading operation and writing operation for corresponding data based upon address information to a data memory part 8 included in the data cache memory. A cache writer 1 searches a tag memory part 9 to check whether or not there is a dirty bit, and outputs a control signal for storing blocks present in rewritten data in the main memory when there is the rewritten data in the tag memory part 9. Then the hit controller 3 and cache writer 1 operate to control other blocks independently of each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data cache memory system.

[0002]

2. Description of the Related Art Conventionally, it is generally well known that an effective main memory access time can be shortened and speeded up by providing a small-capacity high-speed buffer memory between a processor and a main memory. That is. A memory system for realizing this speedup is called a cache memory system, and FIG. 7 shows a block diagram of an example of a conventional data cache memory system. The buffer memory mounted in the system is called a cache memory. Further, the cache memory can be divided into two, an instruction cache memory and a data cache memory. When divided into two in this way, the instruction cache memory buffers the instructions, and the data cache memory buffers the data. By dividing the cache memory into two, it is possible to access the instruction and the data at the same time, so that it is possible to improve the processing capability of the computer system. The present invention is an invention relating to a cache memory system related to the improvement of the data cache.

In general, data cache operations are CP
Although it occurs in writing from U, the method is mainly divided into two methods. One is a method of simultaneously writing data in a cache memory and a main memory, which is called a write-through method. The other is to write the main data to the cache memory once, and only if the rewritten data exists in the block to be replaced due to a cache miss, write the contents of the block to the main memory, and write the new data. It is a method of writing by a process of replacing with a block and is called a write-back method.

First, a conventional data cache memory system by the write-back method will be described. FIG.
FIG. 4 is a block diagram showing a basic configuration of a conventional data cache memory system. As shown in FIG. 7, in this conventional example, an internal address bus 102 and an internal data bus 10 are used.
3, external address bus 112 and external data bus 11
3 corresponding to CPU 3, main memory 13, comparator 2, data memory unit 8, tag memory unit 9, cache controller 15, external bus interface 1
6 is provided. The CPU 12, the data memory unit 8 and the external bus interface 16 are connected to each other via the internal data bus 103.
The internal address bus 102 output from 12 is connected to the tag memory unit 9, the data memory unit 8 and the external bus interface 16, and the external address bus 112 is provided between the main memory 13 and the external bus interface. And an external data bus 113 are connected. Further, FIG. 8 is a flow chart during a read operation in this conventional example, and FIG. 9 is a flow chart during a write operation.

First, referring to FIG. 7, a description will be given of the case where the address of the data to be read is present in the tag memory unit 9 when the data is read by the write back method. First, the address information output from the CPU 12 is input to the comparator 2 and the tag memory unit 9 (step 81). In the comparator 2, it is compared and collated whether the corresponding address information in the tag memory unit 9 matches the address information output from the CPU 12 (step 82). If they match in step 82, the hit information 106 is output from the comparator 2 and input to the cache controller 15. This coincident operation state is called a cache hit, but this also applies to data writing.
In the cache controller 15, hit information 1
In response to the input of 06, the control signal 110 is generated and output, and input to the data memory unit 8 and the external bus interface 16. In the data memory unit 8, the CPU receives the control signal 110 and receives it.
The corresponding data is read from the block designated by the address information inputted from 12 and is output onto the data bus 103, and the data reading process is completed (step 87). At that time, the external interface 16 is controlled by the control signal 110 input from the cache controller 1 and the external address bus 1 is controlled.
12 and the external data bus 113.

Next, at the time of reading data by the write-back method, if the address of the data to be read does not exist in the tag memory section 9, following the input of the address information at the step 81, the step 82 is followed. In the above, the comparison and comparison result of the corresponding address information in the tag memory unit 9 by the comparator 2 and the address information output from the CPU 12 do not match, and the data to be read does not exist in the data memory unit 8. It will be. This mismatched operating state is called a cache miss. Next, it is determined whether the dirty bit of the block to be replaced in the tag memory unit 9 is set (step 83). When the dirty bit is set in step 83, it is indicated that the contents of the data memory unit 8 and the contents of the main memory 13 do not match (miss hit), and the external interface 16 is shown. It is determined whether or not the block to be replaced has been rewritten (step 84). If the block to be replaced has been rewritten, the external bus interface 16 is used. And the block to be replaced is the data memory unit 8
Is written from the main memory 13 to the main memory 13 (step 85), and then the block containing the miss-hit address data is read from the main memory 13 via the external bus interface 16 to obtain the data memory. It is stored in the unit 8. At the same time, the dirty bit of the corresponding block is reset, and the tag memory unit 9 is rewritten and updated (step 86). The dirty bit is a bit indicating that the data in the data cache and the data in the main memory do not match. Then, the corresponding data is read from the block designated by the address information input from the CPU 12 and is output onto the data bus 103, and the data reading process ends (step 87). Further, when the dirty bit is not set in step 83, the contents of the data memory unit 8 and the contents of the main memory 13 match each other.
In step 96, the block included in the address data is read from the main memory 13 without overwriting the data in the data 3 and is overwritten in the data memory unit 8. At the same time, the tag memory unit 9 is rewritten and updated, the corresponding data is written in the data memory unit 8, and the process ends. Even when the block to be replaced has not been rewritten in step 94, the process proceeds to step 96 and the same processing as above is performed.

Next, referring to FIG. 7, a description will be given of the case where the address of the data to be rewritten exists in the tag memory unit 9 when the data is written by the write back method. The address information output from the CPU 12 is
It is input to the comparator 2 and the tag memory unit 9 (step 91). In the comparator 2, the corresponding address information in the tag memory unit 9 is compared and collated with the address information output from the CPU 12 (step 92). If they match in step 92, the hit information 106 is output from the comparator 2 and input to the cache controller 15. The cache controller 15 receives the hit information 106 and generates and outputs the control signal 110.
Data memory unit 8 and external bus interface 16
Is input to In the data memory unit 8, when the control signal 110 is input, the data on the internal data bus 103 is stored in the block designated by the address information input from the CPU 12 (step 9).
7). And at that time, the external bus interface 1
6 is controlled by the control signal 110 input from the cache controller 1 and is separated from the external address bus 112 and the external data bus 113.

Next, at the time of writing data by the write-back method, if the address of the data to be rewritten does not exist in the tag memory section 9, following the input of the address information in the step 91, the step 92 is followed. In the above, the comparison and comparison result by the comparator 2 between the corresponding address information in the tag memory unit 9 and the address information output from the CPU 12 does not match, and the rewriting target data does not exist in the data memory unit 8. It will be. Then, it is determined whether or not the dirty bit of the block to be replaced in the tag memory unit 9 is set (step 93). If the dirty bit is set in step 93, it indicates that the contents of the data memory unit 8 and the contents of the main memory 13 do not match (miss hit), and the external interface 16 is used. Thus, it is determined whether the block to be replaced has been rewritten (step 94). In step 94, if the block to be replaced has been rewritten, the block to be replaced is written from the data memory unit 8 to the main memory 13 via the external bus interface 16. (Step 95), and then the external bus interface 1
The block containing the mishit address data is read from the main memory 13 via 6 and stored in the data memory unit 8. At the same time, the tag memory unit 9 is rewritten and updated, and the dirty bit of the corresponding block is reset (step 96). After that, the corresponding data is written in the data memory unit 9 and the process ends. Further, when the dirty bit is not set in step 93, the contents of the data memory unit 8 and the contents of the main memory 13 match each other.
In step 96, the block included in the address data is read from the main memory 13 without overwriting the data in the data memory unit 8 without overwriting the data in the data memory unit 8. At the same time, the tag memory unit 9 is rewritten and updated, the corresponding data is written in the data memory unit 8, and the process ends. Even if the block to be replaced has not been rewritten in step 94, the process shifts to step 96 and the above processing is performed.

In the case of the write-through method, data is written to the main memory 13 at the same time as the data memory section 9 at the time of writing, so that the contents of the data memory section 8 and the main memory 13 do not become inconsistent. Therefore, in contrast to the write-back method, it is a method that does not require dirty bit determination and block replacement at that time. As one of the write-through methods, a write buffer composed of a FIFO is used to write data to the main memory and the write buffer of the memory at the time of writing, and the free time of the external bus is kept at the write buffer. By writing the data to the main memory 13 when it is checked,
A data cache memory system that can reduce the overhead of writing to 3 is also generally known.

[0010]

In the conventional data cache memory system described above, write back
In the case of a cache, when the dirty bit is set at the time of a cache miss hit, writing to the main memory of the block is an indispensable condition, and if the frequency of cache miss increases, this There is a drawback in that the consumption time required for writing to the main memory increases to a non-negligible level, which becomes an obstacle to improving the processing speed of the data cache memory system.

In the conventional write-through type data cache memory system using the write buffer, a cache miss at the time of reading from the data cache to the CPU causes a cache miss in the block read from the main memory to the cache. When the value includes data that should be changed first, a mismatch occurs between the contents of the cache memory and the contents of the main memory. The problem of this inconsistency has conventionally been dealt with by writing the entire contents of the write buffer to the main memory, but in the case of this method, the overhead due to writing to the main memory increases. There are drawbacks.

[0012]

In the data cache memory system of the first invention, operand data is exchanged at high speed between a central processing unit and a main memory, and the central processing unit instead of the main memory. A data cache memory, a cache controller that controls a write operation to the main memory to perform a write-back operation in parallel with an access operation to the data cache memory by the central processing unit at the time of a cache hit, and the main memory, In a data cache memory system comprising an external interface connected between the central processing unit, the data cache memory and the cache controller, the data cache memory stores predetermined tag information. A tag memory unit for storing, A data memory unit formed by a dual port RAM including a port for receiving the address of the central processing unit and a port for receiving the address of the write-back operation, the address information of the central processing unit and the tag information of the tag memory unit. And a comparator for detecting a match / mismatch between the two pieces of information, the cache controller receiving the hit information output from the comparator and receiving the data cache. Corresponding to the data memory unit included in the memory, there is a hit controller for outputting a signal for controlling the read / write operation of the corresponding data based on the address information, and a dirty bit exists in the tag memory unit. If there is rewritten data in the relevant tag memory section A predetermined internal address bus, which receives a cache writer for outputting a control signal for storing the block in which the corresponding data exists in the main memory and an R / W signal output from the central processing unit. And a bus arbiter that acts to indicate the same block with a given write-back address bus,
Is provided at least.

A data cache memory system according to a second aspect of the present invention includes a central processing unit and a main memory, and a data cache memory which, in place of the main memory, exchanges operand data with the central processing unit at high speed. ,
At the time of a cache hit, in parallel with the access operation to the data cache memory by the central processing unit,
An external interface connected between the cache controller that controls write operations to the main memory to perform a write-back operation, the main memory, the central processing unit, the data cache memory, and the cache controller. In a data cache memory system including: a data cache memory, a tag memory unit for storing predetermined tag information, a port for receiving addressing of the central processing unit, and addressing for write-back operation. A comparator for comparing and collating the address information of the central processing unit and the tag information of the tag memory unit with a data memory unit formed by a dual port RAM including a receiving port, and detecting a match / mismatch between the both information. And at least The cache controller receives the hit information output from the comparator and, in response to the data memory unit included in the data cache memory, a read operation / write operation of corresponding data based on the address information. And a hit controller that outputs a signal for controlling the address, and the address information output from the central processing unit during the write operation by the central processing unit is input and held, and in response to the cache hit, the block in which the corresponding data exists A write address buffer for outputting a control signal for storing in the main memory, and an input of an R / W signal output from the central processing unit, and a predetermined internal address bus and a predetermined write back address. A bus arbiter that acts to indicate the same block as the bus. It is characterized in.

[0014]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG.
The internal address bus 102, internal data bus 103, write back address bus 109, write back data bus 111, external address bus 112, and external data bus 113 are compared and the CPU 12, main memory 13, and cache writer 1 are compared. Device 2, hit controller 3, input control circuits 4 and 7, data input / output control circuit 5, bus arbiter 6, data memory unit 8 formed by a dual port RAM, and tag memory unit 9
And an external address bus interface 10 and an external data bus interface 11.
In the present embodiment, the hit controller 3 and the cache writer 1 are assumed to operate independently to control other blocks, respectively, and are shown in FIGS. 3 and 4. What is shown is an operation flowchart under the control of the cache controller 3, and FIG. 5 is an operation flowchart under the control of the cache writer 1.

Referring first to FIG. 1, the operation associated with the hit controller 3 will be described. As a read operation corresponding to the data memory unit 8 from the CPU 12, first, address information output from the CPU 12 is input to the comparator 2 and the tag memory unit 9 via the internal address bus 102 (step 31: FIG. 3). ). In the comparator 2, the corresponding address information in the tag memory unit 9 is
The address information output from the CPU 12 is compared and collated (step 32: FIG. 3). In step 32, in the case of a cache hit in which both pieces of information match, hit information 106 is output from the comparator 2 and input to the hit controller 3. The hit controller 3 receives the input of the hit information 106 and generates and outputs the control signal 108, which is sent to the input control circuit 4 and the data input / output control circuit 5.
Then, by the control action of the input control circuit 4 and the data input / output control circuit 5 which have received the input of the control signal 108, the corresponding data corresponding to the address information is read from the data memory unit 8 and the data on the internal data bus 103 And the data reading process ends (step 34: FIG. 3). When the address information in the tag memory unit 9 is a mishit which does not match the address information output from the CPU 12 in step 32,
Without considering the contents of the tag memory unit 9 and the data memory unit 8, the corresponding block is transferred from the main memory 13 to the external data bus 113 and the external data bus interface 11.
And is read via the internal data bus 103 to be stored in the data memory unit 8 and the tag memory unit 9 is updated (step 33: FIG. 3).
The corresponding data is output from the data memory unit 8 onto the internal data bus 103 (step 34: FIG. 3).

Further, from the CPU 12 to the data memory unit 8
In the case of the write operation corresponding to, the operation is performed in substantially the same manner as in the case of the above read. That is, first the CPU
The address information output from 12 is input to the comparator 2 and the tag memory unit 9 via the internal address bus 102 (step 41: FIG. 4). The corresponding tag information is read from the tag memory unit 9 and the internal address bus 102 is read.
Is input in parallel to the comparator 2, the address information and the tag information are compared and collated (step 42: FIG. 4), and when the both information match, the hit information 106 is output and hit. It is input to the controller 3. The control signal 108 is output from the hit controller 3 and input to the input control circuit 4 and the data input / output control circuit 5. Then, the corresponding data corresponding to the address information on the internal data bus 103 is taken into the data memory section 8 through the control action of the input control circuit 4 and the data input / output control circuit 5 by the control signal 108 (step 44: FIG. 4). In the case where the comparator 2 is a mis-hit in which the two pieces of information do not match, the corresponding block is transferred from the main memory 13 to the external data bus 113 without considering the contents of the tag memory unit 9 and the data memory unit 8.
The data is read out via the external data bus interface 11 and the internal data bus 103, stored in the data memory unit 8 and the tag memory unit 9 is updated (step 43: FIG. 4). Memory section 8
The corresponding data is written to (step 44: FIG. 4).

The above is the description of the operation related to the hit controller 3 in the first embodiment. Next, the operation of the cache writer 1 according to this embodiment will be described.

In FIG. 1, the operation of the cache writer 1 is performed independently of the operation of the hit controller 3. First, the cache writer 1 searches for dirty bits in the tag memory unit 9 (step 51: FIG. 5). Then, through the search in step 51, it is judged whether or not there is rewritten data (step 52: FIG. 5). If there is rewritten data, the block in which the corresponding data exists is stored in the main memory 13. The operation shifts to the writing operation, and when there is no rewritten data, the process returns to step 51 again, and the dirty bit in the tag memory unit 9 is searched. When there is data rewritten in step 52 and the block in which the data exists is written in the main memory 13, the hit controller 3 is inquired whether or not the cache is hit ( Step 53: FIG. 5). If the cache is not hit in step 53, it is placed in a standby state (step 56: FIG. 5), after which the process returns to step 50 again. If the cache is hit in step 53, it is judged whether the internal address bus 102 and the write-back address bus 109 are overlapped (step 54: FIG. 5), and it is not overlapped. In the case of cash writer 1
The control signal 110 output from the external address bus interface 10 and the external data bus interface 11 is sent to the data memory unit 8, the external address bus interface 10 and the external data bus interface 11. The write-back data bus 111 and the external data bus 113 are operated by the operation of the face 11.
Then, the corresponding data is written to the main block 13 via the write-back address bus 109 and the external address bus 112 (step 57: FIG. 5). At this time, the R / W signal 101 output from the CPU 12 is input to the internal address bus 102 by the bus arbiter 6.
And the write-back address bus 109 are shown to be in the same block state, and when a write operation is being performed by the CPU 12, the operation of the CPU 12 is prioritized until the write operation by the CPU 12 is completed. An arbitration operation of executing the operation is performed. In step 54, if the internal address bus 102 and the write-back address bus 109 overlap, the internal address bus 102 is given priority (step 5).
5: FIG. 5), step 53 again via step 56
Return to

Next, a second embodiment of the present invention will be described.

FIG. 2 is a block diagram showing a second embodiment of the present invention. As shown in FIG. 2, this embodiment is
The internal address bus 102, internal data bus 103, write back address bus 109, write back data bus 111, external address bus 112, and external data bus 113 are compared and the CPU 12, main memory 13, and cache writer 1 are compared. Device 2, hit controller 3, input control circuits 4 and 7, data input / output control circuit 5, bus arbiter 6, data memory unit 8 formed by a dual port RAM, and tag memory unit 9
A write address buffer 14, an external address bus interface 10 and an external data bus interface 11.

Note that the difference from the first embodiment of the present embodiment is that the address information for asynchronous writing is FIF.
It is stored in the write address buffer 14 constituted by O. This write address buffer 1
4, the internal address bus 102 from the CPU 12
Address information output via the
The address information and the R / W signal 101 are constantly monitored in response to the input of the R / W signal 101 output by the CPU 12. When the CPU 12 writes the address information, the address information is written. Address buffer 14
Once held. On the other hand, in the write operation, the control signal 107 output from the hit controller 3 is received, the current cache state is recognized, and the cache address is held in the write address buffer 14 during the cache hit. Address information is output to the write address bus 109, and the input control circuit 7
And to the external address bus interface 10. As a result, the data at the corresponding address in the data memory unit 8 is taken out and written to the corresponding address in the main memory 13 via the data input / output control circuit 5, the external data bus interface 11 and the external data bus 113. Be done.

FIGS. 3 and 4 are operation flowcharts showing the procedure of the control operation by the hit controller 3 in this embodiment. The contents of the cache read operation and the cache write operation are the same as those in the first embodiment described above. This is similar to the case, and the description thereof will be omitted because it is redundant.
The operation of the write address buffer 14, which is a feature of this embodiment, will be described below with reference to the operation flowchart of FIG.

First, as described above, the internal address bus 1
02 and the R / W signal 101 are constantly monitored by the write address buffer 14, and when the write operation by the CPU 12 occurs (step 61: FIG. 6), the address information is held in the write address buffer 14 (step 62). : FIG. 6). On the other hand, the write operation by the CPU 12 is started when the write address buffer 14 holds the address information. Therefore, it is first determined whether or not the address information is held in the FIFO of the write address buffer 14 (step 6).
3: FIG. 6). If the address information is not held in step 63, the process returns to step 63 again.
If the address information is held in step 63, the write address buffer 14
The hit controller 3 is inquired as to whether or not the cache is hit (step 64: FIG. 6), and if it is not hit, it is placed in a standby state (step 67: FIG. 6). Then, the process returns to step 64 again.
If the inquiry result indicates that the cache is hit in step 64, it is determined whether the internal address bus 102 and the write-back address bus 109 overlap (step 65: FIG. 6). If they do not overlap, both the external address bus 112 and the external data bus 113 are in an empty state, so that the external address bus interface is controlled by the control signal 110 output from the write address buffer 14. 10 and external data bus interface
FI of the write address buffer 14 via the external address bus 112 and the external data bus 113.
Based on the address information output from the FO, the corresponding block is written into the main memory 13 (step 68: FIG. 6). At that time, R output from the CPU 12
The bus arbiter 6 to which the / W signal 101 is input allows the internal address bus 102 and the write-back address bus 10
9 indicates the same block state, and when a write operation is being performed by the CPU 12, an arbitration operation of preferentially executing the operation of the CPU 12 until the write operation by the CPU 12 is completed. Is done. In step 65, the internal address bus 102 and the write-back address bus 1
09 are duplicated, the internal address bus 102
Is prioritized (step 66: FIG. 6), and the process returns to step 64 again via step 67.

That is, one feature of the present invention is that the dual port RAM is used as the data memory unit 8, whereby the write back operation is performed asynchronously with the access from the CPU to the data cache memory. Is possible.

[0026]

As described above, according to the present invention, the dual port RAM is used for the data memory portion forming the data cache, and the write back operation can be performed asynchronously with the access to the data cache memory from the CPU. By doing so, there are the following effects. (1) In the case of the rewrite back cache, in the state where the dirty flag is set at the time of a cache miss, conventionally, it is a necessary condition to write the block in the main memory, and a cache miss hit occurs. In contrast to the increase in the number of times, the time required for the write cannot be ignored and the high speed is impaired. In contrast, in the present invention, the write operation to the main memory at the time of a cache miss becomes unnecessary, and the data cache memory system There is an effect that the high speed can be effectively maintained. (2) In the write-through method using the write buffer, in the case of a cache miss at the time of reading, in the block read from the main memory to the cache, the data to be changed first by the value in the write buffer. , The contents of the cache memory and the contents of the main memory may be inconsistent. However, in the present invention, from the time when the CPU writes to the cache memory, the contents of the main memory Since the timing of shifting to the time of writing to is shortened, the effect of eliminating the above-mentioned inconsistency can be achieved without adopting the conventional overhead method of writing the entire contents of the buffer in the main memory. is there. (3) According to the present invention, the consistency between the cache memory and the main memory is improved, so that the task switch can be speeded up and the system down can be checked easily as compared with the conventional data cache memory system. In addition, there is an effect that control of cache coherency in a multiprocessor system becomes easy.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a flowchart of a read operation in the first and second embodiments.

FIG. 4 is a flowchart of a write operation in the first and second embodiments.

FIG. 5 is a flowchart showing an operation of the cache writer of the first embodiment.

FIG. 6 is a flowchart showing an operation of a write address buffer of the second embodiment.

FIG. 7 is a block diagram showing a conventional example.

FIG. 8 is a flowchart of a read operation in a conventional example.

FIG. 9 is a flowchart of a write operation in a conventional example.

[Explanation of symbols]

1 cache writer 2 comparator 3 hit controller 4 input control circuit 5 data input / output control circuit 6 bus arbiter 7 input control circuit 8 data memory unit 9 tag memory unit 10 external address bus interface 11 external data bus interface 12 CPU 13 Main memory 14 Write address buffer 15 Cache controller 16 External bus interface 31-34, 41-44, 51-57, 61-68, 8
1-87, 91-97 steps

Claims (2)

[Claims] 1. A central processing unit and a main memory, and a data cache memory which, in place of the main memory, exchanges operand data with the central processing unit at high speed.
At the time of a cache hit, in parallel with the access operation to the data cache memory by the central processing unit,
An external interface connected between the cache controller that controls write operations to the main memory to perform a write-back operation, the main memory, the central processing unit, the data cache memory, and the cache controller. In a data cache memory system comprising: a data cache memory, a tag memory unit for storing predetermined tag information, a port for receiving addressing of the central processing unit, and addressing for write-back operation. A data memory unit formed by a dual port RAM including a receiving port, and a comparator for comparing and collating address information of the central processing unit and tag information of the tag memory unit to detect a match / mismatch between the two information. And at least The cache controller receives the hit information output from the comparator, and reads / writes the corresponding data based on the address information corresponding to the data memory unit included in the data cache memory. A hit controller that outputs a signal that controls a write operation, and a search for whether or not a dirty bit exists in the tag memory unit, and if there is rewritten data in the tag memory unit, the existence of the corresponding data Block
A cache writer that outputs a control signal to be stored in the main memory, and a predetermined internal address bus and a predetermined write-back address bus by receiving an R / W signal output from the central processing unit. A data cache memory system comprising at least a bus arbiter that operates so as to indicate the same block. 2. A central processing unit and a main memory, and a data cache memory which, instead of the main memory, exchanges operand data with the central processing unit at high speed.
At the time of a cache hit, in parallel with the access operation to the data cache memory by the central processing unit,
An external interface connected between the cache controller that controls write operations to the main memory to perform a write-back operation, the main memory, the central processing unit, the data cache memory, and the cache controller. In a data cache memory system configured to include: a data cache memory, a tag memory unit that stores predetermined tag information, a port that receives addressing of the central processing unit, and addressing of a write-back operation. A data memory unit formed by a dual port RAM including a receiving port, and a comparator for comparing and collating address information of the central processing unit and tag information of the tag memory unit to detect a match / mismatch between the two information. And at least The cache controller receives the hit information output from the comparator and reads / writes the corresponding data based on the address information corresponding to the data memory unit included in the data cache memory. A hit controller that outputs a signal for controlling the operation, and during the write operation by the central processing unit, the address information output from the central processing unit is input and held, and corresponding data exists in response to the cache hit. A write address buffer that outputs a control signal for storing a block in the main memory, and an input of an R / W signal output from the central processing unit to receive a predetermined internal address bus and a predetermined write back. A bus arbiter that acts to indicate the same block as the address bus, and Data cache memory system, characterized in that.