JPH02222169A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02222169A JPH02222169A JP1042710A JP4271089A JPH02222169A JP H02222169 A JPH02222169 A JP H02222169A JP 1042710 A JP1042710 A JP 1042710A JP 4271089 A JP4271089 A JP 4271089A JP H02222169 A JPH02222169 A JP H02222169A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- silicon nitride
- active element
- semiconductor device
- active elements
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 22
- 239000002184 metal Substances 0.000 claims abstract description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 238000010438 heat treatment Methods 0.000 claims description 12
- 239000011521 glass Substances 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 239000011248 coating agent Substances 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 5
- 238000000034 method Methods 0.000 abstract description 29
- 125000002887 hydroxy group Chemical group [H]O* 0.000 abstract description 9
- 150000002500 ions Chemical class 0.000 abstract description 7
- 239000000758 substrate Substances 0.000 abstract description 7
- 239000012535 impurity Substances 0.000 abstract description 6
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 3
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 230000006837 decompression Effects 0.000 abstract 1
- 239000004615 ingredient Substances 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000002161 passivation Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 125000005372 silanol group Chemical group 0.000 description 1
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野コ
本発明は、閾値電圧が異なる複数の能動素子により形成
された半導体装置の構造に関し、特に製造過程において
データを書き込んだ読みだし専用のメモリー（以下マス
クＲＯＭと称す）において、能動素子の閾値電圧が異な
ることをデータとして用いたマスクＲＯＭを有する半導
体装置に関する。Detailed Description of the Invention [Field of Industrial Application] The present invention relates to the structure of a semiconductor device formed by a plurality of active elements having different threshold voltages, and in particular to a read-only memory (read-only memory) into which data is written during the manufacturing process. The present invention relates to a semiconductor device having a mask ROM (hereinafter referred to as a mask ROM) in which different threshold voltages of active elements are used as data.
［従来の技術］
従来の半導体装置におけるマスクＲＯＭの構造としては
、能動素子のチャンネル部の不純物濃度を変えることに
より閾値電圧を変えた複数の能動素子をから成る構造や
、能動素子と金属配線を電気的に接続する開孔部（コン
タクトホール）の有無によりマスクＲＯＭのデータとす
る構造などからなり、閾値電圧の異なる能動素子やコン
タクトホールを形成した上に配線を形成した構造になっ
ていた。[Prior Art] The structure of a mask ROM in a conventional semiconductor device includes a structure consisting of a plurality of active elements whose threshold voltages are changed by changing the impurity concentration of the channel portion of the active element, and a structure consisting of a plurality of active elements whose threshold voltages are changed by changing the impurity concentration of the channel portion of the active element, and a structure consisting of a structure in which the active elements and metal wiring are connected. It has a structure in which data is stored in a mask ROM depending on the presence or absence of electrically connected openings (contact holes), and has a structure in which active elements with different threshold voltages and contact holes are formed, and then wiring is formed.
［発明が解決しようとする課題］
しかしながら、前述の従来技術では、マスクＲＯＭのデ
ータを書き込む工程の後、配線を形成し製品とするまで
多くの工程があり、マスクＲＯＭの納期がかかるという
問題を有していた。またデータを書き込む工程としてフ
ォトリソ工程とイオン注入工程あるいはエツチング工程
を必要とし全体としての製造工程が長くなるという問題
も有していた。[Problems to be Solved by the Invention] However, with the above-mentioned conventional technology, there are many steps after the process of writing data in the mask ROM until wiring is formed and the product is manufactured, and the problem is that it takes a long time to deliver the mask ROM. had. Another problem is that a photolithography process and an ion implantation process or an etching process are required as a process for writing data, which lengthens the overall manufacturing process.
そこで、本発明はこのような課題を解決しようとするも
ので、その目的とするところは、マスクＲＯＭのデータ
を書き込む工程からマスクＲＯＭの完成までの工程を短
縮することと、データを書き込むための工程を簡単にす
ることのできる半導体装置を提供するところにある。Therefore, the present invention attempts to solve such problems, and its purpose is to shorten the process from writing data in a mask ROM to completion of the mask ROM, and to shorten the process for writing data. It is an object of the present invention to provide a semiconductor device that can simplify the process.
［課題を解決するための手段］
本発明の半導体装置は、（１）複数からなるＭＯＳ型の
能動素子と、その能動素子上の酸化シリコンを主成分と
する絶縁膜と、窒化シリコンを主成分とする絶縁膜と、
ガラス溶液の塗布及び加熱により形成された絶縁膜と、
その絶縁膜上の金属膜からなる半導体装置に於いて、前
記窒化シリコンを主成分とする絶縁膜の一部で所望の能
動素子上について開孔部を有する構造を特徴とし、（２
）前記窒化シリコンを主成分とする絶縁膜の一部で所望
の能動素子上について開孔部を有した構造、および窒化
シリコンを主成分とする絶縁膜上にガラス溶液の塗布及
び加熱により形成された絶縁膜を有する構造による閾値
電圧の異なる能動素子を有することを特徴とし、
（３）前記能動素子上に形成する金属膜は複数の能動素
子のある領域全体を覆う構造であることを特徴とする。[Means for Solving the Problems] A semiconductor device of the present invention includes (1) a plurality of MOS type active elements, an insulating film mainly composed of silicon oxide on the active elements, and a silicon nitride mainly composed of an insulating film,
An insulating film formed by applying and heating a glass solution;
A semiconductor device comprising a metal film on an insulating film is characterized in that a part of the insulating film mainly composed of silicon nitride has an opening over a desired active element, (2)
) A structure having an opening over a desired active element in a part of the insulating film mainly composed of silicon nitride, and a structure formed by coating and heating a glass solution on the insulating film mainly composed of silicon nitride. (3) The metal film formed on the active element has a structure that covers the entire area where the plurality of active elements are located. do.
［実施例コ
第１図は本発明の半導体装置の一例を実施例として示し
た図であり、半導体基板１０１表面に複数のＭＯＳ型の
能動素子を形成し、能動素子上に酸化シリコンを主成分
とする絶縁膜１０２と開孔部を有する窒化シリコンを主
成分とする絶縁膜１０３ガラス溶液の塗布及び加熱によ
り形成された絶縁膜１０４と絶縁膜上の金属膜１０５と
パッシベーション膜１０６からなる構造となっている。[Example 1] FIG. 1 is a diagram showing an example of the semiconductor device of the present invention as an example, in which a plurality of MOS type active elements are formed on the surface of a semiconductor substrate 101, and silicon oxide is the main component on the active elements. An insulating film 102 mainly composed of silicon nitride having an opening, an insulating film 104 formed by coating and heating a glass solution, a metal film 105 on the insulating film, and a passivation film 106. It has become.
さらにこの酸化シリコンを主成分とする絶縁膜１０２は
ＯＨ基などのイオンを加熱処理中に透過できる膜質であ
る。Further, the insulating film 102 mainly composed of silicon oxide has a film quality that allows ions such as OH groups to pass through during heat treatment.
窒化シリコンを主成分とする絶縁膜１０３は緻密であり
ＯＨ基などのイオンを加熱処理によっても透過しない膜
質である。またガラス溶液の塗布及び加熱により形成さ
れた絶縁膜１０４は酸化シリコンのほかにＯＨ基やその
ほかの不純物を含んだ膜質である。絶縁膜１０２の形成
例として、０．１ｔ。The insulating film 103 whose main component is silicon nitride is dense and has a film quality that does not allow ions such as OH groups to pass through even when subjected to heat treatment. Further, the insulating film 104 formed by applying and heating a glass solution is a film containing OH groups and other impurities in addition to silicon oxide. As an example of forming the insulating film 102, the thickness is 0.1 t.
ｒｒ程度の減圧下で４００°Ｃ程度の温度によりＳｉＨ
４と０２を化学反応させ５ｉ０２として半導体基板上に
降り積もらせ５ｉ０２を主成分とする絶縁膜を形成する
方法（以下、減圧ＣＶＤ法と称す）がある。絶縁膜１０
３の形成例として、ｌｔ。SiH at a temperature of about 400°C under reduced pressure of about rr
There is a method (hereinafter referred to as low pressure CVD method) in which 4 and 02 are chemically reacted to form 5i02 and deposited on a semiconductor substrate to form an insulating film containing 5i02 as a main component. Insulating film 10
As an example of formation of 3, lt.
ｒｒ程度の減圧下で３００°Ｃ程度の温度および高周波
電界によるプラズマによりＳｉＨ４とＮＨ３を化学反応
させＳｉｘＮｙとして半導体基板上に降り積もらせ窒化
シリコンを主成分とする絶縁膜を形成する方法（以下、
プラズマＣＶＤ法と称す）がある。また絶縁膜１０４の
形成例として東京応化製の０ＣＤ−Ｐ−４８３１６など
を半導体基板上に回転塗布した後、４００°Ｃ程度の加
熱処理により溶液をガラス化して絶縁膜を形成する方法
（以下、ＳＯＧ法と称す）がある。A method (hereinafter referred to as
(referred to as plasma CVD method). As an example of forming the insulating film 104, a method (hereinafter referred to as (referred to as the SOG method).
第２図（ａ）から（、ｅ）は本発明の半導体装置を形成
する方法を実施例として工程を追って示した図である。FIGS. 2(a) to 2(e) are diagrams showing step by step a method for forming a semiconductor device according to an embodiment of the present invention.
以下この図にしたがって本発明を実施例として工程を追
って説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained step by step as an example with reference to this figure.
第２図（ａ）で示す様に半導体基板２０１上に不純物を
拡散したソース及びドレイン２０７、ゲート絶縁膜２０
８、ゲート電１極２０９、下層の絶縁膜２１０、引出し
配線２１１からなる複数の能動素子を形成する。ここて
は、−例としてこの能動素子はＮチャンネルＭＯＳトラ
ンジスタで、初期の閾値電圧は０．７■であるものとす
る。次に第２図（ｂ）に示す様に半導体基板及び能動素
子上に減圧ＣＶＤ法により５ｉ０２を主成分とする絶縁
膜２０２とプラズマＣＶＤ法により窒化シリコンを主成
分とする膜２０３を形成する。この窒化シリコンを主成
分とする絶縁膜２０３の一部で所望の能動素子上のみ、
第２図（Ｃ）に示すようにフォトリソ技術及びエツチン
グ技術により開孔部２０３′を形成する。さらに第２図
（ｄ）に示すようにこの絶縁膜２０３上及び開孔部２０
３°上にＳＯＧ法により絶縁膜２０４を形成し、金属膜
２０５を形成しパターニングする。このとき絶縁膜２０
４により下層の能動素子による段差や開孔部を形成した
絶縁膜による段差を平坦化できる。また金属膜２０５は
前記の複数の能動素子が存在する領域全体を覆うように
形成し、この領域以外の回路上の金属膜２０５は除去す
るか、第２の配線として使用してもよい。この後この半
導体装置上にパッシベーション膜２０５を形成する。こ
のパッシベーション膜２０６を形成すると同時に、ある
いはパッシベーション膜形成の前か後に加熱処理する事
により、ＳＯＧ法により形成された絶縁膜２０４に含ま
れているＯＨ基などのイオンが移動する。第２図（ｅ）
で示すようにＳＯＧ法により形成した絶縁膜２０４の下
に窒化シリコンを主成分とする絶縁膜２０３がある能動
素子上ではＯＨ基などのイオンは下層に移動できないた
め、下の能動素子への影響はないが、窒化シリコンを主
成分とする絶縁膜が開孔部２０３′になっている下の能
動素子はＳＯＧ法により形成した絶縁膜２０４に含まれ
ていたＯＨ基などのイオン２１４は金属膜２０５の下へ
移動し能動素子のゲート絶縁膜に２０８に達し、能動素
子のチャンネル部分２１２゛の閾値電圧を変化させる。As shown in FIG. 2(a), a source and drain 207 with impurities diffused on a semiconductor substrate 201 and a gate insulating film 20
8. A plurality of active elements consisting of a gate electrode 209, a lower insulating film 210, and an extraction wiring 211 are formed. Here, for example, it is assumed that this active element is an N-channel MOS transistor and the initial threshold voltage is 0.7. Next, as shown in FIG. 2(b), an insulating film 202 containing 5i02 as a main component by low pressure CVD and a film 203 containing silicon nitride as a main component by plasma CVD are formed on the semiconductor substrate and active elements. A part of the insulating film 203 mainly composed of silicon nitride is formed only on the desired active element.
As shown in FIG. 2(C), an opening 203' is formed by photolithography and etching. Furthermore, as shown in FIG.
An insulating film 204 is formed 3° above by the SOG method, and a metal film 205 is formed and patterned. At this time, the insulating film 20
4, it is possible to flatten the step caused by the active element in the lower layer or the step caused by the insulating film in which the opening is formed. Further, the metal film 205 may be formed to cover the entire region where the plurality of active elements are present, and the metal film 205 on the circuit other than this region may be removed or used as a second wiring. After that, a passivation film 205 is formed on this semiconductor device. At the same time as forming this passivation film 206, or by performing heat treatment before or after forming the passivation film, ions such as OH groups contained in the insulating film 204 formed by the SOG method are moved. Figure 2(e)
As shown in , on an active element where there is an insulating film 203 mainly composed of silicon nitride under an insulating film 204 formed by the SOG method, ions such as OH groups cannot move to the lower layer, so they have no effect on the active element below. However, ions 214 such as OH groups contained in the insulating film 204 formed by the SOG method are removed from the metal film in the active element below, where the insulating film mainly composed of silicon nitride forms the opening 203'. It moves below 205 and reaches the gate insulating film of the active element 208, changing the threshold voltage of the channel portion 212' of the active element.
本実施例では閾値電圧が０．７ｖからＯ■以下に変化し
た。このようにして閾値電圧の異なる複数の能動素子か
らなる半導体装置が形成された。In this example, the threshold voltage changed from 0.7 V to below O■. In this way, a semiconductor device including a plurality of active elements having different threshold voltages was formed.
また前記の実施例のような方法で形成した複数の閾値電
圧が異なる能動素子をデータとしてマスりＲＯＭを形成
することができる。Further, a mass ROM can be formed using a plurality of active elements having different threshold voltages formed by the method of the above embodiment as data.
以上述べたように本発明の実施例により閾値電圧の異な
る能動素子を有する半導体装置を形成する場合、能動素
子、引出し配線２１１、及び酸化シリコンを主成分とす
る絶縁膜２０２及び窒化シリコンを主成分とする絶縁膜
２０３を形成後、絶縁膜２０３のパターニング、更にＳ
ＯＧ法による絶縁膜２０４の形成と金属膜２０５の形成
および加熱処理により異なる閾値電圧にする事ができる
ためマスクＲＯＭのような半導体装置においてデータ書
き込みをする工程から完成まで少ない工程で半導体装置
が完成する。As described above, when forming a semiconductor device having active elements with different threshold voltages according to the embodiment of the present invention, the active elements, the lead wiring 211, the insulating film 202 mainly composed of silicon oxide, and the insulating film 202 mainly composed of silicon nitride. After forming the insulating film 203, patterning of the insulating film 203 and further S
Different threshold voltages can be obtained by forming the insulating film 204 by the OG method, forming the metal film 205, and heat treatment, so the semiconductor device can be completed with fewer steps from the process of writing data to completion in a semiconductor device such as a mask ROM. do.
また本実施例ではガラス溶液の塗布及び加熱により形成
する絶縁膜の例としてＳＯＧ法による絶縁膜を例に挙げ
たが、このほかシラノール系溶液やポリイミドの溶液な
どのようなＯＨ基を含む溶液を用いたガラス溶液ならば
本発明の半導体装置を構成できる。Furthermore, in this example, an insulating film formed by the SOG method was used as an example of an insulating film formed by coating and heating a glass solution, but in addition, solutions containing OH groups such as silanol solutions and polyimide solutions were used. The semiconductor device of the present invention can be constructed using the glass solution used.
［発明の効果］
以上述べたように本発明の半導体装置の構造によれば、
ＳＯＧ法による絶縁膜の形成と金属膜の形成及び加熱処
理により下層の能動素子を異なる閾値電圧にする事がで
きるためＳＯＧ法により形成された絶縁膜の下の窒化シ
リコンを主成分とする絶縁膜のパターニングすなわち窒
化シリコンを主成分とする絶縁膜が開孔部になっている
が、いないかにより下層の能動素子の閾値電圧を変化さ
せることができ、閾値電圧の異なる能動素子を有する半
導体装置を形成できる。[Effects of the Invention] As described above, according to the structure of the semiconductor device of the present invention,
The insulating film whose main component is silicon nitride under the insulating film formed by the SOG method because the underlying active elements can be made to have different threshold voltages by forming the insulating film by the SOG method, forming the metal film, and heat treatment. In other words, the threshold voltage of the underlying active element can be changed depending on the patterning of the insulating film whose main component is silicon nitride, and the threshold voltage of the underlying active element can be changed. Can be formed.
また本発明の半導体装置の構造を用いてマスクＲＯＭを
形成すると、能動素子上の窒化シリコンを主成分とする
絶縁膜のパターニングによる下層の能動素子の閾値電圧
を変化させる方法によりデータの書き込みをすることに
よりマスクＲＯＭのデータ書き込みの工程から半導体装
置の完成までに必要とする工程を従来技術に比べて部分
の一程度にに短縮でき半導体装置を短い納期で完成でき
るという効果を有する。Furthermore, when a mask ROM is formed using the structure of the semiconductor device of the present invention, data is written by a method of changing the threshold voltage of the underlying active element by patterning an insulating film mainly composed of silicon nitride on the active element. This has the effect that the steps required from writing data in the mask ROM to completing the semiconductor device can be shortened to about one part compared to the conventional technology, and the semiconductor device can be completed in a short delivery time.
さらに金属膜及びパッシベーション膜形成前にＳＯＧ法
による絶縁膜の形成により半導体装置の表面が平坦化さ
れているためパッシベーション膜にひび割れが生じにく
く、信頼性の高い半導体装置を提供できる。Furthermore, since the surface of the semiconductor device is flattened by forming an insulating film using the SOG method before forming the metal film and the passivation film, cracks are less likely to occur in the passivation film, making it possible to provide a highly reliable semiconductor device.
第１図は、本発明の半導体装置の断面図。
第２図（ａ）〜（ｅ）は本発明の半導体装置を形成する
実施例を工程を於って示した図。
１０１．２０１・・・・・半導体基板
１０２．２０２・・・・・５ｉ０２を主成分とする絶縁
膜１０３．２０３・・・・・窒化シリコンを主成分とす
る絶縁膜
２０３′ ・・・・・窒化シリコンを主成分とする
絶縁膜の開孔部
１０４．２０４・・・・・ガラス溶液の塗布及び加熱に
より形成した絶縁膜
１０５．２０５・・・・・金属膜
１０６．２０６・・・・・パッシベーション膜１０７．
２０７・・・・・不純物拡散層（ソース及びドレイン）
１０８．２０８・・・・・ゲート絶縁膜１０９．２０９
・・・・・ケート電極
１１０．２１０・・・・・下層の絶縁膜１１１．２１１
・・・・・引出し配線
１１２．２１２・・・・・能動素子のチャンネル部２１
２” ・・・・・ＯＨ基及び電荷により閾値電圧の変
化したチャンネル部
１１３．２１３・・・・・コンタクトホール２１４
・・・・・ＳＯＧ法により形成した絶縁膜に含まれて
いたＯＲ基などのイオン
以上
出願人 セイコーエプソン株式会社
代理人弁理士 鈴木喜三部（他１名）FIG. 1 is a sectional view of a semiconductor device of the present invention. FIGS. 2(a) to 2(e) are diagrams showing steps of an embodiment of forming a semiconductor device of the present invention. 101.201... Semiconductor substrate 102.202... Insulating film containing 5i02 as the main component 103.203... Insulating film 203' containing silicon nitride as the main component... Openings 104,204 of an insulating film mainly composed of silicon nitride...Insulating film 105,205 formed by coating and heating a glass solution...Metal film 106,206... Passivation film 107.
207... Impurity diffusion layer (source and drain) 108.208... Gate insulating film 109.209
...Kate electrode 110.210 ... Lower layer insulating film 111.211
...Output wiring 112.212...Channel section 21 of active element
2”...Channel portion 113 where the threshold voltage has changed due to OH groups and charges.213...Contact hole 214
...Ions such as OR groups contained in the insulating film formed by the SOG method Applicant Seiko Epson Co., Ltd. Representative Patent Attorney Kizobe Suzuki (1 other person)
Claims (3)
子上の酸化シリコンを主成分とする絶縁膜と、窒化シリ
コンを主成分とする絶縁膜と、ガラス溶液の塗布及び加
熱により形成された絶縁膜と、その絶縁膜上の金属膜か
らなる半導体装置に於いて、前記窒化シリコンを主成分
とする絶縁膜の一部で所望の能動素子上について開孔部
を有する構造を特徴とする半導体装置。(1) A MOS type active element consisting of a plurality of elements, an insulating film mainly composed of silicon oxide on the active element, an insulating film mainly composed of silicon nitride, and formed by coating and heating a glass solution. A semiconductor device comprising an insulating film and a metal film on the insulating film, characterized in that a part of the insulating film mainly composed of silicon nitride has an opening over a desired active element. Device.
所望の能動素子上について開孔部を有した構造、および
窒化シリコンを主成分とする絶縁膜上にガラス溶液の塗
布及び加熱により形成された絶縁膜を有する構造による
閾値電圧の異なる能動素子を有することを特徴とする第
１項記載の半導体装置。(2) A structure in which a part of the insulating film mainly composed of silicon nitride has an opening above a desired active element, and a glass solution is applied and heated on the insulating film mainly composed of silicon nitride. 2. The semiconductor device according to claim 1, further comprising active elements having different threshold voltages due to a structure having an insulating film formed thereon.
子のある領域全体を覆う構造であることを特徴とする第
１項記載の半導体装置。(3) The semiconductor device according to item 1, wherein the metal film formed on the active element has a structure that covers the entire region where the plurality of active elements are located.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1042710A JPH02222169A (en) | 1989-02-22 | 1989-02-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1042710A JPH02222169A (en) | 1989-02-22 | 1989-02-22 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02222169A true JPH02222169A (en) | 1990-09-04 |
Family
ID=12643630
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1042710A Pending JPH02222169A (en) | 1989-02-22 | 1989-02-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02222169A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8350308B2 (en) | 2008-03-06 | 2013-01-08 | Nxp B.V. | Reverse engineering resistant read only memory |
-
1989
- 1989-02-22 JP JP1042710A patent/JPH02222169A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8350308B2 (en) | 2008-03-06 | 2013-01-08 | Nxp B.V. | Reverse engineering resistant read only memory |
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