JPH02221871A - Voltage monitor circuit - Google Patents

Abstract

PURPOSE:To monitor a hit with a simple circuit constitution at low cost and further to reduce a power consumption by outputting a detection signal when an inversion on the 1st and 2nd voltage levels is generated. CONSTITUTION:When a monitor voltage Vin is inputted to an input terminal 10 and a normal state is maintained, the output signal CMP of a comparator 11 is in L-level and no detection signal is outputted from the comparator 11. However, when voltages of a point A and a point B are lowered together responding to a rapid drop of monitor voltage Vin, the condition such as the voltage of point A is made to be lower than the voltage of point B is generated although in short time as the result of that the voltage dropping of point A is quicker than that of the point B. Hence, the signal CMP in H-level is outputted by the comparator 11 as the detection signal at the time when the voltage of point A is made to be lower than that of the point B. With this constitution, the circuit constitution is simplified and manufactured at low cost. Also the hit can be detected without fail as the monitoring is performed all the time, and further the power consumption can be reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a voltage monitoring circuit that monitors relative fluctuations in voltage, and is particularly suitable for application to detecting off-hook of a telephone receiver. .

[Prior Art] This type of voltage monitoring circuit is used, for example, to check whether a terminal device is connected to a telephone line during telephone line construction. In the case of a telephone line, the line terminal voltage is normally 48V when the handset is on the hook, that is, when there is no DC circuit formed on the telephone line.
It is. On the other hand, in the off-hook state, that is, when a direct current circuit is formed in the telephone line, the line terminal voltage drops significantly.

From this, it is possible to know that the terminal device is connected to the telephone line by detecting a drop in line terminal voltage.

By the way, for telephone line terminals, etc., the transmission characteristics such as line resistance between the terminal and the station differ depending on the location where the terminal is connected, and the voltage applied to the equipment varies, so it is necessary to monitor absolute voltage fluctuations. It is often meaningless. Therefore, a circuit that monitors fluctuations in relative voltage values is required.

FIG. 4 is a block diagram showing the configuration of a conventional voltage monitoring circuit that monitors fluctuations in relative voltage values.

In the figure, reference numeral 1 indicates an input voltage to which a monitoring voltage (line voltage) is input, and 2a and 2b indicate sample-and-hold circuits that hold sample values of the monitoring voltage for a certain period of time. These sample and hold circuits 2a.

2b is an anal mouth switch 3a13b,
It consists of hold capacitors 4a, 4b and output buffer amplifiers 5a, 5b.

Also, 6 is the 0N-OF of analog switches 3a and 3b.
This is a timing signal generation circuit that generates a timing signal for F operation. 7 is a differential amplifier that amplifies the difference between the output voltages of the sample and hold circuits 2a and 2b; 8 is a differential amplifier 7;
9 is the output voltage of a comparator that compares the output voltage of 1 with the reference voltage 8.

In the above configuration, the timing signal generation circuit 6 first turns off the analog switch 3a of the sample and hold circuit 2a at a predetermined time point. As a result, the sample value V of the monitoring voltage at the OFF time is held in the sample-and-hold circuit 2a. Next, a certain time difference (
For example, after a 0.5 second difference), the analog switch 3b of the sample/hold circuit 2b is turned OFF. As a result, the sample value Vb at this time of OFF
is held in the sample and hold circuit 2b.

The analog switches 3a and 3b repeat the above ON-OFF operation with a certain time difference, and each time, the sample value is held. The differential amplifier 7 receives two sample values V and V
The difference in b is amplified and output, and this output value vc is the sample value ■6, ■. This corresponds to the fluctuation value of the monitored voltage at the time of hold. The comparator 8 receives the output value v of the differential amplifier 7.

and a reference voltage value va. As a result, vc>vR
The comparator 8 outputs a detection signal when v
If c<va, no output is made.

In this way, it can be confirmed that the device is connected to the telephone line. Moreover, it can be known that there was a voltage fluctuation of more than a predetermined value in - boat fishing.

[Problems to be Solved by the Invention] Incidentally, in the above conventional configuration, two sample-and-hold circuits 2a and 2b and a timing generation circuit 6
Therefore, the manufacturing cost is high and the simplification of the circuit configuration is hindered. Furthermore,
When applying the voltage monitoring circuit with the above configuration to monitoring instantaneous interruptions, it is necessary to shorten the sampling period.
In this case, there was a drawback that power consumption increased.

This invention has been made in view of the above problems, and provides a voltage monitoring circuit that has a simple circuit configuration, is therefore inexpensive to manufacture, does not miss instantaneous interruptions, and consumes less power. It is intended to.

[Means for Solving the Problems] The present invention provides a first method corresponding to an input voltage in a steady state.
a first voltage generating means for generating a voltage, and making the first voltage respond sensitively to sudden fluctuations in the input voltage; Generated at a different level from the first voltage, gah,
a second voltage generating means that causes the second voltage to respond slowly to a sudden change in the human voltage; and a second voltage generating means that generates a detection signal when a reversal occurs in the levels of the first voltage and the second voltage. The above problem is solved by providing an output means for outputting the output.

[Function] For example, if the input voltage suddenly drops while the first voltage is set high and the second voltage is set low, the first voltage will respond suddenly and the second voltage will respond quickly. The voltage responds slowly, and as a result, the levels of the first voltage and the second voltage are reversed. When a level reversal occurs,
A detection signal is output, which allows voltage fluctuations to be detected.

[Embodiments] Hereinafter, embodiments of the voltage monitoring circuit of the present invention will be described with reference to the drawings.

FIG. 1 shows one embodiment of the present invention, and is a block diagram showing the electrical configuration of a voltage monitoring circuit. In this figure, l
0 is the input voltage of the monitoring voltage, 11 is the comparator, and 12 is the output voltage of the detection signal. Resistors R1 and R1 are inserted in series between the input voltage 10 and ground. The voltage vA at the connection point PA between the resistors R2 and R9 is determined by the comparator 11.
is applied to the inverted input voltage A of . Therefore, when the monitoring voltage V In is input to the input voltage 10, the voltage applied to the inverted input voltage A (hereinafter referred to as the A point voltage) is
” Rt-V +-/ (Rt+ Rt).Resistors R5 and R are further connected between the above input voltage 10 and ground.
4 are inserted in series. The voltage 8 at the connection point P8 between the resistors R3 and R4 is the non-inverting input voltage B of the comparison all.
is applied to Therefore, the input voltage lO and the monitoring voltage V
When ln is input, the voltage applied to the non-inverting input voltage B (hereinafter referred to as the B point voltage) is VB=R, ・v+
, / (R3+R4). In a steady state, the values of the resistors R, , R, , R, , R are set so that the voltage at point A is always slightly higher than the voltage at point B. In this example, the resistors R,,R,,
The resistance values of R1 and R4 are IOMΩ, 1MΩ, and IO, respectively.
By setting it to MΩ and 820 KΩ, a state is obtained in which the voltage at point A is higher than the voltage at point B. Further, a capacitor CI is inserted between the inverted input voltage A and the ground. Further, a capacitor C9 is inserted between the non-inverting input voltage B and the ground.

The capacitance of the capacitor C1 is set to a value sufficiently smaller than that of the capacitor C1. That is, in this embodiment, the capacitances of capacitors C, , C, are set to 0.1 μF and 1 μF, respectively.

Next, the operation of the voltage monitoring circuit of this example will be explained with reference to the time chart shown in FIG.

When the monitoring voltage V In is manually applied to the input voltage 10 and reaches a steady state, the voltage at point A is VA = 0.091·v.
ln, and on the other hand, the voltage at point B is VB=0.076・vl
n, and the voltage at point A is higher than the voltage at point B. Therefore, the output signal CMP of comparator 11 is at "L" level (see Figure 2 (]\)), and the detection signal from comparator 11 is However, as shown in the same figure (A), at time T1
Assume that the monitoring voltage (I7) suddenly decreases. Regarding this situation, the voltage at point A responds sensitively to fluctuations in the input voltage because the capacitance of capacitor CI is small, but the voltage at point B responds slowly to fluctuations in input voltage because the capacitance of capacitor C2 is large. (see figure (b) p.
, however). In other words, when the voltage at point A and the voltage at point B both decrease in response to a sudden decrease in the monitoring voltage V in, the voltage at point A decreases more rapidly than the voltage at point B, and as a result, the voltage at point A decreases more rapidly than the voltage at point B. , a situation occurs in which the voltage at point A becomes lower than the voltage at point B (from time T to time T) (see (b) in the same figure). Therefore, when the voltage at point A becomes lower than the voltage at point B, the comparator 11 outputs the "H" level signal CMP as a detection signal (see ( ) in the figure).

According to the above configuration, four resistors and two capacitors are provided in place of the two sample-and-hold circuits, differential amplifier, and timing generation circuit that constitute the conventional voltage monitoring circuit. As a result, the circuit configuration can be simplified, and therefore the manufacturing cost can be significantly lower. Also, unlike the conventional sample-and-hold method, constant monitoring is performed, so instantaneous interruptions can be detected without mistakes. Furthermore, since a resistor with a relatively high resistance value is used in place of a conventional circuit configuration that requires power, power consumption can be reduced despite constant monitoring.

Note that the detection level and detection sensitivity can be adjusted by arbitrarily changing and setting the electrical resistance or capacitance. For example, if the capacitor C1 inserted between the inverting input voltage Δ of the comparator 11 and ground is removed, the comparator 11 becomes very sensitive to fluctuations in the monitored voltage. Furthermore, if the difference between the voltage at point A and the voltage at point B during steady state is set to be large, the detection signal will not be output unless a large voltage fluctuation occurs.

Further, in the above-described example, a case has been described in which a voltage drop is detected, but the voltage monitoring device of the present invention is not limited to this, and can also be applied to monitoring a voltage rise.

[Application Example] Next, as an application example of the present invention, a case where the present invention is applied to a dual-off hook state detection circuit in a parent-child telephone will be described.

FIG. 3 is a block diagram showing the electrical configuration of a simultaneous OFF state detection circuit for parent and child telephones. Note that in this figure, the first
Portions corresponding to those in the figures are given the same reference numerals and their explanations will be omitted. In the figure, Ll and L2 are telephone lines, 13 is input voltage 1
The rectifier 14 for inputting a positive voltage to 0 is a mono-staple multi-vibrator (hereinafter referred to as a mono-multi), and the mono-multi vibrator 14 was provided for the following reason. In other words, the cause of the sudden voltage drop is (
1) When using both the parent phone and child phone at the same time,
(2) Possible cases include a momentary interruption of the telephone line. Therefore, the monomulti 14 was provided to prevent erroneous detection of a voltage drop caused by a momentary power outage. Note that details will be explained later. Reference numeral 15 denotes a D (delay) flip-flop, which is used together with the monomulti 14 to detect only the voltage drop caused by simultaneous use of both the parent phone and the slave phone.

Next, the operation of the detection circuit of this example will be explained with reference to the time chart shown in FIG.

First, it is assumed that before time T, only one of the parent phone or the child phone is in an OFF-hook state (in use), and the other is in an ON-hook state (not in use).

During this period, as shown in Figure 2 (A), the line voltage Vin is in a steady state, and as shown in Figure 2 (B), the voltage at point A, ■, is higher than the voltage at point B, VB. As shown in the same figure (c), comparator 1 is set to
The output signal CMP of No. 1 is at the "L" level. Therefore, at time T1, when the other telephone starts to be used and both are in the OFF-hook state at the same time, the line voltage V tn
A sudden drop occurs (see (a) in the same figure), and as a result, a phenomenon occurs in which the voltage at point A becomes lower than the voltage at point B for a certain period of time due to the above-mentioned reason.

Therefore, during the period from time T, when the voltage at point A is lower than the voltage at point B, to time T (see (b) in the same figure), comparator 11 is at the "H" level with a pulse width τ1. signal CMP
(See figure (c)).

At this time, the monomulti 14 is triggered by the rise of the signal CMP output from the comparator 11, and outputs a signal MMB (the signal waveform is shown in FIG. 4(D)) with a pulse width of τ, 4. Here, the pulse width τ, 4 of the signal MMB is shown in the same figure (c).
is set shorter than the pulse width τ of the signal CMP shown in FIG.
At the falling edge of B (time T), the “H” level signal CMP
is read and output as a detection signal KEN (see (e) in the same figure). On the other hand, if an instantaneous interruption of the signal waveform shown in FIG.
From time T, the voltage at point A is lower than the voltage at point B (
A phenomenon occurs (see figure (g)). Therefore, from time T, when the voltage at point A is lower than the voltage at point B, to time T3 (see FIG. It outputs a signal CMP of "H" level (see (h) in the same figure). At this time, in the same way as described above, the monomulti 14 is triggered by the rising edge of the signal CMP output from the comparator 11, and outputs the signal MMB (the signal waveform is shown in (d) of the same figure) with a pulse width of τ. . Here, signal MMB
The pulse width τ,4 (τ2.) is set longer than the pulse width τ,3 of the signal CMP shown in FIG. Therefore, the D-flip-flop 15 reads the signal from the voltage at the falling edge of the signal MMB (time T), but at this point, the signal CMP (see FIG. Therefore, the detection signal KEN is not outputted (see FIG. 3).

According to the above configuration, it is possible to distinguish between a voltage drop due to a momentary power outage and a voltage drop due to simultaneous use of both the parent phone and the slave phone, and only the latter case can be detected.

In addition, in the above example, both parents and children have O
Although a detection circuit has been described that detects only a voltage drop due to the FF hook state and does not detect instantaneous interruptions, the present invention can also be applied to a detection circuit that detects only instantaneous interruptions, contrary to the above. .

[Effects of the Invention] As explained above, according to the voltage monitoring circuit of the present invention, the circuit configuration can be simplified, so that it can be manufactured at significantly lower cost.

In addition, since it can be constantly monitored, there is no need to miss a momentary power outage (
can be detected.

In addition, power consumption can be reduced despite constant monitoring.

Furthermore, the detection level and detection sensitivity can be easily adjusted.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention, a block diagram showing the electrical configuration of a voltage monitoring circuit, and FIG. 2 a time chart showing the operation of the embodiment shown in FIG. 1 and the applied example shown in FIG. 3. , FIG. 3 is a block diagram showing the electrical configuration of a dual OFF state detection circuit for parent and child telephones, and FIG. 4 is a block diagram showing the configuration of a conventional voltage monitoring circuit. Vln... Input voltage, pressure, ■! 1...Second voltage, (first voltage generation means), (first voltage generation means), (second voltage generation means), (second voltage generation means) ), (output means). ■6...First voltage Rl+ R,...Resistance C, ---Conductor Rs, R-...Resistance C, ---Contest-- Condan 11... Comparator

Claims (1)

[Scope of Claims] A first voltage corresponding to an input voltage in a steady state is generated, and the first voltage corresponds to a sudden change in the input voltage.
a first voltage generating means that sensitively responds to the voltage of the input voltage, and a second voltage that corresponds to the input voltage in a steady state and generates a level different from the first voltage, and that responds to the sudden change in the input voltage. a second voltage generating means that causes the second voltage to respond slowly to fluctuations; and an output means that outputs a detection signal when a reversal occurs in the levels of the first voltage and the second voltage. A voltage monitoring circuit characterized by: