JPH0754337B2 - Voltage monitoring circuit - Google Patents

Description

TECHNICAL FIELD The present invention relates to a voltage monitoring circuit for monitoring relative fluctuations in voltage, and is particularly suitable for application to detection of an OFF hook of a handset in a telephone. .

[Prior Art] This type of voltage monitoring circuit is used, for example, to confirm whether or not a terminal device is connected to a telephone line during telephone line construction. In the case of a telephone line, the line terminal voltage is usually 48 V when the handset is in the ON hook state, that is, when the DC line is not formed in the telephone line. On the other hand, in the OFF hook state, that is, when a DC circuit is formed in the telephone line, the line terminal voltage drops significantly. From this, it is possible to know that the terminal is connected to the telephone line by detecting the drop in the line terminal voltage.

By the way, in terminals such as telephone lines, transmission characteristics such as line resistance with the station are different depending on the place where the terminal is connected, and the voltage applied to the equipment is different, so absolute voltage value fluctuations are monitored. However, it often has no meaning. Therefore, a circuit for monitoring the fluctuation of the relative voltage value is required.

FIG. 4 is a block diagram showing the configuration of a conventional voltage monitoring circuit for monitoring fluctuations in relative voltage value.

In the figure, reference numeral 1 is an input terminal to which a monitoring voltage (line voltage) is input, and 2a and 2b are sample-hold circuits for holding a sampled value of the monitoring voltage for a fixed time. Each of these sample and hold circuits 2a and 2b includes analog switches 3a and 3b, hold capacitors 4a and 4b, and output buffer amplifiers 5a and 5b. Further, 6 is a timing signal generation circuit for generating timing signals for ON-OFF operation of the analog switches 3a and 3b. Reference numeral 7 is a differential amplifier for amplifying the difference between the output voltages of the sample and hold circuits 2a and 2b, 8 is a comparator for comparing the output voltage of the differential amplifier 7 with the reference voltage V _R, and 9 is an output terminal.

In the above configuration, the timing signal generating circuit 6 first turns the analog switch 3a of the sample and hold circuit 2a on and off at a predetermined time. This allows O
The sampled value v _a of the monitor voltage at the time of FF is held in the sample and hold circuit 2a. Next, after a certain time difference (for example, 0.5 second difference) from the ON-OFF of the analog switch 3a, the analog switch of the sample and hold circuit 2b is turned on.
Turn switch 3b ON-OFF. As a result, OFF at this time
The sampled value v _b at time is held in the sample and hold circuit 2 b. The analog switches 3a and 3b repeat ON-OFF with a certain time difference, and the sampled value is held each time. The differential amplifier 7 amplifies and outputs the difference between the two sampled values v _a and v _b , and this output value v _c corresponds to the fluctuation value of the monitoring voltage at the time of holding the sampled values V _a and V _b. Is. The comparator 8 outputs the output value v _c of the differential amplifier 7.
And the reference voltage value v _R. As a result, the comparator 8 outputs a detection signal when v _c > v _R , but does not output when v _c <v _R.

In this way, it can be confirmed that the device is connected to the telephone line. In addition, it can be generally known that there is a voltage change of a predetermined value or more.

[Problems to be Solved by the Invention] By the way, in the above-described conventional configuration, two sample and hold circuits 2a and 2b and the timing generation circuit 6 are required, which increases the manufacturing cost, and This has been an obstacle to simplification of the circuit configuration. Furthermore, when the voltage monitoring circuit having the above configuration is applied to the monitoring of instantaneous interruption, it is necessary to shorten the sampling cycle, but in this case, there is a drawback that power consumption increases.

The present invention has been made in view of the above problems, and provides a voltage monitoring circuit that has a simple circuit configuration, therefore has a low manufacturing cost, does not miss an instantaneous interruption, and has low power consumption. The purpose is to do.

[Means for Solving the Problem] The present invention relates to a voltage monitoring circuit for monitoring fluctuations in line terminal voltage, which corresponds to an input voltage in a steady state.
And a second voltage corresponding to the input voltage in a steady state, the first voltage generating means for generating the voltage of 1) and sensitively responding to the first voltage to the abrupt change of the input voltage. It occurs at a level different from that of the first voltage, and
Second voltage generating means for slowly responding to the second voltage in response to a sudden change in the input voltage, and a detection signal during a period in which the levels of the first voltage and the second voltage are reversed. It is characterized by comprising an output means for outputting and a determination means for determining the occurrence of a momentary interruption or terminal connection according to the duration of the detection signal when the detection signal is output.

[Operation] For example, in a state where the first voltage is set high and the second voltage is set low, for example, if the input voltage sharply decreases, the first voltage responds rapidly and the second voltage As a result of the slow response of the voltage, the level of the first voltage and the level of the second voltage are reversed. When a level reversal occurs,
A detection signal is output, and if the duration is short, it is determined that there is a momentary interruption, and if it is long, it is determined that the terminal is connected.

[Embodiment] An embodiment of the voltage monitoring circuit of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention and is a block diagram showing an electrical configuration of a voltage monitoring circuit. In this figure, 10
Is a monitor voltage input terminal, 11 is a comparator, and 12 is a detection signal output terminal. A resistor R ₁ is connected between the input terminal 10 and ground.
And R ₂ are inserted in series. The voltage V _{A at} the connection point P _A between the resistors R ₁ and R ₂ is applied to the inverting input terminal A of the comparator 11. Therefore, when the monitor voltage V _in is input to the input terminal 10, the voltage applied to the inverting input terminal A (hereinafter referred to as A
(Point voltage) is V _A = R ₂ · V _in / (R ₁ + R ₂ ). Resistors R ₃ and R ₄ are further inserted in series between the input terminal 10 and the ground. Connection point P _B between the above resistors R ₃ and R ₄
The voltage V _B applied to the non-inverting input terminal B of the comparator 11.
Therefore, when the monitoring voltage V _in is input to the input terminal 10, the voltage applied to the non-inverting input terminal B (hereinafter referred to as the B point voltage) is V _B = R ₄ · V _in / (R ₃ + R ₄ ). In the steady state, the values of the resistors R ₁ , R ₂ , R ₃ , and R ₄ are always set so that the voltage at the point A is slightly higher than the voltage at the point B. In this example, the resistor
Set the resistance values of R ₁ , R ₂ , R ₃ , and R ₄ to 10MΩ, 1MΩ, and 10M, respectively.
By setting Ω and 820 KΩ, the voltage at the point A is higher than the voltage at the point B. Also,
A capacitor C ₁ is inserted between the inverting input terminal A and the ground. A capacitor C ₂ is inserted between the non-inverting input terminal B and the ground. And the capacitor
The capacitance of C ₁ is set to a value sufficiently smaller than that of the capacitor C ₂ . That is, in this embodiment, the electric capacities of the capacitors C ₁ and C ₂ are 0.1 μF and
It is set to 1 μF.

Next, the operation of the voltage monitoring circuit of this example will be described with reference to the time chart shown in FIG.

When the monitoring voltage V _in is input to the input terminal 10 and becomes a steady state, the voltage at the point A becomes V _A = 0.091 · V _in , while the voltage at the point B becomes V _B = 0.076 · V _in , and the point A Since the voltage becomes higher than the point B voltage, the output signal CMP of the comparator 11
Is at the "L" level (see FIG. 2C), and the detection signal is not output from the comparator 11. However, as shown in (a) of the figure, it is assumed that the monitoring voltage V _in sharply drops at the time point T ₁ . Against this situation, the voltage at point A is a capacitor
Since the capacitance of C ₁ is small, it responds sensitively to fluctuations in the input voltage, but since the voltage at point B has a large capacitance of capacitor C ₂ , it can respond only slowly to fluctuations in the input (Fig. reference). That is, when the A point voltage and the voltage at the point B in response to a sudden drop in the monitored voltage V _in is lowered together, as a result of the A side point voltage is rapidly lowered than the voltage at the point B, but a short time it is a , A situation in which the voltage at point A becomes lower than the voltage at point B (from time T ₂ to time T ₅ ) occurs (see (b) in the same figure). Therefore, when the voltage at the point A becomes lower than the voltage at the point B, the comparator 11 outputs the signal CMP at the "H" level as a detection signal (see (c) in the figure).

As described above, according to the above configuration, four resistors and two capacitors are provided in place of the two sample and hold circuits, the differential amplifier, and the timing generation circuit that constitute the conventional voltage monitoring circuit. Since this is done, the circuit configuration can be simplified, and therefore, it is possible to manufacture at a much lower cost. Further, unlike the conventional sample and hold method, since constant monitoring is performed, instantaneous interruption can be detected without error. Furthermore, since a resistor having a relatively high resistance value is used in place of the conventional circuit configuration that requires power, it is possible to reduce power consumption despite constant monitoring.

The detection level and the detection sensitivity can be adjusted by arbitrarily setting the electric resistance or the electric capacity. For example, if the capacitor C ₁ inserted between the inverting input terminal A of the comparator 11 and the ground is removed, it becomes very sensitive to the fluctuation of the monitoring voltage. In the steady state, A
If a large difference between the point voltage and the point B voltage is set, the detection signal is not output unless a large voltage fluctuation occurs.

Further, in the above example, the case where the voltage drop is detected has been described, but the voltage monitoring device of the present invention is not limited to this, and can be applied to the monitoring of the voltage increase.

[Application example] Next, as an application example of the present invention, both
The case of application to the OFF hook state detection circuit will be described.

FIG. 3 is a block diagram showing an electrical configuration of the simultaneous OFF state detection circuit for parent and child telephones. In this figure, the parts corresponding to those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. In the figure, L1 and L2 are telephone lines, 13 is a rectifier for inputting a positive voltage to the input terminal 10, and 14 is a monostable multivibrator (hereinafter referred to as monomulti).
The reason for providing this mono-multi 14 is as follows. That is, it is considered that the cause of the sudden voltage drop is (1) when both the parent phone and the child phone are used at the same time, and (2) when a momentary interruption of the telephone line occurs. Therefore, the mono-multi 14 is provided in order to prevent the voltage drop due to the instantaneous interruption from being erroneously detected. The details will be described later. Reference numeral 15 is a D (delay) -flip-flop for detecting only the voltage drop due to the simultaneous use of both the parent telephone and the child telephone together with the monomulti 14.

Next, the operation of the detection circuit of this example will be described with reference to the time chart shown in FIG.

First, before time T ₁ , only one of the parent phone and the child phone is in the OFF hook state (in use) and the other is in the ON hook state (not in use). During this period, as shown in Fig. 2 (a), the line voltage V _in
Is in a steady state, and the point A voltage V _A is set to be higher than the point B voltage V _B as shown in FIG. Output signal CM of comparator 11
P is at "L" level. Therefore, at the time point T ₁ , when the other telephone is started to be used and both are in the OFF hook state at the same time, the line voltage V _in drops sharply (see (a) in the figure). For some reason, the voltage at the point A becomes lower than the voltage at the point B for a certain period. Therefore, between time T ₂ and time T ₅ when the voltage at the point A is lower than the voltage at the point B (see (b) in the same figure), the comparator 11 keeps the “H” level of the pulse width τ ₂₅ . The signal CMP is output (see (c) in the figure). At this time, Mono Multi 14 is a comparator
Triggered by the rising edge of the signal CMP output from 11,
A signal MMB with a pulse width of ₂₄ (the signal waveform is shown in FIG. Here, the pulse width τ ₂₄ of the signal MMB is set shorter than the pulse width τ _{25 of the} signal CMP shown in FIG. Therefore, the D-flip-flop 15 is
In MMB falling (time T _4), reads the "H" level signal CMP, and outputs as a detection signal KEN (see FIG (e)). On the other hand, at the time point T ₁ , if a momentary interruption of the signal waveform shown in (f) of the figure is input, from the time point T ₂ to the time point
During T _3, a phenomenon occurs in which the voltage at the point A becomes lower than the voltage at the point B (see (g) of the same figure). Therefore, between time T ₂ and time T ₃ when the voltage at the point A is lower than the voltage at the point B (see (g) in the same figure), the comparator 11 keeps the “H” level of the pulse width τ ₂₃ . The signal CMP is output (see the same figure (h)). At this time as well, similarly to the above, the monomulti 14 is triggered by the rising edge of the signal CMP output from the comparator 11, and outputs the signal MMB having the pulse width of τ ₂₄ (the signal waveform is shown in FIG. . Here, the pulse width τ ₂₄ (<τ ₂₅ ) of the signal MMB is set longer than the pulse width τ _{23 of the} signal CMP shown in FIG. Therefore, the D-flip-flop 15 is the signal MM.
At the falling edge of B (time T ₃ ), the signal is read from the terminal D, but at this time, the signal CMP (Fig.
(See (i) in the figure), the detection signal KEN is not output.

According to the above configuration, it is possible to distinguish between a voltage drop due to a momentary interruption and a voltage drop due to simultaneous use of both the parent phone and the child phone, and it is possible to detect only the latter case.

In the above example, both of the OF
Only detect the voltage drop due to the F-hook condition,
Although the detection circuit in which the instantaneous interruption is not detected has been described, the present invention can also be applied to a detection circuit that detects only the instantaneous interruption, contrary to the above.

[Effects of the Invention] As described above, according to the voltage monitoring circuit of the present invention, since the circuit configuration can be simplified, it is possible to manufacture at a much lower cost.

Further, since it is possible to constantly monitor, it is possible to detect a momentary interruption or a subsequent terminal without mistake.

Further, it is possible to reduce the power consumption despite the constant monitoring.

Furthermore, it is easy to adjust the detection level and the detection sensitivity.

[Brief description of drawings]

FIG. 1 shows an embodiment of the present invention, and is a block diagram showing the electrical configuration of a voltage monitoring circuit, and FIG. 2 is a time chart showing the operation of the embodiment shown in FIG. 1 and the application shown in FIG. FIG. 3 is a block diagram showing the electrical configuration of a dual off-state detection circuit for parent and child telephones, and FIG. 4 is a block diagram showing the configuration of a conventional voltage monitoring circuit. V _in ...... Input voltage, V _A ...... First voltage, V _B ...... Second voltage, R ₁ , R ₂ ...... Resistors (first voltage generating means), C ₁ ......
Capacitor (first voltage generating means), R ₃ , R ₄ ... Resistor (second voltage generating means), C ₂ ... Capacitor (second voltage generating means), 11 ... Comparator (output means) ).

Continuation of the front page (56) References JP-A-63-315962 (JP, A) Actually opened 61-114374 (JP, U) JP-B 64-5261 (JP, B2)

Claims (1)

[Claims] 1. A voltage monitoring circuit for monitoring fluctuations in line terminal voltage, wherein a first voltage corresponding to an input voltage in a steady state is generated, and the first voltage is applied to a sudden fluctuation in the input voltage.
Of the first voltage generating means for sensitively responding to the input voltage and the second voltage corresponding to the input voltage in the steady state at a level different from that of the first voltage, and the abrupt change of the input voltage. Second voltage generating means for slowly responding to the second voltage in response to fluctuations, and output means for outputting a detection signal during a period in which the levels of the first voltage and the second voltage are reversed. A voltage monitoring circuit, comprising: a determination unit configured to determine, when the detection signal is output, whether a momentary interruption or a terminal connection occurs according to a duration of the detection signal.