JPH02220132A - Cpu type deciding device - Google Patents

Cpu type deciding device

Info

Publication number
JPH02220132A
JPH02220132A JP1040320A JP4032089A JPH02220132A JP H02220132 A JPH02220132 A JP H02220132A JP 1040320 A JP1040320 A JP 1040320A JP 4032089 A JP4032089 A JP 4032089A JP H02220132 A JPH02220132 A JP H02220132A
Authority
JP
Japan
Prior art keywords
cpu
type
cpu type
executing time
execution time
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1040320A
Other languages
Japanese (ja)
Other versions
JPH0630061B2 (en
Inventor
Hiroyuki Kishimoto
岸本 宏之
Tsutomu Ueno
勉 上野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
PFU Ltd
Original Assignee
PFU Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by PFU Ltd filed Critical PFU Ltd
Priority to JP1040320A priority Critical patent/JPH0630061B2/en
Publication of JPH02220132A publication Critical patent/JPH02220132A/en
Publication of JPH0630061B2 publication Critical patent/JPH0630061B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Executing Machine-Instructions (AREA)
  • Microcomputers (AREA)

Abstract

PURPOSE:To omit a set state changing operation by deciding the type of a CPU through the comparison carried out between the measured executing time and the executing time stored in a decision table. CONSTITUTION:A CPU type deciding means 54 decides the type of a CPU by comparing the executing time measured by a loop executing time measuring means 52 with the executing time stored in a decision table 80. That is, the executing time of a loop executing means 50 varies with the change of the frequency of a basic control clock 12. A timer 14 can measure the executing time regardless of the frequency of the clock 12. Thus the CPU type is decided by comparing the executing time measured by the means 52 with that stored in the table 80. As a result, a CPU type deciding device is obtained with no addition of circuits nor any operation required for change of the CPU type just by preparing those means 50, 52 and 54, and the table 80 in a form of firmware.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、基本的な動作は同じであるが動作可能な基本
動作クロックの最高周波数(以下CPUタイプと称す)
が異なる複数種のCPUが使用可能なコンピュータシス
テムのためのCPUタイプ判別装置に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention has the same basic operation, but the highest frequency of the basic operation clock that can operate (hereinafter referred to as CPU type).
The present invention relates to a CPU type discriminating device for a computer system in which multiple types of CPUs having different types can be used.

〔従来の技術〕[Conventional technology]

コンピュータシステムのCPU (中央処理ユニット)
を1〜数個のマイクロプロセッサとして集積する場合、
その動作速度と価格とは一般にトレードオツの関係にあ
る。その場合において、基本的な動作、すなわち大部分
あるいは全部の命令セットが共通であるがクロックの動
作可能な最高周波数が異なるチップを数種類用意し、使
用目的に応じてそれらを選択して用いることがしばしば
行なわれる。この時、CPU周辺のハードウェアとして
は、最小限、基本動作クロックの周波数をユニットの差
し換えによって変更するのみでCPUタイプの変更に備
えることができる。ところが、ソフトウェアとしては使
用目的の差、すなわち、高速処理を要求される110機
器とのデータの入出力を行なうか否かの差を実現しなけ
ればならず、そのためには何らかの手段でCPUタイプ
に関する情報をCPUへ入力してやらなければならない
CPU (Central Processing Unit) of a computer system
When integrating as one to several microprocessors,
There is generally a trade-off between operating speed and price. In that case, it is possible to prepare several types of chips that have the same basic operation, that is, most or all of the instruction set, but differ in the maximum operating frequency of the clock, and select and use them according to the purpose of use. often done. At this time, the hardware surrounding the CPU can be prepared for a change in CPU type by simply changing the frequency of the basic operating clock by replacing the unit. However, as software, it is necessary to realize the difference in purpose of use, that is, the difference in whether or not to input and output data with 110 devices that require high-speed processing. Information must be input to the CPU.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来では、これを実現するために切換スイッチ等の回路
を追加する必要があり、また、クロック周波数の切換の
際には、それと共にこの切換スイッチを変更する操作が
必要であった。
Conventionally, in order to realize this, it was necessary to add a circuit such as a changeover switch, and when changing the clock frequency, it was also necessary to change the changeover switch.

したがって本発明の目的は、そのために回路の変更又は
設定の変更をする必要のないCPUタイプ判別装置を提
供することにある。
Therefore, it is an object of the present invention to provide a CPU type determination device that does not require circuit changes or settings changes.

〔課題を解決するための手段〕[Means to solve the problem]

第1図は本発明に係るCPUタイプ判別装置の原理構成
図である。図において、本発明のCPUタイプ判別装置
は、CPU10のタイプに応じて周波数の変更が可能な
基本制御クロック12と、実時間で動作し該CPU 1
0よりアクセス可能なタイマ14とを具備するコンピュ
ータシステムのためのCPUタイプの判別装置であって
、該基本制御クロック12に基き、該CPU 10の制
御命令からなる所定回数のループを実行するループ実行
手段50と、該タイマ14により該ループ実行手段50
の実行時間を計測するループ実行時間計測手段52と、
実行時間とCPUタイプとの関係を記憶する判別テーブ
ル80と、該実行時間計測手段52が計測した実行時間
と該判別テーブル80内の実行時間とを比較してCPU
タイプを決定するCPUタイプ決定手段54とを具備す
ることを特徴とするものである。
FIG. 1 is a diagram showing the basic configuration of a CPU type discriminating device according to the present invention. In the figure, the CPU type discriminating device of the present invention has a basic control clock 12 whose frequency can be changed according to the type of CPU 10, and a basic control clock 12 that operates in real time.
A CPU type discriminating device for a computer system comprising a timer 14 accessible from zero, the loop execution device executing a predetermined number of loops consisting of control instructions for the CPU 10 based on the basic control clock 12. means 50, and the loop execution means 50 by the timer 14.
loop execution time measuring means 52 for measuring the execution time of;
A determination table 80 that stores the relationship between execution time and CPU type is used to compare the execution time measured by the execution time measuring means 52 with the execution time in the determination table 80 to determine whether the CPU
This is characterized by comprising a CPU type determining means 54 for determining the type.

〔作 用〕[For production]

基本制御クロック12の周波数が変わるとループ実行手
段50の実行時間が変化する。タイマ14は基本制御ク
ロック12の周波数に関係なく実時間を計測することが
できるので、ループ実行時間計測手段52が計測する実
行時間を判別テーブル80内の時間と比較すればCPU
タイプが決定される。ループ実行手段50、ループ実行
時間計測手段52、CPUタイプ決定手段54、及び判
別テーブル80をファームウェアの形で組み込んでおけ
ば、何らの回路の追加なしでかつCPUタイプ変更の操
作の必要のないCPUタイプ判別装置が実現される。
When the frequency of the basic control clock 12 changes, the execution time of the loop execution means 50 changes. Since the timer 14 can measure real time regardless of the frequency of the basic control clock 12, if the execution time measured by the loop execution time measuring means 52 is compared with the time in the discrimination table 80, the CPU
The type is determined. By incorporating the loop execution means 50, the loop execution time measurement means 52, the CPU type determination means 54, and the discrimination table 80 in the form of firmware, the CPU can be used without adding any circuits or requiring any operation to change the CPU type. A type discrimination device is implemented.

〔実施例〕〔Example〕

第2図は本発明に係るCPUタイプ判別装置の一実施例
が組み込まれたコンピュータシステムのブロック図であ
る。
FIG. 2 is a block diagram of a computer system incorporating an embodiment of the CPU type discriminating device according to the present invention.

CPUl0Iは直接アクセス可能なレジスタ102を一
体に集積したマイクロプロセッサより成っている。
CPU10I consists of a microprocessor with integrated directly accessible registers 102.

制御クロックユニット121はCPUl0Iへ制御クロ
ックを供給するもので、cpuiolのタイプに応じて
差し換えが可能である。ROM501には実行時間とC
PUタイプとの関係を表わすデータと後述のソフトウェ
アプログラムとがコード化されて格納されている。 R
AM103には制御のためのデータ及び処理データ等が
格納される。タイマ141は実時間を計測する。これら
のcpυ101 、 ROM501 、 RAM103
、及びタイマ141は相互に内部バス110で接続され
ており、CPUl0Iからその他のユニットがアクセス
可能である。
The control clock unit 121 supplies a control clock to the CPUI0I, and can be replaced depending on the type of CPUIOL. ROM501 contains execution time and C
Data representing the relationship with the PU type and a software program to be described later are encoded and stored. R
The AM 103 stores control data, processing data, and the like. Timer 141 measures real time. These cpυ101, ROM501, RAM103
, and timer 141 are mutually connected by an internal bus 110, and can be accessed by other units from CPU10I.

第3図はROM501に格納され、前述のループ実行手
段50、ループ実行時間計測手段52、及びCPUタイ
プ判別手段54を実現するためのソフトウェアのフロー
チャートである。CPUl0Iが処理を開始すると、初
期処理の形でこれら一連の処理が実行される。まず、タ
イマ14に初期値0が設定され(ステップa)、所定回
数のループを開始する(ステップb)、所定の回数のル
ープが終了したらタイマ14の値を読み込み(ステップ
C)、ROM501内に格納された判別テーブル内の値
と比較する(ステップd)0判別テーブル内にはそれぞ
れのタイプのCPUが前記所定の回数を実行するのに要
する時間が格納されているので、実際のタイマ14の値
からCPUタイプを決定することができる。決定された
CPUタイプを表わすコードをレジスタ102へ格納し
たら(ステップe)、通常の処理へと移行する。
FIG. 3 is a flowchart of software stored in the ROM 501 to implement the loop execution means 50, loop execution time measurement means 52, and CPU type determination means 54 described above. When CPUl0I starts processing, a series of these processes is executed in the form of initial processing. First, the timer 14 is set to an initial value of 0 (step a), a predetermined number of loops are started (step b), and when the predetermined number of loops are completed, the value of the timer 14 is read (step C) and stored in the ROM 501. Compare with the value in the stored discrimination table (step d) Since the time required for each type of CPU to execute the predetermined number of times is stored in the 0 discrimination table, the actual value of the timer 14 is The CPU type can be determined from the value. Once the code representing the determined CPU type is stored in the register 102 (step e), normal processing begins.

〔発明の効果〕〔Effect of the invention〕

以上述べてきたように本発明によれば、回路の変更又は
追加の必要がなく、設定変更の操作の必要のないCPU
タイプ判別装置が提供される。
As described above, according to the present invention, there is no need to change or add circuits, and there is no need to change the settings of the CPU.
A typing device is provided.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の原理構成を表わす図、第2図は本発明
の一実施例におけるハードウェアのブロック図、 第3図は本発明の一実施例におけるソフトウェアのフロ
ーチャート。 図において、 12・・・基本制御クロック、 121・・・II?ilりoツクユニット。 第2
FIG. 1 is a diagram showing the principle configuration of the present invention, FIG. 2 is a block diagram of hardware in an embodiment of the invention, and FIG. 3 is a flowchart of software in an embodiment of the invention. In the figure, 12...Basic control clock, 121...II? illiotsuku unit. Second

Claims (1)

【特許請求の範囲】[Claims] 1. CPU(10)のタイプに応じて周波数の変更が
可能な基本制御クロック(12)と、実時間で動作し該
CPU(10)よりアクセス可能なタイマ(14)とを
具備するコンピュータシステムのためのCPUタイプ判
別装置であって、 該基本制御クロック(12)に基き、該CPU(10)
の制御命令からなる所定回数のループを実行するループ
実行手段(50)と、 該タイマ(14)により該ループ実行手段(50)の実
行時間を計測するループ実行時間計測手段(52)と、 実行時間とCPUタイプとの関係を記憶する判別テーブ
ル(80)と、 該実行時間計測手段(52)が計測した実行時間と該判
別テーブル(80)内の実行時間とを比較してCPUタ
イプを決定するCPUタイプ決定手段(54)とを具備
することを特徴とするCPUタイプ判別装置。
1. For a computer system comprising a basic control clock (12) whose frequency can be changed depending on the type of CPU (10) and a timer (14) that operates in real time and is accessible from the CPU (10). A CPU type discriminating device, comprising: a CPU type determination device based on the basic control clock (12);
loop execution means (50) for executing a predetermined number of loops consisting of control instructions; loop execution time measuring means (52) for measuring the execution time of the loop execution means (50) using the timer (14); A discrimination table (80) that stores the relationship between time and CPU type, and a CPU type is determined by comparing the execution time measured by the execution time measuring means (52) with the execution time in the discrimination table (80). A CPU type discriminating device comprising: CPU type determining means (54).
JP1040320A 1989-02-22 1989-02-22 CPU type identification device Expired - Fee Related JPH0630061B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1040320A JPH0630061B2 (en) 1989-02-22 1989-02-22 CPU type identification device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1040320A JPH0630061B2 (en) 1989-02-22 1989-02-22 CPU type identification device

Publications (2)

Publication Number Publication Date
JPH02220132A true JPH02220132A (en) 1990-09-03
JPH0630061B2 JPH0630061B2 (en) 1994-04-20

Family

ID=12577320

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1040320A Expired - Fee Related JPH0630061B2 (en) 1989-02-22 1989-02-22 CPU type identification device

Country Status (1)

Country Link
JP (1) JPH0630061B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016143402A (en) * 2015-02-05 2016-08-08 富士通株式会社 Timer control device, radio communication device and timer control method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62245338A (en) * 1986-04-17 1987-10-26 Sanyo Electric Co Ltd Software delaying system for data processor
JPS63217425A (en) * 1987-03-06 1988-09-09 Alps Electric Co Ltd Automatic loop adjusting system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62245338A (en) * 1986-04-17 1987-10-26 Sanyo Electric Co Ltd Software delaying system for data processor
JPS63217425A (en) * 1987-03-06 1988-09-09 Alps Electric Co Ltd Automatic loop adjusting system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016143402A (en) * 2015-02-05 2016-08-08 富士通株式会社 Timer control device, radio communication device and timer control method

Also Published As

Publication number Publication date
JPH0630061B2 (en) 1994-04-20

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