JPH02217949A - Input/output controller - Google Patents

Abstract

PURPOSE:To guarantee the simultaneousness of respective trace information of respective I/O controllers by adding common time information when respective I/O controllers trace their own operating state. CONSTITUTION:When a system checking processor(SCP) 202 informs reference time information to the I/O controllers 203, 204 connected to a common bus 200 by multiple address communication, the SCP 202 commands the controllers 203, 204 to correct the time information through an exclusive signal line on the common bus 200. The controllers 203, 204 update the reference time information and time difference information based upon the command. The controllers 203, 204 form current time based upon the new reference time information and time difference information, and at the time of collecting each own trace information in the inside of each controller, the current time is stored in a trace memory as a part of the trace information. Consequently, the simultaneousness of respective trace information of respective I/O controllers can be guaranteed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to input/output controllers for data processing systems, and more particularly to input/output controllers that race to one of their operating states.

BACKGROUND ART Conventionally, in this type of input/output control device, when tracing its own operating state, it has added its own time information or added no time information at all.

Problems to be Solved by the Invention In the data processing system using the conventional input/output control device described above, the trace information held by the input/output control device is different from the trace information held by other input/output control devices in terms of time. Since they are unrelated, it was not possible to guarantee the simultaneity of both trace information.

The present invention has been made in view of the above-mentioned conventional situation,
Accordingly, an object of the present invention is to provide a novel input/output control device that makes it possible to solve the above-mentioned problems inherent in the conventional technology.

Means for Solving the Problems In order to achieve the above object, an input/output control device according to the present invention includes means for receiving basic time information from a common input/output bus, and generating a time difference between the basic time and the current time. and the means for
The device is configured to include means for generating the current time using the basic time information and the time difference, and means for adding the time generated by the current time generating means to the trace information.

Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an input/output control device according to the present invention.

Referring to FIG. 1, the input/output control device 100 of the present invention includes a common input/output bus (hereinafter abbreviated as common bus) 101
It is connected to a central processing unit (hereinafter abbreviated as CPU) and a system monitoring device (hereinafter abbreviated as SCP) (see FIG. 2) via. Input/output control device from CPU
The operation command to too is transmitted to the execution control circuit 103 via the common node 101 and the common bus control circuit 102, and the operation as an input/output control device is executed. The trace control circuit 109 traces the operating state of the execution control circuit 103 and sequentially stores the information in the trace memory 110.

The time information receiving circuit 104 has a common SCP slot.
The received basic time information is once held in the time information receiving circuit 104 and then stored in the basic time register 106 according to a command from the time calibration control circuit 105. When the time calibration control circuit 105 receives a time calibration instruction from the SCP via the common bus, it stores the basic time information received by the time information receiving circuit 104 in advance in the basic time register 106, and also stores the basic time information received by the time information receiving circuit 104 in the basic time register 106. The zero time difference generating circuit 107 to be initialized is a counter circuit that becomes "0" at the time of the initialization and then increments every unit time.

The time correction circuit 108 is a circuit that generates the current time from the basic time stored in the basic time register 106 and the time difference created by the time difference generation circuit 107. The state of the execution control circuit 103 is sequentially stored in the trace memory 1.10 by the trace control circuit 109, and at this time, the current time information generated by the time correction circuit 108 is simultaneously stored in the trace memory 110 along with the state information. .

FIG. 2 is a block diagram showing a configuration example of a data processing system using the input/output control device of the present invention.

Referring to FIG. 2, input/output control devices 203 and 204 + CPU201.5CP202 of the present invention are connected via a common bus 200. Input/output control device 203
and 204 operate according to instructions from the CPU 201, respectively. The 5CP 202 controls the common bus 200 and also manages time information as a system.

Synchronization of time control of each input/output control device can be performed by the following procedure, for example. First of all, the 5CP 202 notifies the input/output control devices 203 and 204 connected to the common bus 200 of basic time information by broadcast communication. Next, the 5CP 202 uses the dedicated signal line on the common bus 200 Instructs to calibrate time information. Input/output control device! 203 and 204 generate part of the basic time information and time difference information according to the instruction.

The input/output control devices 203 and 204 generate the current time based on the new basic time information and time difference information. When collecting its own trace information internally, the current time is stored in the trace memory as part of the trace information.

As described in detail, in the data processing system using the input/output control device of the present invention, the simultaneity of each piece of trace information is guaranteed by adding common time information.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an input/output control device according to the present invention, and FIG. 2 is a block diagram showing an example of the configuration of a data processing system using the input/output control device of the present invention. . 100, 203.204... Input/output control device of the present invention, 1.01.200... Common bus, 102... Common bus control circuit, 103... Execution control circuit, 104...
- Time information receiving circuit, 105... time calibration control circuit 5
106... Basic time register, 107... Time difference generation circuit, 108... Time correction circuit, 109... Trace control circuit, 110... Trace memory. 201... central processing unit (CPU), 202...
...System monitoring device (SCP) Figure

Claims (1)

[Claims] In an input/output control device that is connected to a central processing unit and a system monitoring device via a common input/output bus, and has a function of tracing its own internal operating state, the common input/output means for receiving basic time information from a bus; means for generating a time difference between the basic time and the current time; means for generating the current time using the basic time information and the time difference; and the current time generating means. An input/output control device comprising: means for adding a generated time to trace information.