JPS62117021A - Control method for switching regulator - Google Patents

Abstract

PURPOSE:To prevent the generation of the switching noises and malfunctions, etc. during the address/data processing of a microprocessor, by actuating a switching regulator synchronously with the microprocessor. CONSTITUTION:A voltge-pulse width converter 14 starts its actuation by the switching enable ENSW delivered from a system clock generator 20. Then a counter 22 set in the converter 14 performs a counting action up a prescribed value synchronously with the system clock fSYS. The counting start and end actions are carried out in response to the switching action of a switching regulator within the converter 14 and also synchronous with the system clock fSYS. Thus the switching action of the switching regulator is started synchronously with the fall of the system clock. Then the switching action is through synchronously with the fall of the clock fSYS after a prescribed number of clocks are counted.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for controlling a switching regulator, and more particularly to a method for controlling a switching regulator that controls the operating timing of the switching regulator and prevents noise from entering the system. .

2. Description of the Related Art In an M source circuit attached to a data processing system such as a microprocessor, a switching regulator is used as a device 2 for adjusting an unstable voltage supplied to the system to a stable voltage. A conventional example of such a switching regulator is shown in FIG. This switching regulator uses a pulse width modulation type and chi'a valve control method, and is supplied with unstable human power.
A chopper 1 performs an intermittent or switching operation for this unstable input, a smoothing circuit 2 includes a means for smoothing the chopper output and sending out two stabilized outputs, and a smoothing circuit 2 between the stabilized output and the main voltage. Based on the error output jtV and the error output jtV from the error intensifier 3 and the error amplifier 53 for determining the error, the sleep pressure-vals Ka (V-P・~■) transformation is performed, and the pulse signal generated here is It consists of a voltage-pulse converter 4 that supplies a signal to the chopper as a signal, and a pulse generator 5 that sends a synchronizing pulse signal to the voltage-pulse converter 4.

Then, in synchronization with the clock operation of the pulse generator 5, the voltage -
The pulse width converter 4 operates and the pressure-pulse width converter 4
The efficiency of chopper 1 is changed based on the pulse signal from.

On the other hand, a data processing system (hereinafter referred to as a microprocessor) that obtains a stabilized output from a switching regulator that operates in this manner operates according to basic timing as shown in FIG.

The microprocessor is configured to ('F,@) synchronously with respect to its system clock, and the fifth
As shown in the figure, addresses/data are input/output in synchronization with the system clock, and read/write control signals are created. Within one synchronization of the system clock, there is an interval in which the address/data bus is turned off (indicated by a in Figure 5) and an interval in which it is enabled (indicated by b in Figure 5).
The address/data bus is enabled or turned off by a bus enable signal. The lengths of the off section a1 and the enable section of the address/data bus created by this bus enable signal are, for example, a-250 nS (+1 second).
, b=750 n S.

During the bus-off period, the address bus and data bus between the microprocessor and the peripherals are disconnected and disabled.

In the bus enable period, the microprocessor and peripheral address bus and data bus are connected, and actual data processing is performed.

Problems to be Solved by the Invention However, in such conventional switching regulators, while the microprocessor operates in synchronization with the system clock, the timing of the switches in the switching regulator has nothing to do with the microprocessor. This was done freely using the timing of the pulse generator 5, which was not available. Therefore, there is a problem in that switching noise generated by the switch operation of the switching regulator enters the microprocessor which is in process of processing during the bus enable section, which tends to cause trouble such as malfunction in the microprocessor.

The present invention has been made in view of these conventional problems, and its purpose is to control the operation timing of the switching regulator in relation to the system clock to prevent malfunctions of the data processing system. .

Means for Solving the Problems In order to achieve the above object, the present invention configures the voltage-pulse width conversion means of the switching regulator to be synchronized with the system clock, and provides a switching enable for starting the switching regulator from the system clock generator. , and the switching operation is performed within the bus-off period of the data processing system's operation/assistance timing.

An error output voltage is obtained between the left-side fixed output of the switching regulator for 1 unit and the 41# relative pressure, and a pulse signal for chopper control is generated in the voltage-pulse width conversion means based on this error output voltage. Ru. The voltage-pulse width conversion means is
It has a built-in counter and counts digital signals. The operation of this counter is started by the switching enable signal ENsw sent from the system clock generator, and ends after counting by the number of counts corresponding to the error output voltage. In the next voltage-pulse width conversion operation, the counter starts in synchronization with the switching enable signal ENsw sent from the system clock generator as in the above case, and in synchronization with the system clock, the counter starts this time. Counts only the number of counts corresponding to the error output voltage. In this way, the start and end of the switching operation of the wind pressure-pulse width conversion means are both synchronized with the system clock, so the switching noise accompanying the switching operation occurs during the bus-off period of the bus enable, so the address / Data is not affected and malfunctions do not occur.

Example 1 to 3 are views showing one embodiment of the present invention.

The switching regulator according to this embodiment adopts the pulse width variable A type chopper control method as described in the above conventional example, and includes a chopper 11, a smoothing circuit 12 for smoothing the chopper output, and an erroneous amplifier. 13 and a voltage-pulse width (vpw) converter 14.

A system clock generator 20 is connected to the voltage-pulse width converter 14, and the voltage-pulse width converter 14 is
It is designed to operate under the same conditions that the system operates under. The voltage-pulse width converter 14 is the error amplifier 13
An A-D converter 421 into which the error output voltage from
The counter 22 performs a count-up operation according to the digital output Dout from the A-D converter 21.

The A-D converter 21 creates a digital value corresponding to the analog value that is the error output voltage from the error output voltage converter 13. For example, when the error voltage is high, it is a large number/value, and when it is low, it is a small value. A digital output for each error Narita is output so that it becomes a numerical value. Further, a signal line 23 for supplying a switching enable (ENsw) from the system clock generator 20 is connected to both the A-D converter 21 and the counter 22, and by supplying this switching enable, A-D converter 21 and counter 2
2 starts operating. Further, a signal line 24 for supplying the system clock fsys from the counter 22Kid system clock generator 20 is connected to the counter 22.
The counting operation is performed in synchronization with the system clock. The switching enable ENsw is outputted by the system clock generator 20 at every predetermined synchronization (ie, predetermined system clock interval) Tsw. Then, as the counter 22 counts up, the pulse width P-Wo corresponding to the count value is determined.
It is output in the on period.

Having such a configuration, the system clock generator 20
By the switching enable ENSW output from
Count synchronously.

The start and end of counting in the voltage-pulse width converter 14 correspond to the switching operation in the switching regulator, and since both the start and end of counting are synchronized with the system clock fsys, this is shown in FIG. In light of this, it can be seen that the switching operation of the switching regulator starts in synchronization with the fall of the system clock in the figure, and ends in synchronization with the fall of the system clock fsys after a predetermined number of counts. Become. As mentioned above in connection with FIG. 5, the fall of the system clock fsys is also the timing at which interval a, in which the address/data bus is turned off, begins in the microprocessor; After completing the counting start or end operation by the counter 22, the bus enable and counting operation are set. If you do this, the switching regulator's switching
Even if the switching noise associated with the masterpiece enters the microprocessor, the microprocessor at this time is disconnected from the address bus and data bus and is disabled.
No failures such as malfunctions will occur. When the bus-off period has passed and the bus becomes enabled, the microprocessor performs address/data processing, but at this time, the switching regulator has already finished the switching start or end operation, so switching noise does not enter and malfunctions do not occur. No. By controlling the operation of the switching regulator in this manner, the timing of occurrence of switching noise can be pushed to the microprocessor's bus-off period, and the normal operation of the microprocessor can be completely maintained.

As explained above, according to the present invention, since the switching regulator is operated in synchronization with the system/system in which the switching regulator is installed, that is, the microprocessor, the address/data processing in the microprocessor is improved. It is possible to prevent switching noise from occurring in the circuit, and it is possible to obtain the effect that failures such as malfunction of the microprocessor do not occur.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a switching regulator according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a voltage-pulse width converter incorporated in the switching regulator, and FIG. 3 is a block diagram showing the configuration of a voltage-pulse width converter incorporated in the switching regulator. FIG. 4 is a block diagram showing a conventional example of a switching regulator, and FIG. 5 is a time chart showing the operation of a system to which the switching regulator is installed. 1.11... Chopper, 2.12... Smoothing circuit, 3
．． 13... Error amplifier, 4.14... Voltage-pulse width converter, 20... System clock generator, 21.
...A-D converter, 22...counter.

Claims (1)

[Claims] It is connected to a data processing system and stabilizes the unstable output supplied to this data processing system by a chopper and a smoothing means, and pulses it by a voltage-pulse width converter based on the error voltage obtained from the stabilized output. The switching regulator generates a signal and controls the chopper using this pulse signal.
The pulse width conversion means is connected to a system clock generator so that it operates in synchronization with the system clock, and the switching operation by the chopper can be performed within the bus-off period of the operation timing of the data processing system. A method of controlling a switching regulator.