JPH02216576A - Multi-processor control system - Google Patents

Abstract

PURPOSE:To simplify an IO control program at the time when each CPU executes an input and an output (IO) by loading the same program on plural pieces of processors (CPU), respectively so that each CPU can execute an access directly to each terminal. CONSTITUTION:The same program is loaded on CPUs 20 - 23, respectively, a common memory (CM) 40 and an IO space 41 are connected by a common bus (CB) 10, and to the IO space 41, plural IOs 30 - 32 are connected. At the time of loading a body program from a boot program, all CPUs check an FLG, and the CPU which detects earliest an idle FLG occupies an IO port, and starts a load processing. Other CPUs execute periodical monitoring of the FLg in order to obtain IO information. Each CPU 20 - 23 has all an equal right and can execute an access independently to each IO port.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a multiprocessor control system.

[Conventional technology]

Conventionally, in online real-time systems, input/output terminal devices are attached to specific processors, and communication between each processor and the terminal is performed through the processor to which the terminal device is attached. Ta. Nine, there was a master processor among the multiple processors, and this master processor performed overall control, including troubleshooting of the entire system. Therefore, the programs installed in each processor are different depending on the master processor, the processor directly connected to the terminal, and other processors.

[Problem to be solved by the invention]

In the conventional multiprocessor control method described above, the input/output terminal device is attached to a specific processor, so when a processor whose terminal device is not attached to the terminal communicates with the terminal, Since communication is performed via a processor to which the device is attached, there are disadvantages in that communication with the terminal device is difficult and the program for controlling the communication is complicated.

Furthermore, since there is a master processor in the system, there is a drawback that the fault handling program becomes complex.

Furthermore, since the programs installed on the master processor, the processor to which a terminal is attached, and other processors are different, the initial loading of the installed programs is not easy and the program initial load control program is complicated.

[Means to solve the problem]

In the multiprocessor control system of the present invention, the same program is installed in each of a plurality of processors, and input/output control between each processor and a terminal device is performed using one input/output port for one terminal. Do it in common,
The input/output ports are controlled by one of the following methods: an input information acquisition method without processor designation, an input/output method with processor designation, and an input/output port occupation control method by a processor, depending on the type of terminal and communication mode. It is characterized by the fact that it is carried out using

〔Example〕

Next, the present invention will be explained with reference to the drawings.

First, three methods used for input/output port control of the present invention will be explained.

The first method is a method for acquiring input information without specifying a processor, which is used when processing is completed with one input/output and there is no need to specify a busy processor at the time of input. In this method of acquiring input information without specifying a processor, when input information appears at an input port, each processor competes to receive the input information, and the processor that succeeds in acquiring the input information first receives the input information. Processing and output information is a method that each processor can use freely if the output port is unavailable.

The second method is an input/output method with processor designation, which is used when a process is performed by multiple inputs and outputs, and the same processor must be designated or the processor must be designated in particular. In this input/output method of specifying a processor, the input port receives not only input information (the processor number is added), but each processor monitors the input port and specifies its own processor number. In this method, input information is taken in from the input port only when the output port is empty, and each processor adds its own processor number to set the output information if the output port is empty.

The third method is a method in which a processor takes possession of an input/output port, which is used when it is better to always process input/output information by the same processor. In this method of taking exclusive use of input/output ports by processors, when the system starts operating, each processor competes for the right to use the exclusive use of the input/output ports. continues to use the input/output port until it becomes an obstacle and relinquishes the exclusive use 41, and the processor that is unsuccessful in acquiring continues to monitor whether the exclusive use right is abandoned, and if the exclusive use right is abandoned. This is a method in which the exclusive right to use the input/output port is immediately acquired and the exclusive right to use the input/output port is transferred.

Next, one embodiment of the present invention will be described.

FIG. 1 is a system block diagram showing an embodiment of the multiprocessor control system of the present invention, and FIG. 2 is a diagram showing a detailed configuration example of input/output ports regarding the input/output space in FIG. 1.

As shown in FIG. 1, the multiprocessor system of this embodiment includes a plurality of processors (hereinafter referred to as CPUs) 20, 21,
22, 23, a common memory (hereinafter referred to as CM) 40, and an input/output space (hereinafter referred to as 0 space) 41 are connected to a common bus (hereinafter referred to as CB) I.
The connection is OK, and multiple input/output terminals (hereinafter referred to as l0) 30, 31, and 32 are connected to the IO space 41, and the CPU 2
0. ~23 are each equipped with the same program.

As shown in the taz diagram, the IO space 41 has an input/output port 90 for the input information acquisition method without processor designation, an input/output port 91 for the input/output method with processor designation, and an input/output port 91 for the input/output port occupation method by the processor. and an input/output port 92, and the input/output port 90 is the input port 50. of the input/output terminal device. 60.The output port 51 is the input port of the input/output terminal device. The input/output port 92 is the input port door 0. of the input/output terminal device. It has an exit door 1. 55.75 indicates an exclusive use right flag (hereinafter referred to as FLG), 80.81 indicates a processor number designation display (hereinafter referred to as PN), and 100 indicates an input/output port of the input/output terminal device.

Next, the operation of this embodiment will be explained using FIGS. 1 and 2.

First, the operation of loading a program into the system will be explained.

Therefore, the boot program starts running on its own.

For example, in order to load the main body program, the boot program in CPU2G first uses the FL of input/output port 90.
Check out G55. As a result, if it is vacant, FLG
55 is in use, and acquires exclusive usage rights for the input/output port 90, and executes the loading process of the main program using the input/output port 90 exclusively. If the FLG55 is not empty, another CPU has already started loading the main program, so the FLG55 is periodically checked to wait until the loading process of the current CPU is completed. . All CPUs that have not been able to acquire the exclusive right to use the input/output port 90 continue to check the FLG 55. Then, in the next load process, the CPU that first detects that the FLG 55 is empty acquires the exclusive right to use the input/output port 901C and starts the main program load process. In this way, the main body program is loaded from the machine 030 into each CPU 20, 21, 22, and 23. The main program is CPO
When 20K is loaded, the CPU 20 starts idling while waiting for input information immediately after loading.

Here, after loading the main body program, each CPU 20°21.
The control method for the input/output port 100 of 22.23 will be explained. The CPU 20, which has started idling, starts periodic monitoring of the input/output capos (1030, 31.32K) 90, 91.92 in order to obtain input information.

First, the input/output port 901C is checked periodically, and if the main program is not being loaded, it is checked to see if input information is coming to the input port 50, and if input information is coming. Immediately import and process the input information yourself. Since each CPU periodically checks the input port 50, the input information arriving at 501C first finds this input information and sends it to 90PUK.
It will be further processed. When outputting information related to information input from input port 50, output port 5
1 is checked, and if it is empty, information is output from the output port 51. If the output port 51 is free, any C
PU is free to use this. In addition, this input/output port 90 allows multiple pieces of input/output information to be sent and received, each using a different C.
It is used when there is no problem even if it is processed by PU.

Next, for the input/output port (input/output port) 91, the CPU number that should process the input information monitors the input port 0 and checks whether its own CPN number is specified in PN80. If specified, the input information is read from input port 0 as information addressed to itself. At this time, one's own CPU can be identified by reading the processor number display of the hardware.

Regarding output information, if output port 1 is empty,
Any CPU can freely use output port 1 by setting its own CPU number to PN81K. This input/output port 91 is used when a plurality of pieces of input/output information sent and received need to be processed by the same CPU.

Next, regarding the input/output port 92, immediately after the start of idling, the GC
The FLG 75 is checked, and if it is empty, the FLG 75 is considered to be in use and the input/output port 92 is used exclusively. Similarly, CPUs for which exclusive usage rights could not be obtained are F.
The LG 75 is checked periodically, and if it is in use, a request is made to the CPUK that is exclusively using the input/output port 92 to transfer the exclusive use right. On the other hand, CPs in exclusive use
When U sends a rejection response, the request is made again in the next cycle, but if there is no rejection response, U can immediately take over the right to use the input/output port 92 exclusively. Further, after this, other CPUs that have not been able to acquire exclusive usage rights repeatedly request transfer of exclusive usage rights. However, input/output port 92
The CPU that has acquired the exclusive use right will not give up the exclusive use right it has acquired unless it becomes an obstacle and becomes unable to run. This input/output port 92 is configured so that all input/output information sent and received from the input/output port 92 is on the same C.
Used when processing by PU is better.

As described above, each CPU 20.21. ! 2.23 each input/output port 90°91.23 independently with equal rights.
92, and does not receive instructions from other CPUs. Furthermore, the design of the type of input/output port for input/output information is determined by the nature of the input/output information and the type of terminal.

Next, the control operation of the input/output port 100 when one failure occurs will be explained. For example, if the CPU 21 becomes a failure, the input/output control will be as follows.

However, since other normal CPUs obtain this input information and process it, it is equivalent to performing fault switching 1 alternative processing for the faulty CPU 21.
The input/output port 90 is not affected by the failure of the PU 21. Further, when the failure of the CPU 21 is recovered, the CPU 21 only needs to re-enter the competition for acquiring information on the input port 500 Å. This is equivalent to performing recovery processing regarding the input/output port 90 due to failure recovery of the CPU 21.

Next, regarding the single person output port 91, the input information is
If the faulty CPU21 is specified, this CPU
Input information that specifies 21 cannot be processed. Furthermore, since the input information specifies the CPU, an alternative CPU cannot be expected.

Therefore, the service of the input information specifying the faulty CPU 21 will be interrupted.

Next, regarding the input/output port 92,
The faulty CPU 21 that was exclusively using the input/output port 92 is unable to refuse a request from another CPU for the exclusive use right, so the exclusive use right of the input/output port 92 is regained by another normal CPU. However, as a result of this, the input/output information of the input/output port 920 will be processed by the CPU that has regained exclusive usage rights, and as a result, the fault processing program will not run on the faulty CPU 21. , the normal CPU that has regained exclusive use of the input/output port 92 is automatically switched, and the system configuration of the CPU due to the occurrence of the failure is automatically changed.

Before, when the failure of the failed CPU21 is recovered, the CPU
21 is a normal CPU that exclusively uses input/output port 92
It is only necessary to start requesting K to transfer the exclusive right to use the input/output port 92. This means that recovery processing regarding the input/output port 92 due to failure recovery of the CPU 21 has been performed.

〔Effect of the invention〕

As explained above, in the present invention, the input/output terminal device is a specific processor Ic<<! Because each processor does not have to access input/output terminals via a specific processor, each processor can directly access each terminal, so each processor can access input/output terminals directly. This has the effect of simplifying the input/output control program.

Also, when loading the initial program to each processor,
Since each processor can independently directly access the terminal device fillc and load a program, there is an effect that control of initial loading of a program to a processor is facilitated.

Furthermore, in the multiprocessor control method of the present invention, since there is no master processor, there is no need to perform fault control for the entire system when a processor fault occurs, so there is no need for a fault control program to control faults for the entire system. There is.

In the present invention, since each processor has the same function, when one of the N+1 processors becomes faulty, all the other processors can replace the faulty processor in an N-fold manner. This has the effect of improving the system's failure tolerance.

Further, there is an effect that it becomes easier to create a direct access output control program from each processor to each terminal, a program initial load control program, and a failure handling control program.

[Brief explanation of the drawing]

FIG. 1 is a system block diagram showing an embodiment of the multiprocessor control method of the present invention, and FIG. 2 is a diagram showing a detailed configuration example of input/output ports regarding the input/output space in FIG. 1. 10... Common path (CB), 20, 21, 22
．． 23... Processor (CPU), 30, 31.3
2... Input/output terminal (10), 40...
Common memory (CM), 41... Input/output space (I
O hollow space, 50, 60.70... Input port of input/output terminal device, 51, 61, 71... Output port of input/output terminal device, 55, 75...・Exclusive use right flag (FLG), 80, 81... Processor number designation display (PN), 9G... Input/output port of input information capture method without processor designation,
91... Input/output port of input/output method of processor designated reed, 92-... Input/output port of input/output port occupation method by processor, 100...
...I/O port of an input/output terminal device. Agent Patent Attorney Uchihara Shinkayu 2

Claims (1)

[Claims] The same program is installed in each of a plurality of processors, and input/output control between each of the processors and the terminal device is performed by a single program.
Each of the processors commonly performs one input/output port for one terminal, and the control of the input/output port depends on the type of terminal and the communication mode. 1. A multiprocessor control method, characterized in that the multiprocessor control method is performed using one of a method and a method for a processor to take possession of an input/output port.