JPH02214944A - Bus synchronizing controller - Google Patents

Abstract

PURPOSE:To attain an automatic restart even when an arithmetic means is stopped by a transient noise by transmitting a rerise signal within a fixed time during which the stop time of an arithmetic processing action is allowed. CONSTITUTION:A collation means b collates the coincident state of the arithmetic results of arithmetic means a1 and a2 with each other and stops the arithmetic processing actions of both means a1 and a2 when no coincidence is obtained between both arithmetic results. A restart deciding means e calculates the stop time of the arithmetic processing action from the difference between the coincident time data stored in the memory means d and d' and the coincident preset times obtained from the timepiece means c and c'. Then the means e restarts the operations of both means a1 and a2 when the stop time is kept within a prescribed time. Thus the rerise is automatically secured for a controller when the discordance of collation is produced by a transient noise, etc., and the controller has a down.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention relates to a bus synchronous control device, and in particular, even though the calculation results between both buses are the same, they are collated due to a temporary disturbance. If there is a discrepancy and the arithmetic processing stop time is within a predetermined allowable range, the system can be restarted automatically.

(Prior Art) Conventionally, a bus synchronous type control device has been used in a control device for a device in which control operations must be performed with safety taking priority over everything else.

That is, one input signal (
data) are processed in parallel by two calculators with the same function, and only when the calculation results of the raindrop calculator match, the device is operated with the output data based on the calculation results. There is.

For example, in a railroad crossing control device, a train detection signal from a predetermined approach point before the level crossing is
Two microcomputers connected to a pair of bus lines through a zero unit perform calculations in parallel, and the results of both calculations are monitored using a matching circuit. Only when the results of both calculations match, the calculation is performed. Based on the results, level crossing alarms are sounded and gates are raised and lowered.

Further, when a discrepancy is detected in the verification circuit, it is determined that the level crossing control device is malfunctioning, and the level crossing alarm and the barrier switch function to operate on the safe side. That is, the level crossing alarm continues to sound, and the barrier operates to maintain the lowered state.

(Problem to be Solved by the Invention) However, in the conventional bus-type synchronous control device described above, a verification circuit is used to detect a mismatch, and the system is configured to always work on the safe side. This situation is often caused by so-called temporary disturbances (noise), even though the two calculation results are the same, and is more likely to be due to an inherent failure of the control equipment.

For example, in the case of the above-mentioned level crossing control device, if the signal line is energized and transient noise occurs, and the matching circuit detects a mismatch, even if the two calculation results at the time of detecting the mismatch are the same, , level crossing alarms, etc. are maintained on the safe side, so regardless of the presence or absence of a train, the level crossing alarm will continue to sound and the barrier will remain off.

In such cases, it would have been necessary for staff to go to the scene and reset and start the level crossing control device.

As mentioned above, this invention allows the control device to be automatically restarted (restarted) when the control device goes down due to a mismatch in the verification circuit due to a cause other than the control device's original failure due to transient noise, etc. The purpose is to do so.

(Means for Solving the Problems) The present invention is configured as shown in FIG. 1 in order to achieve the above object. That is, al and a2 are a first arithmetic means and a second arithmetic means, which are respectively provided on a pair of bus lines and perform arithmetic processing on one input data in parallel.

Further, b is a collation means, and both calculation means a1, a2
The arithmetic processing operations of both arithmetic means a1a2 are stopped when the results of the arithmetic operations are matched.

Further, c and c' are first and second clock means, each of which measures the current time.

Further, d and d' are first and second storage means, and the calculation results of both calculation means al and a2 are stored in both clock hands ViC+C.
', and are updated and stored at predetermined time intervals, that is, at every sampling period.

Further, e is a re-startup determination means, and a re-calculation means a1
+ When the arithmetic processing operation of 32 is stopped, the arithmetic stop time is calculated from the time stored in both storage means d, d' and the current time coincident from both clock means c, c'. and, on the condition that the calculation results of both calculation means a1 and a2 match, both calculation means al.

If the a2 a2 arithmetic processing operation stop time is within an allowable predetermined range, the arithmetic processing operation is restarted.

(Operation) In the present invention configured as described above, the first calculation means a1 and the second calculation means a2 perform calculation processing in parallel based on the same input data, and the raindrop calculation results are used by all the collation means. Verified at

When a matching match is detected in the matching means a, the calculation result is output, and when a mismatch is detected, the output of the calculation result is stopped, and both calculation means a
1. The calculation processing operation of a2 is stopped.

Both storage means d and d' store data immediately before the arithmetic processing is stopped, and the time immediately before the stop from both clock means c and c', respectively.

In the restart determination means e, when the arithmetic processing is stopped, the raindrop calculation results stored in both the storage means d and di immediately before the stop are the same, and the raindrop calculation results stored in both the storage means d and d' are the same. The stop time (stop period) of the arithmetic processing operation is calculated from the difference between the matched time data and the matched current time from both counting means c and c'. If the stop time is within a predetermined time period in which the controlled equipment is not affected even if the arithmetic processing operation is restarted, the arithmetic processing operations of both arithmetic means a 1 + a 2 are restarted.

(Example) Hereinafter, the present invention will be explained based on the drawings.

FIG. 2 is a block diagram showing a schematic configuration of an embodiment of the device of the present invention, and the portions surrounded by chain lines and dashed lines indicate characteristic components of the present invention.

In the figure, 1 is an I10 unit, from which a pair of bus lines B1 and B2 extend, and each bus line is connected to a first microcomputer (MPU) corresponding to the first calculation means a1.
) 11 and a first memory 12, and a second MPU 21 and a second memory 22 corresponding to the second calculation means a2 are connected. A bus verification circuit 2 serving as verification means is connected between both bus lines Bl and 82.

Both of these MPU IIs 21 also function as restart determination means e, and are configured to perform arithmetic processing using the respective memories 12 and 22 as main storage devices in which programs with the same contents are stored.

The bus verification circuit 2 is formed from a gate circuit, and includes both MPUI
The configuration is such that output from the I10 unit 1 is permitted only when the calculation results of I and 21 are the same, that is, only when the bus is synchronized.

Each bus line B, , B2 includes a first non-volatile memory 3., which corresponds to the first storage means d and the second storage means d'. The second non-volatile memories 23 are connected to each other, and the first
Clock means C9 first clock circuit 14 corresponding to second clock means C'. A second clock circuit 24 is connected to each.

The above-mentioned volatile memories 13 and 23 are backed up by a battery, for example, so that the stored contents are not lost even if the power is cut off.

Although not shown in the drawings, uninterruptible circuits are also added to both clockwise rotations #114 and #24. In short, the portion surrounded by the chain line in FIG. 2 incorporates a function to cope with a power outage.

A case where the operation of this embodiment having the above-described configuration is applied to a level crossing control device will be explained using the explanatory diagram of FIG. 3 and the control flowchart of FIG. 4.

Now, as shown in FIG. 3, a train entry sensor 33 is installed on the rail 32 a predetermined distance before the level crossing 31, and a train entry sensor 34 is installed on the rail 32 immediately after the level crossing.
is installed.

FIG. 3(a) shows the case where there is no train between the two sensors 33 and 34, and FIG. 3(b) shows the case where there is a train A.

First, before train A is detected by the train approach sensor 33 (at the time shown in FIG. 3 <a)), an input signal to that effect is input to the I10 unit 1. That is, an input signal without train detection is input, and this is the input signal for two bus lines B.
1. It is sent to both MPUs 11.21 via B2. In both MPU IIs 21, arithmetic processing is performed according to the programs in the memories 12 and 22 connected to the respective bus lines. In this case, since there is no train between the rain sensors 33 and 34, the output signal from the I10 unit 1 accompanying the calculation result is a signal that does not activate a level crossing alarm (not shown).

This arithmetic processing operation is repeated every predetermined period, that is, every sampling synchronization. The results for each cycle are stored in the volatile memory 13. through both bus lines Bl and B2.
23 (step 100).

The right side of FIG. 3(a) shows each nonvolatile memory 13 at that time.
．． 23, and the contents of hour 1 minute and second are rewritten every sampling period (step 102 affirmative, 100).

By the way, in this state, for example, each sensor 33.3
Since signal line 4 is energized, noise occurs in the input signal,
When the bus verification circuit 2 detects a mismatch (step 10)
2 negative, 106 affirmative), the matching state of the contents of each non-volatile memory 13, 14 is determined (step 108).

The contents of each non-volatile memory 1323 for which this matching state is judged are the contents immediately before the mismatch was detected, so it is possible that they usually match, or that they do not match due to a malfunction in each non-volatile memory or each clock circuit. In this case, it is unclear which bus line is correct, and it is also possible that both bus lines are incorrect.In other words, the data that is the basis for restarting is incorrect, so both M
The arithmetic operation of the PUlI 21 is stopped one time. In this case, since the level crossing 31 is maintained on the safe side, the level crossing alarm sounds, the barrier is lowered (step 108, negative, 110), and the staff performs recovery work (step 112).

If step 108 is affirmative, that is, if the contents of the volatile memories 13.23 for both years match, the contents of the memories are adopted and the current time is read from the clock circuits 14.24 for both years (step 114). , 116). Note that if the read current times do not match, it means that one or both of the clock circuits is malfunctioning, so in this case, the process moves to step 110 and a similar failsafe is activated.
(Step 118, negative).

When the current times of both clock circuits 14 and 24 match (Yes at step 118), the arithmetic processing stop time is calculated, and it is determined whether the stop time is within a certain time (step 120).

This fixed time is the time (for example, several seconds) required for the train with the least number of connections to pass through each sensor 33, 34 at the maximum speed.

Therefore, as long as the bus comparison circuit 2 detects a mismatch until the current time, that is, within a certain period of time allowed for the arithmetic processing stop time, the train presence/absence shelf in the nonvolatile memory 13.23 is not changed, so both MPUs 11. No problem will arise even if 21 is started again (restarted) to perform arithmetic processing operations. If a train approaches the train approach sensor 33 during the arithmetic processing suspension period, it will be determined that there is a train when restarting, so there is no risk of any problem occurring in this case as well.

Therefore, in step 120, if the arithmetic processing stop time is within the above-mentioned fixed time (step 120 affirmative),
Since the first and second non-volatile memories 13.23 indicate "no train", the operation of the level crossing alarm is not started, and both MPUs 11
．． The arithmetic processing operation of 21 is restarted (step 122 negative, 124.128>).

However, if the calculation processing time exceeds a certain amount of time,
During that period, it is conceivable that the train has passed the train approach sensor 33, so in this case (step 1
20 (No), the process proceeds to step 110 and the activation of the level crossing warning system is started.

On the other hand, as shown in FIG. 3(b), when train A exists between both sensors 33 and 34, when train A passes the train approach sensor 33, the train detection signal is transmitted by this axle (axle).
10 unit 1, and based on this signal, each MPU 1
1.21 is processed and an output signal for activating a level crossing warning device is output from the I10 unit 1.

In this case, steps 100 to 120 are the same as described above, and since it is determined in step 122 that there is a train (Yes in step 122), the level crossing alarm is restarted while continuing to operate (steps 126 and 128). ).

As mentioned above, in this embodiment, both pass lines B,
, B, respectively. The second non-volatile memory 13.23 and the first non-volatile memory 13.23. Since the second clock circuit 14.24 is provided, verification time F! When the arithmetic processing operations of both MPUs 11 and 21 are stopped due to the mismatch detection of &2, the contents written in the rain volatile memory 13.23 immediately before the stop match,
and the written time and both clock circuits 14.24
If the difference from the current time obtained from
, 21 will be restarted.

Therefore, even if the computation results of both MPUs 11 and 21 are the same, the matching circuit 2 detects a mismatch due to transient noise such as a lightning strike, and even if both MPUs 11 and 21 stop operating, the Restarting is performed, and the gA staff is freed from the trouble of having to go to the site and reset and start every time a verification discrepancy is detected.

Moreover, the data that serves as the reference for restarting is obtained separately for each bus line B, B2, and if these data do not match, restarting is not performed, which further improves safety. Can be done.

In the above-described embodiment, the nonvolatile memory and the clock circuit are provided on a pair of bus lines, that is, two storage means and two clock circuits are provided, and the contents of the two storage means match and Although the arithmetic processing stop time is calculated only when the current time of the clock means matches, it is also possible to provide a single storage means and a single clock means.

In this case, the arithmetic processing operation stop time is calculated from the difference between the arithmetic stop time stored in the single storage means and the current time from the single clock means.

(Effects of the Invention) As described above, the present invention provides a bus synchronous control device with storage means and clock means added to each bus line.
When the matching means detects a mismatch and the arithmetic processing operations of both arithmetic means are stopped, the matching time immediately before the stop stored in both storage means and the matching time obtained from both clock means are used. If the difference from the time, that is, the arithmetic processing operation stop time is within an allowable fixed time, a restart signal is sent to both arithmetic means.

Therefore, even if the calculation results of calculation means □ are the same, the comparison means detects a discrepancy due to transient noise such as a lightning strike, and even if both calculation means stop operating, it will automatically restart. This eliminates the trouble of having to go to the site and reset and start the system every time a matching rate is detected.

Moreover, the reference data for restarting, that is, the reference data for calculating the arithmetic processing stop time, is obtained separately from each clock means and storage means provided separately for each bus line. Of course, when the data does not match, restarting is not performed, which has the effect of further improving safety.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing the functions of the device of the present invention, Fig. 2 is a block diagram showing a schematic configuration of the device of the present invention, and Fig. 3 is an explanation for explaining the case where the device of the present invention is applied to a level crossing control device. 4 and 4 are flowcharts showing control operations. 1...I10 unit, 2...Bus verification circuit, 11.21...Ml, M2 microcomputer (M
PU>, 12.22...1st. 2nd memory, 13.23... 1st. Second non-volatile memory, 14.24
...First. Second clock circuit, al, a2...first.
second calculation means, b... collation means, c, c'... first. second clock means, d, d'...first. second storage means; e...restarting determination means; Beta

Claims (1)

[Claims] (a) A first calculation means, a second calculation means, and a collation means,
It has a first clock means, a second clock means, a first storage means, a second storage means, and a restart determination means, (b) the first calculation means and the second calculation means are a pair of (c) The verification means verifies the matching state of the calculation results of both the calculation means, and if the verification results in a mismatch. (d) The first and second clock means are respectively provided on a pair of bus lines to measure the current time; ) The first and second storage means are respectively provided on the pair of bus lines and update and store the calculation results of both the calculation means in relation to the time from the clock means at predetermined time intervals. (f) When the arithmetic processing operation of both the arithmetic means is stopped, the re-starting determination means is configured to check the times stored in both the memory means in agreement and the clock time from the two clock means. Calculate the arithmetic processing stop time from the current time that has been reached, and resume the arithmetic processing operation if the arithmetic processing stop time is within a predetermined range, provided that the arithmetic results of both arithmetic means match. It is a bus synchronous control device.