JPH02213968A - Program down-loading dsp circuit - Google Patents

Abstract

PURPOSE:To surely down-load a program and to protect the program by releasing a DSP (digital signal processor) reset state after confirmation of a write program and at the same time applying again a write protection state to a DSP program RAM. CONSTITUTION:A program down-loading means secures a write enable state to a DSP program RAM 12 with a DSP resetting operation and writes data into the RAM 12 after releasing a write protection state when a DSP program is down-loaded to the RAM 12 from a host CPU 20. The DSP resetting state is released and a write protection state is set again after a write program is confirmed via the read-back check of the written program. As a result, the program is surely down-loaded and protected.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to highly reliable DSP circuit technology, and in particular, it is possible to reliably download and protect a program in a program download DSP circuit, and to monitor the operation of the DSP circuit. The present invention relates to a program download DSP circuit.

[Conventional technology]

DSP (Digital Signal Processor), a one-chip microprocessor dedicated to digital signal processing
The microprocessor has the characteristic of being able to perform arithmetic processing, such as repeated product-sum calculations, which are particularly common in digital signal processing, more than an order of magnitude faster than a general-purpose microprocessor. Conventionally,
A DSP constructed using a DSP with such characteristics
As a circuit, a high-speed program RAM is provided for versatility and miniaturization without arranging a program ROM for the DSPw, and a program is written to this RAM from an external host CPU, and the program written to this RAM is Download the program to operate the DSP according to the DSP
circuit is known.

Furthermore, the failure modes of DSP circuit operation include: (1) interrupt congestion or runaway stack point due to interrupt congestion, (2) locking that results in program runaway or no-response stoppage, and (2) hardware failure. Conventionally, these failure modes have been dealt with by configuring a WDT circuit using a watchdog timer (hereinafter referred to as WDT) to monitor the operation of the DSP circuit.

[Problem to be solved by the invention] However, the above-mentioned Grodarum download DSP
The WDT circuit for monitoring the operation of circuits and DSP circuits has the following problems.

First, since the program of the program download DSP circuit is located on the high-speed RAM, reliability is lower than when using the EpROM in the following respects. In other words, ■ DSP due to noise etc. when loading a program.
A download failure may occur due to a malfunction; ■ A DSP malfunction or program bug may cause DSP program write corruption; ■ A malfunction or program bug in the host CPU of an external system may cause a DSP program to fail. There is a possibility that write corruption may occur.

Further, among the failure modes of the DSP, there are failure modes and problems that cannot be detected by the WDT' circuit. That is, ■ DSP failure cannot be detected if there is a periodic program runaway and the WDT is retriggered; ■ Data RA not related to DSP operation
(1) When an abnormality occurs in the DSP and is detected by the WDT circuit, there is always a detection delay corresponding to the operating time of the WDT circuit.

Therefore, an object of the present invention is to
In the P circuit, a read/write check is performed when downloading a program to the DSP program RAM, and complete write protection is applied to improve reliability.Furthermore, failures can be detected without delay in operation, and periodicity can be prevented. To provide a program download DSP circuit that does not require a WDT circuit and can detect even a certain program runaway and can check the operation up to a data acquisition circuit (indicating a bus, RAM, and buffer circuit) with a host CPU.

[Means to solve the problem]

The program download DSP circuit according to the present invention is a program download DSP circuit that operates by downloading a program from an external post CPU to a DSP program RAM, and cancels write protection by applying a DSP reset from an external host CPU. program download means for canceling the DSP reset after writing a program after setting the DSP program RAM to a write enable state and performing a readback check of the written program; and a program download means provided on the DSP data R and AM. The DSP writes a predetermined set code to the monitoring register when the DSP interrupt processing is completed, and the set code is readable from the monitoring register when the DSP data RAM is accessed from an external host CPU. At the same time as checking the external host CP
and DSP circuit operation monitoring means for writing a reset code from U to the monitoring register and performing a readback check to verify the reset code.

[For production]

According to the program download DSP circuit according to the present invention, the program download means:
DS from host CPU to DSP program RAM
When downloading a program for P, enable writing to the DSP program RAM with a DSP reset, release the write protection, and then check the written program by reading back the written program. After that, the DSP reset is canceled and write protection is performed again, so programs can be downloaded and protected reliably.

In addition, the DSP circuit operation monitoring means sends a predetermined set code written at the end of interrupt processing to a monitoring register provided at the top of the DSP data RAM.
When the host CPU accesses the DSP data RAM, it checks whether it can read data, forcibly writes a reset code to the monitoring register, and immediately verifies the reset code by a readback check, so the DSP circuit Operation failure and host CPU
It is possible to detect malfunctions in the data acquisition circuit.

〔Example〕

Next, an embodiment of the program download DSP circuit according to the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a block diagram of a highly reliable program download DSP circuit showing one embodiment of the present invention. In FIG. 1, reference numeral 10 indicates a DSP, and the DSPIO is connected to a program RAM 12, a data RAM 14, and a data bus buffer 18 via a data bus line 16. The host CPU 20 is connected to the data bus buffer 18, ROM 22, and control register 24 via a pass line 28, and is also connected to a write terminal W of the host CPU 20 and one input terminal of an AND gate 26 for write protection. The reset signal output terminal of the control register 24 is connected to the other input terminal of the write protection AND gate 26 via a line 30, and also to the reset terminal RST of the DSPIO. Note that several external write output terminals (not shown) are also connected to one input terminal of the AND gate 26 for light protection. Further, the output terminal of the write protection AND gate 26 is connected to the write terminal WT of the program RAM 12 via a line 32.

Program download DSP with this configuration
The program download operation in the circuit will be explained below.

First, the host CPU 20 issues a command to the control register 24 via the pass line 28 to reset the DSPIO, and based on this, the control register 24 sends a reset signal to the DSPI via the line 30.
It is output to the reset terminal RST of PIO and the AND gate 26 for write protection. At the same time that the DSPIO is reset, the gate of the AND gate 26 for write protection is opened by this reset signal, and the write signal from the host CPU 20 etc. connected to one input terminal of the AND gate 26 for write protection is programmed. It is input to the write terminal WT of the RAM 12.

In other words, the write protection is canceled and
Since the DSPIO has been reset, it is reliably disconnected from the data bus buffer 16. In this state,
The host CPtJ20 stores the DSP program in the ROM22.
The DSP program is read from the data bus buffer 18 and downloaded to the program RAM 12. After downloading, the host CPU 20 immediately writes the program to the program RAM 1.2, checks the readback of the SP grodaram, and issues an order to the control register 24 to release the reset signal.
By canceling this reset signal, the gate of the AND gate 26 for write protection is closed, and the program RAM
Write protection is applied to prevent external writing to 12. At the same time, the DSPIO reset signal is also released, so the DSPIO enters DSP initial processing without delay and performs high-speed digital signal processing according to the DSP program stored in the program RAM 12.

Next, regarding the operation monitoring of the DSP circuit in this embodiment,
This will be explained using FIGS. 2 and 3. FIGS. 2 and 3 are explanatory diagrams showing an outline of the monitoring method.

First, after each interrupt processing, the DSPIO
Write a predetermined set code to the check flag register 34, which is a monitoring register on the data RAM 14 (
Figure 2(a) #see).

Next, when the host CPU 20 accesses the data RAM 14 for DSP data transfer, the following processes 1 to 2 are performed simultaneously with the data transfer.

(2) The host CPU 20 reads the check flag register 34 on the data RAM 14 and checks whether a set code is contained (see FIG. 3(b)).

■ From the host CPU 20 to the data RAM 14
A reset code is forcibly written into the y cutlug register 34 (see # in FIG. 3(C)).

(2) The host CPU 20 immediately reads the check flag register 34 again and verifies whether the reset code has been written (see FIG. 3(d)).

In the above processing, if there is an abnormality, it can be determined that it is either a failure of the DSPIO or an abnormality in the data exchange circuit with the host CPU 20.

〔Effect of the invention〕

As is clear from the embodiments described above, according to the present invention,
External system host CP to DSP program RAM
When downloading a program from U, the write protection for the DSP program RAM is canceled at the same time as the DSP is reset, and the written program is immediately read back checked and the written program is confirmed before being transferred to the DSP. By configuring the DSP program RAM to be write-protected again when the reset is released, the program can be downloaded reliably and protected, and the reliability of the program download DSP circuit can be improved.

In addition, by configuring the system to perform read/write checks between the DSP and the host CPU on the monitoring register provided on the DSP data RAM, the conventional WDT circuit can omit the DSP operation monitoring, and errors can be detected immediately without any detection delay. In addition, it becomes possible to detect data RAM malfunctions and periodic program runaways, which greatly contributes to improving reliability.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to the above embodiments, and it goes without saying that various design changes can be made without departing from the spirit of the present invention.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a program download DSP circuit according to the present invention, and FIG. 2 shows an outline of a monitoring method according to the present invention. FIG. 3 is an explanatory diagram showing set code writing, and FIG. 3 is an explanatory diagram showing an outline of the monitoring method according to the present invention and showing signal exchange between the monitoring register on the data RAM and the host CPU. 10...D S P 12...Program RAM14...Data RAM 16...Data bus line 18...Data bus buffer 20...Host CPU 22...ROM24...
・Control register

Claims (1)

[Claims] (1) External host CPU in DSP program RAM
In a program download DSP circuit that operates by downloading a program from an external host CPU, write protection is released by applying a DSP reset from an external host CPU, the DSP program RAM is set to a write enable state, and then a program is written. a program download means for canceling the DSP reset after performing a readback check;
When the SP interrupt processing is completed, the DSP writes a predetermined set code, and the external host CPU
A DSP that checks that the set code can be read from the monitoring register when accessing the data RAM for use, writes a reset code from an external host CPU to the monitoring register, performs a readback check, and verifies the reset code. A program download DSP characterized by being equipped with circuit operation monitoring means.
circuit.