JPH02211550A - Information processing system - Google Patents

Abstract

PURPOSE:To prevent an external disturbance by nulifying a replay signal from another device to a request when a maintenance diagnostic processor is automatically re-started. CONSTITUTION:When a fault is detected by an error detecting circuit 24 of a maintenance diagnostic processor 2 after the processor 2 sends a main storage request through a system controller 1 to a main storage device 3, an error report signal is sent from the circuit 24 through a signal line 124 to an initialization control part 25, the signal is sent through a signal line 117 to a flip flop FF 17, and the FF 17 is set. Thus the processor 2 is automatically started and activated by the control part 25, and a request control part 20, a maintenance diagnostic control part 23, a reply control part 21 and an inter- processor communication receiving part 22 are initialized. When the reply signal to the main storage request is inputted to the controller 1 before the fault is detected, it is nulified by an AND gate 13, and it is not inputted to the processor 2. Thus the external disturbance against the automatic re-starting can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing system, and more particularly to a request control method when a maintenance diagnosis processor provided in the information processing system is automatically restarting.

In recent years, the reliability of information processing systems has been rapidly improved, even in systems with large numbers of gates such as large computers and supercomputers, and there is a tendency to place equal importance on system performance.

Along with this, the role of the system maintenance/diagnosis processor has increased, and the amount of hardware for this maintenance/diagnosis processor has also increased.

As a result, the probability that a failure will occur inside the maintenance diagnostic processor is increasing, and unlike the early information processing systems that were used in early information processing systems, if a failure occurs inside the maintenance diagnostic processor, it is no longer possible to stop operating the system. The situation has become such that it is no longer acceptable to use a fault handling method that causes the system to go down.

Therefore, in recent information processing systems, more and more systems are adopting a failure handling method in which when a failure occurs inside the maintenance diagnosis processor, only the maintenance diagnosis processor is placed in a failed state and automatically restarted. .

In this failure handling method, when a failure occurs in the maintenance diagnosis processor, information essential for retrying is saved in a normal storage device, and the maintenance diagnosis processor is initialized and restarted to a state where it can be retried. The configuration is such that a retry is made using the saved information after this occurs, and during this time the maintenance diagnosis of the system by the maintenance diagnosis processor is interrupted.

Most maintenance diagnostic processors, such as arithmetic processors and system control processors, have only a few main memory access and interprocessor communication functions, but these functions are not exclusive to the maintenance diagnostic processor; If a failure is detected immediately after issuing a request to access the main memory and automatic restart is initiated, there is a drawback that the reply signal from the main memory cannot be sufficiently processed.

Another disadvantage is that when the maintenance diagnosis processor is automatically restarted, it is not possible to process inter-processor communication requests from other devices to the maintenance diagnosis processor.

These drawbacks are serious problems that cause problems in information processing systems.

OBJECTS OF THE INVENTION The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional ones, and is capable of preventing disturbances to the automatic restart of the maintenance diagnostic processor. An object of the present invention is to provide an information processing system that can process an inter-processor communication request issued from another device when the device is automatically restarted.

Composition of the Invention An information processing system according to the present invention is an information processing system having a maintenance diagnosis processor capable of automatically restarting when an internal failure occurs, wherein when the maintenance diagnosis processor is performing automatic restart, the automatic restart is possible. disabling means for disabling a reply from another device to a request issued by the maintenance diagnostic processor before restarting; and disabling the maintenance diagnostic from the other device while the maintenance diagnostic processor is performing the automatic restart. The present invention is characterized by providing a holding means for holding an inter-processor communication request sent to a processor.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. Controls access and communication between these processors, respectively.

The main memory request control unit 10 of the system control device 1 determines that if the request inputted from the maintenance diagnosis processor 2, the arithmetic processor 4, and the system control processor 5 via the signals 11102 to 104 is a main memory request,
The request is buffered and the main memory request is sent to the main memory device 3 via the signal line 100.

Further, when the main memory request control unit 10 receives a reply signal from the main memory device 3 in response to the main memory request via the signal line 101, the main memory request control unit 10 sends a signal ¥Q10 according to the request source.
The reply signal is outputted to the maintenance diagnosis processor 2, the arithmetic processor 4, and the system control processor 5 via the processors 5 to 107.

Further, if the request inputted from the maintenance diagnosis processor 2, the arithmetic processor 4, and the system control processor 5 is an inter-processor communication request, the request is directly sent to the inter-processor communication control unit 11 via the signal line 108.

The inter-processor communication control section 11 sends signal lines 109 to 109 to the maintenance diagnosis processor 2, arithmetic processor 4, or system control processor 5 corresponding to the communication destination code of the inter-processor communication request sent from the main memory request control section 10. 111 to send an interprocessor communication request.

An inter-processor communication request from the inter-processor communication control unit 11 to the maintenance diagnosis processor 2 is input to the OR gate 12 via the signal line 111.
The output signal from the flip-flop 16 is inputted via the flip-flop 5. The OR gate 12 takes the OR logic of these signals and outputs the result to the AND gates 14 and 15 through the signal line 114, respectively.

And gate 13 is a signal! A reply signal from the main memory request control unit 10 to the maintenance diagnosis processor 2 is inputted via the flip-flop 1105.
7 is off, it is sent to the maintenance diagnosis processor 2 via the signal line 112.

AND gate 14 is connected to OR gate 1 via signal line 114.
2 (interprocessor communication request) is input, and the output signal from the OR gate 12 is sent to the maintenance diagnosis processor 2 via the signal line 113 only when the flip-flop 17 is off.

AND gate 15 is connected to OR gate 1 via signal line 114.
2 (interprocessor communication request) is input, and the output signal from the OR gate 12 is output to the flip-flop 16 via the signal line 116 only when the flip-flop 17 is on.

The flip processor 116 holds the output signal (interprocessor communication request) from the AND gate 15 input via the signal 111116 for only one machine cycle.

Flip 70 knob 17 is set by a signal, an error report signal from maintenance diagnostic processor 2 inputted on line 117, and reset by a reset signal from maintenance diagnostic processor 2 inputted via signal line 118.

That is, the flip-flop 17 displays that automatic restart is being executed due to the occurrence of an internal failure in the maintenance/diagnosis processor 2, and the contents of this flip-flop 17 are output to the AND gates 13 to 15 via the signal line 119. be done.

The maintenance diagnostic processor 2 performs maintenance diagnostic control on the system control device 1, main storage device 3, arithmetic processor 4, and system control processor 5, respectively.

Furthermore, like the other arithmetic processors 4 and system control processors 5, the maintenance/diagnosis processor 2 is also capable of accessing the main storage device 3 and inter-processor communication with other processors.

The request control unit 20 of the maintenance diagnosis processor 2 controls the issuance of read/write requests to the main storage device 3 and inter-processor communication requests to the arithmetic processor 4 and system control processor 5, and sends these various requests through the signal line 102. The data is sent to the system control device 1 via the host computer.

The reply control unit 21 receives a reply signal from the main storage device 3 via the system control device 1 and the signal line 112 when the request control unit 20 issues a main storage request, and processes it.

The inter-processor communication receiving unit 22 receives a 10-processor communication request from the arithmetic processor 4 or the system control processor 5 via the system v control device 1 and the signal line 113, and processes it.

The maintenance diagnosis control unit 23 is a central function of the maintenance diagnosis processor 2, and executes maintenance diagnosis for the system control device 1, main storage device 3, arithmetic processor 4, and system control processor 5.

The diagnostic system path from the maintenance diagnosis control unit 23 to the system control device 1, main storage device 3, arithmetic processor 4, and system control processor 5 is connected to a reset signal to the flip-flop 17 of the system control device 1. Not shown except for a signal line 118 for outputting.

Further, a reset signal to the flip 70 knob 17 is issued at the timing when the initialization control section 25 completes initialization of the maintenance diagnosis control section 23.

Error detection time &@24 includes internal data of the request control section 20, internal data of the reply control section 21, internal data of the inter-processor communication reception section 22, and maintenance diagnosis control section 2.
3 are inputted via signal lines 120 to 123, respectively, and these internal data are checked.

When an error is detected by checking this internal data, an error report signal is output to the initial setting control unit 25 via the signal line 124 to notify the detection of the error,
An error report signal is output to the flip-flop 17 of the system control device 1 via the signal M&117.

The initial setting control unit 25 is normally used when starting up the system, but when it receives an error report signal from the error detection circuit 24 via the signal line 124, it starts up the maintenance diagnostic processor 2 again, Initial setting control signals are output to the request control section 20, the reply control section 21, the inter-processor communication receiving section 22, and the maintenance diagnosis control section 23 via the signal line 125 to initialize each section.

Therefore, if a failure occurs in the maintenance/diagnosis processor 2, it is configured to automatically start up again.

Arithmetic processor 4 executes an arithmetic program and connects signal line 1
It sends requests such as access to the main storage device 3 and inter-processor communication with other processors to the system control device 1 via the signal line 103, and receives a reply signal in response to the request from the system control device 1 via the signal line 106. .

Further, the arithmetic processor 4 receives received data and control signals for inter-processor communication from the system control device 1 via the signal line 109.

The system control processor 5 is a system management program (
OS program), etc., and sends requests such as access to the main storage device 3 and inter-processor communication with other processors to the system control device 1 via the signal line 104, and sends a reply signal in response to the request to the signal @ 1
07 from the system control device 1.

Further, the system control processor 5 receives received data and control signals for inter-processor communication from the system control device 1 via the signal line 110.

FIGS. 2 and 3 are time charts showing the operation of one embodiment of the present invention. The operation of one embodiment of the present invention will be explained using these FIGS. 1 to 3.

First, as shown in FIG. 2, after the maintenance diagnosis processor 2 sends a main memory request to the main memory device 3 via the system control device 1, a failure is detected by the error detection circuit 24 of the maintenance diagnosis processor 2. and error detection circuit 24
An error report signal is sent to the initial setting control unit 25 via the signal line 124, and an error report signal is also sent to the flip-flop 17 of the system control device 1 via the signal line 117, so that the flip-flop 17 is set. Ru.

As a result, automatic restart is activated by the initial setting control section 25 in the maintenance diagnosis processor 2, and the request control section 20, reply control section 21, and inter-processor communication receiving section 2
2 and the maintenance diagnosis control section 23 are initialized by the initial setting control section 25, respectively.

At this time, when a reply signal from the main storage device 3 is input to the system control device 1 in response to the main memory request sent to the main storage device 3 before the failure is detected by the maintenance diagnostic processor 2, the system control device 1 Since the flip-flop 17 is set, the reply signal is invalidated by the AND gate 13.

Therefore, when automatic restart is being performed in the maintenance diagnostic processor 2, even if a reply signal is sent from the main storage device 3 in response to a main memory request sent before the automatic restart, the reply signal is is invalidated by the system control device 1 and is therefore not input to the maintenance diagnosis processor 2.

Further, as shown in FIG. 3, when a failure is detected in the error detection circuit 24 of the maintenance diagnosis processor 2,
When the automatic restart is activated by 5 and the initial settings of each part are being performed, when an inter-processor communication request is issued from the arithmetic processor 4 to the maintenance/diagnosis processor 2, the inter-processor communication request is processed by system control. The process is suspended until automatic restart in the maintenance diagnostic processor 2 of the device 1 is completed.

That is, in the system control device 1, since the flip-flop 17 is set when a failure is detected in the maintenance diagnosis processor 2, the AND gate 14 prevents the inter-processor communication request from being sent to the maintenance diagnosis processor 2. At the same time, the OR gate 12, the AND gate 15, and the flip-frog 16 hold the state until the flip-frog 17 is reset.

When automatic restart is completed in the maintenance diagnosis processor 2, a reset signal is sent from the maintenance diagnosis control unit 23 to the flip-flop 17 via the signal line 118, and the flip-flop 17 is reset.

As a result, the inter-processor communication request from the arithmetic processing unit 4 is sent to the maintenance diagnosis processor 2 via the AND gate 14, and is processed in the maintenance diagnosis processor 2.

In this way, when the maintenance diagnosis processor 2 is automatically restarted, the system control unit sends a reply signal to the maintenance diagnosis processor 2! 1 and gate 13
While the maintenance diagnostic processor 2 is automatically restarting, the arithmetic processor 4
By suspending inter-processor communication requests from other 10 setters such as the system control processor 5 and the system control processor 5 to the maintenance diagnosis processor 2 by the OR gate 12, AND gate 15, and flip-flop 16 of the system control device 1, Disturbances to automatic restart of the processor 2 can be prevented.

Furthermore, even if another processor issues an inter-processor communication request to the maintenance diagnosis processor 2 during automatic restart of the maintenance diagnosis processor 2, the request is suspended by the OR gate 12, AND gate 15, and flip-flop 16 of the system control device 1. Therefore, the communication request between the 10 processors can be processed in the maintenance diagnosis processor 2 after automatic restart without affecting other processors.

As explained above, according to the present invention, when the maintenance diagnosis processor is automatically restarting, the request issued by the maintenance diagnosis processor is processed from another device before the maintenance diagnosis processor automatically restarts. By disabling the reply signal and suspending inter-processor communication requests from other devices to the maintenance diagnosis processor while the maintenance diagnosis processor is automatically restarting, the maintenance diagnosis processor can be automatically restarted. This has the effect that it is possible to prevent disturbances to the startup, and that inter-processor communication requests issued from other devices when the maintenance diagnostic processor is automatically restarting can be processed after the automatic restart. be.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention, and FIGS. 2 and 3 are time charts showing the operation of one embodiment of the present invention. Explanation of symbols of main parts 1...System control device 2...Maintenance diagnosis processor 10...Main memory request control unit 11...
... Inter-processor communication control unit 12 ... OR gate 13N15 ... AND gate 16.17 ... Flip-flop 23 ...
...Maintenance diagnosis control section 24...Error detection circuit 25...Initial setting control section

Claims (1)

[Claims] (1) An information processing system having a maintenance diagnostic processor that can be automatically restarted due to the occurrence of an internal failure, when the maintenance diagnostic processor is automatically restarting,
a disabling means for disabling a reply from another device to a request issued by the maintenance diagnosis processor before performing the automatic restart; An information processing system comprising: a holding means for holding an inter-processor communication request sent from the apparatus to the maintenance/diagnosis processor.