JPH02210928A - Synchronous data transfer system and data processing system - Google Patents

Abstract

PURPOSE:To prevent production of overhead and to speed up data transfer by providing a multiple period clock generating means generating a clock whose period is a multiple of that of a basic clock so as to use the clock with a multiple period for the select condition of a data. CONSTITUTION:A basic clock 100 outputted from a clock unit 1 is inputted to a transmission and a reception unit 2, 3 via in put drivers 20, 30. Then a clock frequency divider circuit 31 of the unit 3 outputs a multiple period to the unit 2 as an external signal line clock 102 via an output driver 35. Then a transmission data 105 whose period is a multiple of that of the clock 100 generated in the inside of the unit 2 is valid at the leading edge of the clock 100. Thus, the unit 3 receives the data having a multiple period clock being an output of the circuit 31 inputted via an input driver 32 as the select condition of a selector 33 as a data input of a reception register 34. Then the overhead at the time of inputting to the transmission register and at the time of outputting from the reception register is prevented to speed up the transfer speed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a synchronous data transfer method between logical units that share a clock source in a system, and a data transfer method that can perform data transfer using such a method. Relating to data processing systems.

[Conventional technology]

As described in Japanese Unexamined Patent Application Publication No. 62-204359 "Synchronous Data Transfer Method", conventional devices use clock inputs for the transmitting register and receiving register to control the delay required for data transfer between the transmitting register and the receiving register. It was a device that gave a clock determined by time.

That is, in the conventional technology, in a data processing system consisting of a plurality of logical units that share a clock source, in a synchronous data transfer method in which data is transferred from a transmitting register of one logical unit to a receiving register of another logical unit, Transfer delay time adjusting means for adjusting a maximum value and a minimum value of a transfer delay time required for data transfer between the transmitting register and the receiving register, and making the transfer delay time larger than a transfer cycle time; The device is characterized by comprising a data holding buffer provided between the receiving register and storing data in the middle of transfer when the clock is stopped.

[Problem to be solved by the invention]

By the way, as the operating frequency of microprocessor systems has increased in recent years, as well as become highly integrated and large-scale, the delay time of the output driver has increased when receiving and passing control signals between multiple LSIs that constitute each logic unit. There is a growing need for data transfer from a low-speed process LSI with a high operating frequency to a high-speed process LSI with a short output driver delay time that can support the speed of a microprocessor with a high operating frequency.

The delay time of the gate inside the LSI is sufficiently small compared to the delay time of the output driver. Therefore, the LS on the sending side
The internal operating frequency of both I and the LSI on the receiving side is often the same as the high-speed operating frequency of the microprocessor.

Depending on the operating frequency of the microprocessor, the control signals output from the microprocessor cannot be handled synchronously.
Since SI devices are not acceptable in terms of system performance, the condition that the delay time of the output driver is small is as follows.
Required. Therefore, the output driver's delay time is determined to be a high-speed process LSI or a low-speed process LSI, depending on whether the delay time of the output driver is smaller than the operating cycle of the microprocessor.

In the conventional technology, both the clock input of the transmission register on the transmitting side and the 0 clock input of the +im register on the receiving side,
A divided clock with a frequency multiplied by the microprocessor's operating cycle determined by the delay time of the output driver of the low-speed process on the transmitting side was provided. death.

However, since the internal operating cycle of both the transmitting-side LSI and the receiving-side LSI is the same as the operating cycle of the microprocessor, each has the following problems.

That is, on the transmitting side, transmission data cannot be sent directly to the m register. Therefore, it is necessary to pass the data through a register with a reverse phase clock.

Furthermore, on the receiving side, the received data from the receiving register cannot be used as is within the receiving unit.

Therefore, it was necessary to pass through a resistor of opposite phase. Therefore, there is a problem in that an overhead of one crotter cycle occurs before the transmission data is generated and can be used as reception data.

An object of the present invention is to provide a synchronous data transfer method that eliminates this overhead and easily realizes a microprocessor system with a high operating frequency.

Another object of the present invention is to provide a data processing system that can transfer data between logical units at high speed and without creating any overhead.

[Means to solve the problem]

The present application provides the following invention as a means to achieve the above object.

The invention of the present application, @1, is a synchronization method for transferring data from a transmitting register of one logical unit to a receiving register of another logical unit in a data processing system consisting of a plurality of logical units that share a basic clock supplied from a clock source. In the formula data transfer method, a selector that selects the transmitted data according to the select condition is placed before the transmit register, and a selector that selects the received data according to the select condition is placed before the receive register, and the output of the low-speed process on the transmitting side is placed. A multiplication cycle clock generating means is provided for generating a clock with a multiplication period of the basic clock determined by the delay time of the driver. It is characterized in that data is transferred in all four cases using a periodic clock as a selection condition.

A second invention of the present application is a data processing system comprising a plurality of @processing units that share a basic clock supplied from a clock source and transferring data between the data processing units, the data processing system comprising a transmission register and an output driver. and in the stage before the transmission register of the logic unit that transmits data,
A selector that selects transmit data according to select conditions is placed, and it has an input driver and a receive register, and a selector that selects receive data according to select conditions is placed before the receive register that receives data. Multiplying cycle clock generating means is provided for generating a clock with a multiplication cycle of the basic clock determined by the delay time of the output driver of the process, the basic clock is applied to the clock inputs of the transmitting register and the receiving register, and each selector has the following functions: It is characterized in that data is transferred by giving a clock with a frequency multiplied by the basic clock as a condition.

In each of the inventions described above, the multiplication period clock generation means can be constituted by, for example, a clock frequency division circuit that divides the frequency of the basic clock.

Further, this multiplication period clock generation means can be provided as a separate and independent unit from the logic unit that requires the multiplication period clock.

Furthermore, each of the logical units constituting the system has one
It can be configured with a chip IC.

As described above, in the synchronous data transfer method according to the present invention, the frequency of the microprocessor and the base clock are applied to the clock inputs of the transmit register and the receive register, and
The selection condition is a clock with a multiplication period of the basic clock determined by the delay time of the output driver of the low-speed process on the transmitting side between the transmit data and the transmit register, and the transmit data is given to one of the select data, and the output of the output register is applied to the other. Further, similar means is provided immediately before data input to the receiving register.

[Effect]

In the synchronous data transfer method of the present invention, a selector for selecting transmission data according to a selection condition is arranged before the transmission register, and a selector for selecting reception data according to the selection condition is arranged before the reception register. A clock with a frequency multiplied by the basic clock determined by the delay time of the output driver of the low-speed process on the transmitting side is given to the selector.

Furthermore, a basic clock is applied to the a-c inputs of the transmitting register and the receiving register. As a result, the transmit register and the receive register each operate with the basic clock.

Here, on the transmitting side, transmission data is selected using a clock with a multiplication period corresponding to the delay time of the output driver of the low-speed process on the transmitting side, and is input to the transmitting register to transfer the data. On the other hand, on the receiving side, data sent with a delay is selected using a clock with a multiplication period corresponding to the delay and is input to a receiving register.

That is, in the present invention, a clock with a multiplication period of the basic clock is not given as a clock input to the transmitting register and the receiving register, but is given as a selection condition for transmitting and receiving data, and the clock is not input manually to both the transmitting register and the receiving register. Therefore, the overhead that occurs between the transmit data and the transmit register, and between the receive register and the receive data does not occur.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a synchronous data transfer method according to the present invention and a block diagram of a data processing system that transfers data using this method.
This is a diagram.

This data processing system includes a clock unit l;
The transmitting 4N unit 2 and the receiving unit 3 constitute the main part thereof.

The clock unit 1 includes a clock excavator 1o and a clock frequency divider circuit 11.

The transmitting unit 2 is a low-speed LSI, and includes input drivers 20 and 25, a register 21 and a register, an AND-OR circuit 22, and an output driver 24.

The reception unit 3ti is a high-speed LSI and includes input drivers 30 and 32, a clock frequency divider circuit 31, a selector 33 composed of an inverter 33a and an AND-OR circuit 33b, a reception register 34, and an output driver 35. It is made up of.

In the synchronous data transfer method configured in this way,
For example, the transmitting unit 2 is a CMOS process LSI.
The reception unit 3 is a B1-CMOS process LSI, and the reception unit 1 is a crystal oscillator and T
It is TL.

Next, the operation of the system shown in FIG. 1 will be described with reference to the time chart of FIG. 2, taking as an example the data transfer process in which the present invention is effective.

First, the basic clock 100 output from the clock frequency dividing circuit 11 of the clock unit 1 is input to the transmitting unit 2 through the input driver 20, and to the receiving unit 3 through the input driver 30.

Here, the clock frequency divider circuit 31 is assumed to be a frequency divider circuit, assuming that the maximum time 'l'max of the delay time T of the output driver bus is in the range of 1 to 2 times the basic clock period. A frequency divider circuit output 101 is output. In addition, 3
If the frequency is in the range from twice to four times, it becomes a divide-by-four circuit.

The output driver 35 of the receiving unit 3 has an output delay time of less than l clock periods. In other words, tma in the figure
If x is less than the fundamental clock period and the external (1 upper edge clock 102) crosses the unit,
Data is entered into the register 21 via the . In response to this, the register 21 obtains a Q output 103 and a Q output 104 synchronized with the phase of the basic clock 100.

Transmission data 105 generated inside the transmission unit 2
if, the period is twice that of the basic clock 100, and it is valid at the rising edge of the basic clock 100. In FIG. 2, when the output 104 is 1H, the first data DO passes through the AND-OR circuit 22 and becomes the data input for the 1M register. At the next rising edge of the basic clock 100, the Q output 103 becomes l. Since the HPIQ output 104 becomes L'', the Q output of the transmission register 23 becomes its own data input. Therefore, the Q output of the transmission register n is held for two cycles of the basic clock 100.

The delay time of the output driver 24 is from Tm1n to Tmax
is within the range of Therefore, the external signal line data 106 is T
It does not have a valid value in the range from m1n to Tmax.

On the receiving unit 3 side, the data received via the input driver 32 is sent to that data input of the receiving register via the selector 33 using the frequency dividing circuit output 101, which is equivalent to the page output 104 on the sending unit 2 side, as a selection condition. As Uke takes. Since the data Do is valid at the rising edge of the basic clock 100 when the frequency dividing circuit output 101 is IH+'', it can be given as received data 107 to the receiving unit 3 as synchronous data of the basic clock 100.

According to this embodiment, the transmission data 105 synchronized with the basic clock 100 in the transmission unit 2 is transmitted to the reception unit 3.
Received data 107 synchronized with the basic clock 100
As, the period is slightly larger than the maximum value ax of the delay time T of the output driver U of the transmitting unit 2, that is,
Transfer is possible with a delay of two clock cycles. As a result, automatic distortion occurred when transmit data was input to the transmit register and received data was output from the receive register.
Throat does not occur.

The present invention is not limited to the above embodiments (X.

For example, in the embodiment described above, the clock frequency divider circuit is provided on the receiving unit side as a means for forming the multiplication period multiplier, but it may also be provided in the clock unit node.

〔Effect of the invention〕

As described above, according to the present invention, in a data processing system consisting of a plurality of logical units that share a clock source, data is transferred from the transmitting register of one logical unit to the receiving register of another logical unit using a synchronous data processing system. In the transfer, a multiplication cycle clock of the clock is used as a selection condition for the data, transmitting and receiving data is given to one of the select data, and an output of a transmitting and receiving register is given during the remaining selection conditions, and a clock input of the transmitting and receiving register is
By providing the clock, it is possible to speed up synchronous data transfer from generation of transmission data within the transmission unit to use of reception data within the reception unit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a timing diagram of the operation of the system shown in FIG. 1... Clock unit 2... Transmission unit 3.
...Receiving unit 21...Register 22...
ANDOR circuit n...Transmission register 33...Selector 34...Reception register 41Figure 170 Tsuso unit

Claims (1)

[Claims] 1. Synchronization for transferring data from a transmission register of one logical unit to a reception register of another logical unit in a data processing system consisting of a plurality of logical units that share a basic clock supplied from a clock source. In the formula data transfer method, a selector that selects the transmitted data according to the select condition is placed before the transmit register, and a selector that selects the received data according to the select condition is placed before the receive register, and the output of the low-speed process on the transmitting side is A multiplication cycle clock generating means is provided for generating a clock with a multiplication period of the basic clock determined by the delay time of the driver. A synchronous data transfer method characterized by transferring data by giving a periodic clock as a selection condition. 2. A data processing system consisting of a plurality of logical units that share a basic clock supplied from a clock source and capable of transferring data between the logical units, which has a transmission register and an output driver, and is capable of transferring data between the logical units. In the logic unit that performs transmission, in the preceding stage of the transmission register,
A selector that selects transmit data according to select conditions is placed, and it has an input driver and a receive register, and a selector that selects receive data according to select conditions is placed before the receive register that receives data. Multiplying cycle clock generating means is provided for generating a clock with a multiplication cycle of the basic clock determined by the delay time of the output driver of the process, the basic clock is applied to the clock inputs of the transmitting register and the receiving register, and each selector has the following functions: A data processing system characterized in that data is transferred by giving a clock with a frequency multiplied by a basic clock as a selection condition. 3. The synchronous data transfer system according to claim 1, or the data processing system according to claim 2, wherein said multiplication period clock generation means is constituted by a clock frequency dividing circuit that divides the frequency of a basic clock. 4. The data processing system according to claim 2 or 3, wherein each of the logical units is constituted by one chip of IC. 5. The synchronous data transfer system according to claim 1 or 3, or claim 2, 3, or 4, wherein the multiplication period clock generation means is provided as a separate and independent unit from a logic unit that requires the multiplication period clock. Data processing system as described.