JPH02210568A - Bus controller - Google Patents

Abstract

PURPOSE:To prevent the error processing due to address error and to improve the reliability of data processing by preventing input of an CS signal at the time when a bus controller is in the master state. CONSTITUTION:A master monitor circuit 6 monitors whether a bus controller 4 is in the master state or the slave state; and when it is in the master state, the master monitor circuit 6 receives the master signal generated from a control part 5 and outputs a control signal to a CS signal breaking device 7 during reception of this master signal. The CS signal breaking device receives this control signal to break the CS signal inputted to the bus controller 3. Thus, the bus controller 4 does not perform the error processing of address error because the CS signal is not inputted to the bus controller 4 in the master state, and the bus controller 4 is prevented from being set to the slave state regardless of the master state.

Description

[Detailed Description of the Invention] [Summary] It relates to a bus control device, and in particular, a central processing unit releases a bus, and a bus control device releases C to a peripheral device.
Regarding a bus control device that has two states: a master state in which the central processing unit occupies the bus and controls the peripheral devices and the bus control device by outputting an S signal, etc. The purpose of this is to prevent the CS signal from being input to the bus control device when the bus control device is in the master state, and in the bus control device as described above, when the bus control device 4 is in the master state, A master monitoring means 6 receives a master signal output from the control section 5 of the bus control device 4 and outputs a control signal, and a CS signal received from the master monitoring means 6 and input to the bus control device is cut off. CS signal blocking means 7 is also provided.

(Industrial Application Field) The present invention relates to a bus control device, and in particular, a central processing unit releases the bus, and the bus control device outputs a CS signal etc. to peripheral devices to control the peripheral devices by its own control. The present invention relates to a bus control device having two states: a master state and a slave state in which a central processing unit occupies the bus and controls peripheral devices and the bus control device.

[Conventional technology]

In general, processing such as transferring large amounts of data between peripheral devices through a central processing unit takes a very long time, and the efficiency is reduced because the CPU is occupied by the processing. It was bad.

Therefore, with the recent demand for faster processing in computer systems, more and more processing is being controlled by a bus control device with a DMA function without going through the CPU, and accurate operation of the bus control device is desired. .

The conventional bus control device has been replaced by a central processing unit (hereinafter referred to as C
For example, FIG. 5 shows an example of a PU (called a PU) and peripheral devices such as an input/output device and a memory. In the figure, 11 is a CPU that controls each device, 12 is an input/output device,
13 is a memory; 14 is a bus control device 1 having a DMA function, etc. for data transfer without going through the CPU 11;
4, and these devices are connected by an address/data bus 15 and a control bus 16.

The bus control device 14 includes a control section 17 that outputs a master signal indicating that it is in a masked state, a READ/WRITE signal, etc., and an internal register 18 that stores information for executing processing such as DMA transfer. address·
Address decoder 19 decodes address signals on data bus 15 and outputs them as CS signals to control bus 16
and has. Further, like the bus control device 14, the CPU II also includes a control section 20, an internal register 21, and an address decoder 22.

Normally, when the input/output device 12 and the memory 13 execute their respective processes, they are controlled by the CPU II.

In this case, the CPU 11 occupies the address/data bus 15, and the bus control device 14 also
The bus controller 14 is in a slave state.

At this time, the CPU II outputs an address signal specifying necessary information to the address/data bus 15, and the upper few bits of the address signal are decoded by the address decoder 22, thereby specifying the memory 13 and the input/output device 12. It is output to the control bus 16 as a signal. The control unit 20 outputs a master signal, a READ/WRITE signal, etc. to the control bus 16, and sends them to the memory 13 and the input/output device 12, respectively.

On the other hand, when a large amount of data is transferred by DMA from the memory 13 to the input/output device 12, the CPU II releases the address/data bus 15, and the data transfer is executed under the control of the bus control device 14. In this case, the CPU
II releases the address/data bus 15, the bus controller 14 occupies the address/data bus 15, and the bus controller 14 is in the master state.

At this time, the bus control device 14
Similarly to when the UII is in the master state, the master signal and REA are sent from the control unit 17 along with the CS signal created by decoding the address signal with the address decoder 19.
The D/WRITE signal and the like are outputted to the control bus 16 and sent to the memory 13 and the input/output device 12.

[Problem to be solved by the invention]

By the way, such a conventional bus control device 14
According to , when creating a CS signal, CPU II
Or the address decoder 22 of the bus control device 14
．． In No. 19, only the upper few bits of the address signal were decoded. For example, even if the address signal had 23 bits, only the top three to five bits were decoded.

Therefore, when the bus control device 14 is in the master state and the CPU 11 outputs the CS signal to a peripheral device other than the one in DMA transfer to execute other processing,
A CS signal may be input to the bus control device 14 due to a decoding error in the address decoder 22. In such a case, there is a problem in that the bus control device 14 executes error processing as an address error.

Further, the bus control device 14 is in the master state,
Moreover, until the address/data bus 15 rises to the threshold immediately before data transfer, and when the address/data bus 15 falls from the threshold immediately after data transfer, the upper address of the address signal is undefined and undefined. Therefore, if the address signal is decoded at this time, the high-order address of the address signal changes, and by chance the high-order address coincides with the high-order address of the internal register 18 of the bus control device 14, and the internal register 18 is accessed. Something happened. In other words, the bus control device 14 itself may be accessed by the CS signal that it outputs.

In this case, even though the bus control device 14 is in the master state, the bus control device 14 itself is selected by the CS signal it outputs and shifts to the slave state, and the control unit 17 outputs the WRITE signal. If so, write WRI to internal register 18 by that signal.
I executed a TE command. Therefore, immediately before data transfer, there is no data on the address/data bus 15, so the data stored in the internal register 18 is erased. Also, if the data has just been transferred, the transfer data remaining on the address/data bus 15 and the data stored in the internal register 18 will be rewritten, destroying the contents of the internal register 18. There was a problem.

Therefore, if the above problem occurs and you perform DMA transfer again, if you handle the former error, you will have to repeat the process from the beginning, and the bus control device 1
When the contents of the internal register 18 of No. 4 are rewritten, the only method available is to reset the contents of the internal register 18, which is very time-consuming and impairs work efficiency.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a bus control device that prevents a CS signal from being input to the bus control device when the bus control device is in the master state.

[Means to solve the problem]

In the present invention, the means for solving the above problem is as shown in FIG. 1, when the central processing unit 1 releases the bus 2,
A master state in which the bus control device 4 outputs a CS signal etc. to the peripheral device and controls the peripheral device 3 under its own control, and a master state in which the central processing device 1 occupies the bus 2 and controls the peripheral device 3 and the bus control device 1. In a bus control device having two states, a slave state and a slave state, when the bus control device 4 is in the master state,
Master monitoring means 6 receives a master signal output from the control section 5 of this bus control device 4 and outputs a control signal.
and a CS signal cutoff means 7 which receives the control signal from the master monitoring means 6 and cuts off the CS signal input to the bus control device.

(Function) According to the present invention, the master monitoring circuit 6 monitors whether the bus control device 3 is in the master state or in the slave state, and when it is in the master state, the control unit The master monitoring circuit 6 receives the master signal generated from the master monitoring circuit 5, and outputs a control signal to the CS signal cutoff device 7 while receiving this signal. The CS signal cutoff device receives this control signal and cuts the C signal input to the bus control device 3.
Cut off the S signal.

Therefore, the CS signal is not input to the bus control device 4 in the master state, so the bus control device 4 does not process an error as an address error, and even though the bus control device 4 is in the master state, However, it never becomes a slave state.

〔Example〕

Embodiments of the bus control device according to the present invention will be described below with reference to FIGS. 2 to 4.

FIG. 2 shows an embodiment of the bus control device together with a CPU, an input/output device, and a memory. In the figure, 31 is a CPU that controls each device, 32 is an input/output device, 33 is a memory, and 34 is a bus control device 34 having a DMA function to transfer data without going through the CPU 31. The CPU 31 and the above-mentioned devices are connected by an AT 17 data bus 35 and a control bus 36.

The bus control device 34 has a control section 37 having the same functions as those of the conventional example, an internal register 38, and an address decoder 39. Furthermore, when the bus control device 34 is in the master state, the control section 37 It has a master monitoring device 40 that receives the output master signal and outputs a control signal while receiving the master signal, and an O8 signal cutoff device 41 that receives this control signal and cuts off the input of the CS signal. .

Further, like the bus control device 34, the CPU 31 also includes a control section 42 having the same functions as those of the conventional example, an internal register 43, and an address decoder 44.

Here, the master monitoring device 40 and the CS signal cutoff device 41
For example, there is a device that has both of the above functions, as shown in FIG. 3, which is constructed using a logic circuit, and there is a device that is specifically constructed using elements such as transistors, as shown in FIG. 4.

Next, to explain the operation with reference to FIG. 2, when the input/output device 32 is in the master state of the CPU which executes data transfer with the memory 33 under the control of the CPU 31, the bus control device 34 is in the slave state. Therefore, the master signal is not output from the control section 37. Therefore, since the mass monitoring device 40 does not receive the master signal, it does not send a control signal to the CS signal cutoff device 41, and the CS signal cutoff device 41 does not operate and the CPU 3
The CS signal output from 1 is sent to the bus control device 34.
is input.

On the other hand, when the CPU 31 releases the address/data bus 35 and the bus control element 34, which executes DMA transfer between the input/output device 32 and the memory 33 under the control of the bus control device 34, is in the master state, The control unit 37 of the bus control device 34 sends CS signals and READ/WRI signals to the input/output device 32 and memory 33.
It outputs a TE signal and the like to control them, and also outputs a master signal to the master monitoring device 40. The master monitoring device 40 receives the master signal from the control unit 37, and while receiving the master signal, sends a control signal to the CS signal cutoff device 41 to cut off the CS signal. The CS signal cutoff device 41 is activated by this control signal and cuts off the input of the CS signal to the bus control element 34.

Therefore, even if the CS signal is attempted to be input to the bus control device 34 due to a decoding error in the address decoder 44 of the CPU 31 when the bus control element 34 is in the master state, or the upper address of the address signal immediately before and after data transfer is determined. Even if the upper address of the address signal output by the bus control device 14 coincidentally coincides with the upper address of its own internal register 18 and a CS signal is attempted to be input, the master monitoring device 40 and the CS signal cutoff device 41 This allows the input of the CS signal to be cut off.

Further, to explain this circuit in FIG. 3, one input terminal of the AND circuit 51 receives a signal r from the control section 37 as a master signal if the bus control device 34 is in the master state.
If highJ is also in the slave state, rlowJ is inverted and input. That is, if the bus control element 34 is in the master state, rlowJ is input, and if it is in the slave state, rhhighJ is input. The other input terminal is connected to the control bus 36, and the CS signal is inputted to become rhhighJ. Then, the output of the AND circuit 41 is connected to the control section 37. Therefore, if the bus control device 34 is in the master state, rlowJ is always input to one input terminal, so even if the O8 signal is input from the other input terminal and becomes rhhighJ, A
The output of the ND circuit 51 is always rlowJ, and can cut off the input of the CS signal to the bus control device 34.

Further, to explain the operation in FIG. 4, it consists of transistors TR and TR2 whose emitters are commonly grounded, the base of transistor TR2 and the collector of transistor TR are connected, and a power source E is connected between the emitter and collector of transistor TR1. has been established. The bus control element 34 receives a master signal from the control unit 37 to the base of the transistor TR□, the emitters of the transistor TR□ and the transistor TR2, which are commonly grounded, are connected to the control unit 37, and the collector of the transistor TR2 receives the control signal. is connected to bus 16, and from this collector the CS
A signal is input. For this reason, the bus control device 3
4 is in the slave state, the master signal is not input to the base of transistor TR1, so transistor TR
□ is OFF, while transistor TR is turned off by power supply E.
Since the base potential of the transistor TR2 is higher than the emitter potential, the transistor TR2 is turned on, and the CS signal is transferred to the transistor TR2.
from the collector to the emitter and can be input to the bus controller 34. On the other hand, if the bus control device 34 is in the master state, the master signal is input to the base of the transistor TR1, so the transistor TR□ is turned on, and the collector potential and emitter potential of the transistor TR become equal. For this reason,
Since the base potential and emitter potential of transistor TR2 are equal, transistor TR2 is turned off and C
Even if the S signal is input to the collector of the transistor TR2, it will not flow to the emitter of the transistor TR2, and the CS signal can be prevented from being input to the bus control device 34.

Therefore, according to this embodiment, since the bus control device 34 is configured as described above, the bus control device 34
When the bus control device 3 is in the master state, the bus control device 3
4 can be prevented from being input to the bus control device 34, it is possible to prevent error processing due to an address error from being executed, and the CS signal can also cause the internal register 38 of the bus control device 34 to enter the slave state.
It is possible to prevent the data from being accessed and rewritten, thereby increasing the reliability of data processing. As a result, it is possible to save the operator's extra effort and improve the work efficiency of the input/output processing.

Note that the circuit in FIG. 3 is configured with a logic circuit as a device that has both the functions of the master monitoring device 40 and the CS signal cutoff device 41, and the circuit in FIG. 4 is specifically configured with transistors. It is not limited to this circuit, and may be configured with other circuits, and such a function may be provided in software. It goes without saying that the master monitoring device 40 and the CS signal cutoff device 41 may be configured separately.

〔Effect of the invention〕

As explained above, according to the present invention, since the bus control device is configured as described above, when the bus control device 34 is in the master state, input of the CS signal can be prevented, so that errors caused by address errors can be prevented. It is possible to prevent the processing, and also to prevent the CS signal from shifting to the slave state and accessing the internal register of the bus control device 34 and rewriting its contents, thereby improving the reliability of data processing. can be increased. As a result, the operator's extra effort can be saved, and the efficiency of the input/output processing can be improved.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a diagram showing an embodiment of a bus control device according to the present invention, FIG. 3 is a diagram in which the main part of this embodiment is configured by a logic circuit, and FIG. Figure 5 shows the main part of this embodiment constructed using transistors.
The figure is a diagram showing a bus control device according to a conventional example. 4...Bus control device 5...Control unit 6...Master monitoring means 7...CS signal cutoff means

Claims (1)

[Claims] The central processing unit (1) releases the bus (2), and the bus control device (4) outputs a CS signal etc. to the peripheral device to control the peripheral device (3) under its own control. In the bus control device having two states: a master state and a slave state in which the central processing unit (1) occupies the bus (2) and controls the peripheral devices (3) and the bus control device (1), When the control device (4) is in the master state, the control section (5) of this bus control device (4)
a master monitoring means (6) which receives a master signal output from the master monitoring means (6) and outputs a control signal; and a CS signal cut-off means (6) which receives a control signal from the master monitoring means (6) and cuts off a CS signal input to the bus control device. 7) A bus control device comprising: