JPH02210552A - Logic simulation system - Google Patents

Abstract

PURPOSE:To shorten the time of logic verification and to improve the efficiency of logic verification by selectively executing a test program for verification by simulators adapted to respective parts of the test program. CONSTITUTION:A discriminator building-in means 2 which builds a discriminator, which indicates the change of a simulator 4 to be executed during the execution of simulation, in the test program executed on a model, a test program loading means 3 which loads this test program which the discriminator is built in to the model on the simulator, and a discriminator detecting means 7 which detects the built-in discriminator during the execution of simulation are provided. An execution change means 8 is provided to change the execution of simulation to the simulator 4 indicated by this detected discriminator. Thus, the test program for verification is selectively executed by simulators adapted to respective parts of the test program, and the logic verification time is shortened and the efficiency of logic verification is improved.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a logic simulation method, and particularly relates to a logic simulation method in which a verification test program is executed by a simulator suitable for each part of the test program. .

[Conventional technology]

Conventionally, this type of logic simulation method, particularly the execution of a verification test program on a simulator, has been performed using a single simulator, and all processes of the verification test program have been executed continuously on the same simulator.

[Problem to be solved by the invention]

In the conventional logic simulation method described above, all the steps of the program are executed on a simulator suitable for the test instruction part, so the execution time of other parts increases pointlessly, which increases the time for logic verification. There is a drawback.

[Means to solve the problem]

The logical simulation method according to the present invention includes means for embedding an identifier instructing a change in the simulator to be executed during simulation execution into a test program executed on a model, and loading the test program embedded with this identifier into the model on the simulator. means for detecting the embedded identifier during simulation execution; and means for changing execution of the simulation to a simulator designated by the detected identifier.

[For production]

According to the present invention, a verification test program can be selectively executed by a simulator suitable for each part of the test program.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of a logic simulation method according to the present invention. In the same figure, 11 is a verification test program, 2 is an identifier embedding means for embedding an identifier in this verification test program 1, and 3 is a verification test program that is loaded onto the model in the simulator to make it executable. A test program loading means, 4 a simulator, 5 a simulator that performs simulations at high speed at a functional level, 6 a simulator that performs simulations at a detailed level, 7 detects identifiers when each of the simulators 5 and 6 are executed, and detects the identifiers thereof. An identifier discovering means 8 notifies the simulator to be executed next specified by T, and 8 stops the currently running simulator and shifts the current simulation state of the simulator to be executed next based on the notification from the identifier discovering means T. This is an execution change means that restarts execution.

Next, the operation of the simulation method with the above configuration will be explained with reference to the flowchart of execution of the verification test program shown in FIG. - For example, the verification test program is the preprocessing part 9. It consists of a test command section 10 and a post-processing section 11, 3-1. The identifier is at position A
and embedded in position B. The execution of each part, especially the preprocessing part 9, is carried out in the simulator 5, and the test command part 1
0 is performed in the simulator 6, and the post-processing portion 11 is performed in the simulator 5. Then, the verification test program 1 is inserted between the preprocessing part 9 and the test command part 10 by the identifier embedding means 2, and the test command part 10.
A BK identifier is embedded between the post-processing portion 11 and the test program loading means 3, and is loaded into the model in the simulator 5 by the test program loading means 3. The simulator 5 then executes said processing part 9 at a functional level. At this time, the identifier discovering means 7 detects the identifier, selects the simulator to be executed next, and notifies the execution changing means 8 of the selection information. Then, the execution change means 8 transfers the current simulation state from the simulator 5 to the simulator 6, and the simulator 6 resumes execution of the test instruction portion 10 at a detailed level. Then, in the simulator 6, the identifier discovering means 7 discovers the identifier in the same way, and the execution changing means 8 changes the execution from the simulator 6 to the simulator 5, and restarts the execution of the post-processing part 11 at the functional level using the simulator 5. be able to.

In the above-described embodiment, the case where the verification test program is executed by the simulators 5 and 6 has been described, but the present invention is not limited to this, and it goes without saying that the same can be done when three or more simulators are used.

〔Effect of the invention〕

As explained in detail above, according to the present invention (the simulation method), the test is performed.

By selectively executing the program using a simulator suitable for each part of the test program, it is possible to shorten logic verification time and improve efficiency.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the logic simulation method according to the present invention, and FIG. 2 is a diagram showing the flow of execution of a verification test program. DESCRIPTION OF SYMBOLS 1...Test program for verification, 2...Identifier embedding means, 3...Test program loading means, 4...Simulator, 5 and 66...Simulator, 7...Identifier Discovery means, 8...Execution change means, 9...Pre-processing part, 10...Test command part, 11...Post-processing part.

Claims (1)

[Claims] In a logic simulation method in which a verification test program is executed on a simulation model using two or more independent logic simulators, an identifier that instructs a change in the simulator to be executed during simulation execution is embedded in the test program executed on the model. means for loading a test program embedded with this identifier into a model on a simulator; means for detecting the embedded identifier during simulation execution; and execution of the simulation on the simulator indicated by the detected identifier. A logical simulation method characterized by comprising: means for changing.