JPH02208726A - Microprogram controller - Google Patents

Abstract

PURPOSE:To execute the branch to a specified address area mounted in a separated position at a high speed by selecting a micro-instruction which is read out of a specific address area in accordance with a part of a branch address field and an address area designating part, in the case when a branch instructing part instructs a branch to plural specific address areas. CONSTITUTION:By an address of 9 bits in a micro-instruction register 14, a control memory 10 and a control memory 15 are brought to access. Subsequently, in accordance with an address area designating bit in a micro-instruction register 13, a selector 16 and a selector 17 select the control memory 10. Also, in accordance with a branch instruction bit in the micro-instruction register 13, a selector 11 and a selector 12 select a specific address area, therefore, a micro-instruction which is read out of the control memory 10 is stored in the micro-instruction register 13 and the micro-instruction register 14. In such a way, a branch to the control memories 10, 15 is executed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to an information processing device, and particularly to a microprogram control device that performs arithmetic control using a microprogram.

[Conventional technology]

In a microprogram control device, a microinstruction stored in a control memory includes a branch address field, and the address indicated by the branch address field in the microinstruction read from the control memory is controlled as the address of the next microinstruction to be executed. A branching method that accesses memory is generally employed.

Furthermore, due to hardware considerations, all fields in a specific address area of the control memory and some fields in the normal address area may have to be implemented at separate locations. At this time, the access time of the control memory mounted at the location 111 becomes a problem. This will be explained in detail using FIG. Return address register in Figure 3! , 2 are registers in which the return address from the subroutine is stored. Return address register 1.2 and selector 5.6 are area A
and area B. Address register 3 is a register in which the address of the first step of a microinstruction for executing an instruction is stored. The address save register 4 is a register for temporarily storing an address for accessing the control memory 10. Selector 5 and selector 6 each select one of the branch address field in the microinstruction or return address register 1.2 as an address for accessing control memory 8.9. The branch address field in the microinstruction is stored in microinstruction registers 13 and 14 in a distributed manner.
4 are supplied to selectors 5, 6.7. Selector 7 uses the branch address field in the microinstruction, address register 3, or address save register 4 as an address for accessing the control memory IO.
This is a selector for selecting one of them. The control memory 8 is a memory in which the F-order 5 bits of the branch address field of the microinstruction and other fields are stored, and is an 8kw×81-bit memory. The control memory 9 is a memory in which the lower 9 bits of the branch address field of the microinstruction are stored, and is an 8 kW x 9 bit memory. The control memory 10 is a memory in which the first step of microinstructions for executing instructions and other microinstructions are stored, and is 1kw x 9
It is a 0-bit memory. The selector 11 is a selector for selecting one of the control memory 8 and the control 10. Selector 12 is control memory 9
Alternatively, it is a selector for selecting the control memory 10. Selector 11 and selector I2 are activated when the most significant bit of the branch address field in microinstruction register 13 is "engine" or when an instruction start signal (not shown) is "engine".
1", control memory 10 is selected; otherwise, control memory 8 and control memory 9 are selected. The microinstruction register 13 stores the upper 5 bits of the microinstruction branch address field and other fields. It is a register.

The microinstruction register 14 is a register in which the lower 9 bits of the branch address field of the microinstruction are stored.

FIG. 4 is a diagram showing the format of microinstructions used in the conventional microprogram control device of FIG. The sequence control field selects return address register 1 and return address register 2 as addresses for accessing control memory 8 and control memory 9 or control memory 10, or selects the branch address field in microinstruction register 13 and microinstruction register 14. This is a field that instructs whether to do so. The upper 5 bits of the branch address field are stored in the microinstruction register 13, and the lower 9 bits are stored in the microinstruction register 14.

In such a microprogram control device, when an attempt is made to access the control memory 10 using a branch address field in a microinstruction, the delay time of the path from microinstruction register 13 → selector 7 → control memory 10 → selector 11 → microinstruction register 13 increases. becomes a problem. This is because the above path has to pass through the areas twice, from area A to area B to area A, resulting in a longer delay time than other paths. The delay time of the sea signal is large when accessing the memory and passing between areas, so if you access the mesori and pass between areas twice, the delay time will be 1.
It exceeds the clock cycle.

Therefore, conventionally, when accessing the control memory 10 using a branch address field in a microinstruction, the address is stored in the address save register 4 once;
It was accessed in the next clock cycle. That is, branching to control memory 10 required two clock cycles.

[Problem B that the invention attempts to solve]

The conventional microprogram controller described above has the disadvantage that branching to control memory 10 requires two clock cycles, which reduces performance.

(Means for Solving the Problems) A microprogram control device of the present invention uses an address indicated by a branch address field in a microinstruction read from a control memory to a microinstruction register as an address of a microinstruction to be executed next. A branching method is adopted to access the control memory, and the control memory is used in the first and second address areas, which are normal address areas.
In a microprogram control device consisting of a control memory and a plurality of third control memories which are specific address areas, microinstructions are stored in a sequence control field, a branch address field, a first
, a branch supporter that instructs whether to branch to the second control memory or the third control memory;
and an address area specifying section that specifies one of the third control memories when branching to the third control memory, and the second control memory includes the first . Second. A second portion that commonly accesses the third control memory is stored, a first portion of the microinstruction excluding the second portion is stored in the first control memory, and the microinstruction register is a microinstruction register. , a first microinstruction register in which a first part of the microinstruction read from the first control memory or the microinstruction read out from the third control memory is stored; a second microinstruction register in which a second part of the microinstructions read from the plurality of third control memories or microinstructions read from the third control memory is stored; , the first and second portions of the third control memory specified by the address area specification part of the microinstruction read into the first microinstruction register, respectively. a selector, and a branch of the microinstruction read out from the first control memory or the first part of the third control memory selected by the first selector into the first microinstruction register. Follow the instructions to select
a third selector that outputs the microinstruction to the first microinstruction register; and a microinstruction read from the second control memory or a second portion of the third control memory selected by the second selector; and a fourth selector that selects according to the branch instruction part of the microinstruction read into the microinstruction register and outputs the selected microinstruction to the second microinstruction register.

[For production]

When accessing the control memory in a specific area, there is no longer a need for a bus from the first microinstruction register to the control memory in the specific area, and the selector switching time is much shorter than the memory access time. Branching to control memory is faster.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a microprogram control device showing one embodiment of the present invention, and FIG. 2 is a diagram showing the format of microinstructions used in this embodiment.

The microprogram control device of this embodiment has a control memory 8.9 which is a normal address area and a control memory 10.15 which is a specific address area.

The microinstructions used in this embodiment are of format 1 and format 2, as shown in FIG. Format 1 is used when branching to the normal address area, that is, control memory 8 and control memory 9, and the branch instruction bit (
1 bit), 4-bit microprogram sequence control field, upper 5 bits and lower 9 bits of branch address
Contains bits, one unused bit, and other fields. Format 2 is used when branching to a specific address area, that is, control memory 10 or control memory 15, and includes an address area designation bit (1 bit) indicating whether to branch to control memory 10 or control memory 15. It includes a branch instruction bit (1 bit) for instructing branching to an address area, a 4-bit microprogram sequence control field, a 9-bit branch address field, and other fields. In format 2, the upper 5 bits of the branch address field in format 1 are used for other purposes (arithmetic control, etc.)
Can be used for Whether a microinstruction is used as format 1 or format 2 is determined according to the branch instruction bit.

That is, if the branch instruction bit is "0", it is regarded as type 1, and if it is 1'', it is regarded as type 2.

Control memories 10 and 15 are each 512 word by 92 bit memories in which specific processing routines are stored. The control memory 8 is a memory of 8 words x 83 bits in which the part of the branch address field of the microinstruction excluding the lower 9 bits is stored. The control memory 9 is an 8 word x 9 bit memory in which the lower 9 bits of the branch address field of the microinstruction are stored. Selector 16 is control memory 10
The upper 83 bits of the microinstruction read from the control memory 15 or the microinstruction read from the control memory 15 are selected according to the address area designation bits stored in the microinstruction register 13. The selector 17 selects the lower 9 bits of the microinstruction read from the control memory 10 or the microinstruction read from the control memory 15 according to the address area designation bits stored in the microinstruction register 13. The selector 11 selects the upper 83 bits of the microinstruction read from the control memory 8 or from the specific address area selected by the selector 16, according to the branch instruction bit stored in the microinstruction register 13. The selector 12 selects the lower 9 bits of the microinstruction read from the control memory 9 or the microinstruction read from the specific address area selected by the selector 17 in accordance with the branch instruction bit stored in the microinstruction register 13. The microinstruction register 13 is
This register stores the address area designation bit, branch instruction bit, sequence control field, upper five bits of the branch address field, and other fields of the microinstruction. The return address register 1, return address register 2, address register 3, selector 5, selector 6, selector, and microinstruction register 14 are the same as those described in (Prior Art), so please refer to them.

In this embodiment, when branching to the control memory 10, microinstructions are read out as follows. Control memory 10g and control memory 15 are accessed using a 9-bit address in microinstruction register 14. Next, selector 16 and selector 17 are selected according to the address area designation bit in microinstruction register 13.
selects control memory 10. Further, since selector 11 and selector 12 select a specific address area according to the branch instruction bit in microinstruction register 13, the microinstruction read from control memory 10 is stored in microinstruction register 13 and microinstruction register 14.

In this way, when accessing control memory 10.15 using the branch address field in a microinstruction,
As before, microinstruction register 13 → selector 7 →
There is no bus for control memory 10 → selector 11 → microinstruction register 13. Microinstruction register 13
In the bus of →selector 17 →selector 12 →microinstruction register 14, the bus passes through the selector one more time than the conventional bus, but there is no memory access, and moreover, it passes through only one time between areas. Since the selector switching time is much shorter than the memory access time, branching to the control memory 10.15 is performed quickly.

(Effects of the Invention) As described above, the present invention provides a micro-instruction that includes a branch address field, a branch instruction section that instructs a branch to one of a plurality of specific address areas, and a branch address field that instructs a branch to one of a plurality of specific address areas. , and if the branch instruction section instructs branching to multiple specific address areas, read from the specific address area according to part of the branch address field and the address area specification section. By having a selector for selecting a microinstruction that has been executed, there is an effect that branching to a specific address area implemented at a remote location can be realized with high performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a microprogram control device showing one embodiment of the present invention, FIG. 2 is a diagram showing the format of microinstructions used in the microprogram control device of FIG. 1,
FIG. 3 is a block diagram showing a conventional microprogram control device, and FIG. 4 is a diagram showing the format of microinstructions used in the microprogram control device of FIG. 1.2...Return address register, 3...Address register, 4...Address save register, 5.6.7.11,12,16.17...◆...
・Selector, 8.9, 10.15...Control memory, 13.1
4...Microinstruction register.

Claims (1)

[Claims] 1. A branch method is adopted in which the control memory is accessed using the address indicated by the branch address field in the microinstruction read from the control memory to the microinstruction register as the address of the next microinstruction to be executed. , in a microprogram control device in which the control memory consists of first and second control memories that are normal address areas and a plurality of third control memories that are specific address areas, the microinstructions are arranged in sequence control fields. , in addition to the branch address field, a branch support section that indicates whether to branch to the first, second, or third control memory, and a third control memory when branching to the third control memory. and an address area designation section that designates one of the memories, and a second part of the branch address field that commonly accesses the first, second, and third control memories is stored in the second control memory. , the first control memory stores a first part of the microinstruction excluding the second part, and the microinstruction register stores the microinstruction read from the first control memory or the third control part. a first microinstruction register in which a first part of the microinstructions read from the memory is stored; a microinstruction register read from the second control memory or one of the microinstructions read from the third control memory; a second microinstruction register in which a second part is stored, and a microinstruction read into the first microinstruction register among the first part and second part of the plurality of third control memories; first and second selectors that respectively select the first and second parts of the third control memory specified by the address area specification section of the microinstruction or microinstruction read from the first control memory; selecting a first portion of the third control memory selected by the first selector in accordance with a branch instruction part of the microinstruction read into the first microinstruction register;
a third selector that outputs the microinstruction to the first microinstruction register; and a third selector that outputs the microinstruction read from the second control memory or a second portion of the third control memory selected by the second selector to the A microprogram control device comprising: a fourth selector that selects a branch instruction section of a microinstruction read into the microinstruction register and outputs the selected branch to the second microinstruction register.