JPH02207621A - Decoder circuit - Google Patents

Abstract

PURPOSE:To detect a correct BnZS code and to convert the code to an NRZ code by comparing an output signal from an output step near the shift position of a second violation pulse with a detection signal from a detection circuit when a first violation pulse is detected an identifying whether the pulse is erroneous pulse or not. CONSTITUTION:First and second shift registers 1 and 2 are equipped with the number of shift steps corresponding to an (n) bit of the BnZS code and in a condition that a negative polarity signal is shifted to the shift registers 1 and 2 next to a positive polarity signal, a detection circuit 3 judges the signal as a regular bipolar signal. When the positive polarity signal is continuously shifted next to the positive polarity signal or the negative polarity signal is continuously shifted next to the negative polarity signal, the circuit 3 judges the pulse as the violation pulse. By using the output signal from the output step near the shift position of the second violation pulse by the first and second shift registers 1 and 2 when the first violation pulse is detected by the detection circuit 3, a comparator circuit 5 detects the presence and absence of the mixing of the erroneous pulse. Thus, concerning the correct BnZS code, it can be defined as the unipolar signal of the NRZ code.

Description

[Detailed Description of the Invention] [Summary] Regarding a decoder circuit that detects a BnZS code, removes violation pulses, and converts it into an NRZ code, the present invention aims to detect a correct BnZS code and convert it into an NRZ code. The first step separates the received bipolar signal of the code into a positive polarity signal and a negative polarity signal and shifts them respectively. a second shift register; a detection circuit that detects a first violation pulse based on an output signal from a predetermined stage of a second shift register; In a decoder circuit comprising a detection output section that detects a BnZS code from output signals of a plurality of stages of a second shift register and converts the received bipolar signal into a unipolar signal of an NRZ code and outputs it, the detection circuit The first violation pulse at the time when the first violation pulse is detected.
A comparison circuit is provided that compares the output signal from the output stage near the shift position of the second violation pulse of the second shift register with the detection signal from the detection circuit to determine whether or not it is an error pulse. Configured.

[Industrial application field]

The present invention relates to a decoder circuit that detects a BnZS code, removes violation pulses, and converts it into an NRZ code.

In a bipolar signal, for example, "1" is alternately converted into a positive polarity signal and a negative polarity signal, and "0" is set to O level. Therefore, when "0" continues, the bipolar signal is Since the θ level is continuous, the receiving side cannot extract the clock signal. Therefore, on the transmitting side, a BnZS code is used that inserts a violation pulse every time n bits of "0" are consecutive.
On the receiving side, the bipolar signal has many changing points, making it easier to extract the clock signal. However, it is necessary to remove the inserted violation pulse, and a decoder circuit is provided for this purpose. This decoder circuit is
It is necessary to detect BnZS codes without error.

[Conventional technology]

A conventional decoder circuit for the B8ZS code with n-8 of the BnZS code has the configuration shown in FIG. 4, for example, and has the configuration shown in FIG. F21 to F28 are the first. Second
F29 is a flip-flop that constitutes the shift register of
is a flip-flop set by B8ZS code detection, F30 is an output flip-flop, 11 to 13 are inverters, 14 to 21 are NAND circuits, 22 is an AND circuit, and 23 is an output terminal.

The bipolar signal of the B8ZS code is separated into a positive polarity signal PS and a negative polarity signal NS by a bipolar/unipolar converter (not shown), and each of them is sent to a flip-flop Fi1. It is added to the data terminal of F21.

Also, the clock signal CL extracted from the received bipolar signal
K is connected to flip-flop F through inverters 11 and 12.
The flip-flop F is further connected to the clock terminal C of il~F1B, F21~F2B, and F30 via the inverter 13.
29 clock terminals C, respectively.

Therefore, the positive polarity signal PS is applied to the flip-flops F11-F.
are sequentially shifted into a first shift register consisting of 18,
Further, the negative polarity signal NS is sequentially shifted to a second shift register consisting of flip-flops F21-2. Further, the NAND circuits 14 to 17 constitute a detection circuit for detecting violation pulses. Also, NAND circuit 18-2
1 and a flip-flop F29. F30 and the AND circuit 22 constitute a detection output section.

The initial setting signal Is (“0”) causes the latch section by the NAND circuit 14 and 15 of the detection circuit and the flip-flop F
30 is reset, and when the switching signal ABS is set to "0", it becomes an AMI code decoding function, and when it is set to "1', it becomes a B8ZS code decoding function.

FIG. 5 is an explanatory diagram of the operation, and (a) shows the clock signal CL.
K, (b) shows a bipolar signal of B8ZS code. After the data bit DB, if bits B1 to B8 are consecutive "0", on the transmitting side, bin) B4 is used as the first violation pulse ■, bit B5 is inserted as the first bipolar law pulse B, bit B7 is the second violation pulse v1, bit BB is inserted as the second bipolar law pulse B, and when the data bit DB is a positive polarity signal,
Since the bipolar signal shown in (b) is obtained, the positive polarity signal P
S is as shown in (C), and the negative polarity signal NS is as shown in (d).

Further, when the data pin DB is a negative polarity signal, (C) is a negative polarity signal NS, and (d) is a positive polarity signal.

The positive polarity signal PS shown in (C) is shifted to the flip-flops F18-Fil, and the flip-flops F28-F
21, when the negative polarity signal NS shown in (d) is shifted, the first violation pulse V is transferred to the flip-flop F15, and the second violation pulse V is transferred to the flip-flop F15.
are shifted to the flip-flop F22, the first bipolar law pulse B is shifted to the flip-flop F25, and the second bipolar law pulse B is shifted to the flip-flop Fi.
Therefore, the inputs of the NAND circuit 19 are all '1', and the output signal is '1'.
In that case, the input of the NAND circuit 20 is “0”.
Since it contains "0", its output signal becomes "1".

Therefore, the output signal of the NAND circuit 21 becomes "1", and the clock signal C is sent to the clock terminal C via the inverter 13.
Output terminal d of flip-flop F29 to which LK is applied
becomes “0”. Therefore, the output signal of the AND circuit 22 becomes "0", and the flip-flops F12 to F18 and F22 to F28 are all reset by the output signal of O.

Also flip-flop F16. When the output terminals d of F26 are both "1", the output signal of the NAND circuit 18 is "0", and otherwise it is "1", so the positive polarity signal PS
When either the negative polarity signal or the negative polarity signal NS is "1", the output terminal Q of the flip-flop F30 becomes "1". However, as described above, the output signal of the AND circuit 22 is When it becomes "0", the flip-flops F16 and F26 are also reset, so the output terminal Q of the flip-flop F30 becomes "O". That is, a unipolar signal of the NRZ code from which the violation pulse (2) and the bipolar law pulse B inserted on the transmitting side are removed can be output as shown in FIG. 5(e).

[Problem to be solved by the invention]

If the received bipolar signal contains an error pulse,
Alternatively, if an error pulse is mixed in when the positive polarity signal and the negative polarity signal are separated, for example, the negative polarity signal NS (as shown in Shu) with respect to the positive polarity signal PS shown in FIG. When an error pulse E is mixed between the first bipolar law Hals B and the second violation pulse V, the positive polarity signal PS is shifted to the shift registers Fil to F18, and the positive polarity signal PS is shifted to the shift registers F21 to F2B. When the negative polarity signal NS is shifted, the error pulse E is shifted to the flip-flop F23.

However, if the positive polarity signal PS includes, for example, the first violation pulse V and the second bipolar law pulse B,
In addition, the first bipolar law pulse B and the second bipolar pulse are applied to the negative polarity signal NS.
If violation pulse V is included,
Even if the error pulse E is included, as shown in (h),
A unipolar signal of the NRZ code obtained by decoding the B8ZS code is output. In other words, even if the conditions of the B8ZS code are not satisfied due to the inclusion of an error pulse E, etc., the B8Z
There was a drawback that it was decoded as S code. In other words,
It was not possible to detect the inclusion of the error pulse E.

The present invention aims to detect a correct BnZS code and convert it into an NRZ code.

[Means to solve the problem]

The decoder circuit of the present invention converts a BnZS code bipolar signal into an NRZ code unipolar signal, and will be explained with reference to FIG.

A received bipolar signal of the BnZS code is separated into a positive polarity signal and a negative polarity signal by a bipolar/unipolar converter (B/U) 6, and the first . second shift register 1
．． 2, and the first and second shift registers 1
, 2, and the first and second shift registers 1., 2 at the time when the detection circuit 3 detects the first violation pulse. The BnZS code is detected from the output signals of multiple stages of 2, and the received bipolar signal is converted to NR.
In a decoder circuit comprising a detection output section 4 that converts the signal into a Z-code unipolar signal and outputs it, the first violation pulse is detected at the time when the detection circuit 3 detects the first violation pulse. A comparison circuit that compares the output signal from the output stage near the shift position of the second violation pulse of the second shift register 1.2 with the detection signal from the detection circuit 3 to identify whether or not it is an error pulse. 5.

[Effect]

1st. The second shift registers 1 and 2 have the number of shift stages corresponding to n bits of the BnZS code, and the detection circuit 3 detects that the negative polarity signal is the first . Second
If the signal is shifted to shift registers 1 and 2, it is determined to be a regular bipolar signal, and if the signal is shifted to the positive polarity signal after the positive polarity signal or the negative polarity signal is shifted to the negative polarity signal, the bipolar signal is determined to be a normal bipolar signal. ration pulse,
In the detection output section 4, at the time when the violation pulse detection signal is obtained, the first. second shift register 1
, 2 is used to detect the BnZS code, the inserted violation pulse is removed, and the NRZ
It outputs a unipolar signal with a code of the first . Using the output signal from the output stage near the shift position of the second violation pulse of the second shift register 1.2, the comparator circuit 5 detects the presence or absence of an error pulse, and detects the presence or absence of an error pulse. If there is, the NR from which the violation pulse has been removed from the detection output section 4
If a Z-code unipolar signal is output and an error pulse is mixed in, it is not considered to be a BnZS code and is output as NRZ.
It outputs a unipolar signal of the code.

[Examples] Examples of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention.
The same reference numerals as in FIG. 4 indicate the same parts. In the same figure, 24° and 25 are NOR circuits that constitute the comparison circuit, and NAND circuit 1 that constitutes the detection circuit.
4 to 17 are flip-flops F16. This output signal from the output terminal of F26 inverts the output signal of the latch section consisting of NAND circuits 14 and 15, and the output signal and the flip-flops F, 15. The first violation pulse is detected by applying the output signal of the output terminal Q of F25 to the NAND circuits 16 and 17.

The output signals of the NAND circuits 16 and 17 and the flip-flops F23. The output signal of the output terminal Q of F1a is compared by NOR circuits 24 and 25.

FIG. 3 is an explanatory diagram of the operation of the embodiment of the present invention, in which (a) shows a clock signal, and (b) shows a received bipolar signal of a BnZS code, in which 8 or more consecutive bits of positive polarity signal (data bif) DB are shown. is "0", the first . Second
violation pulse V and the first. By inserting the second bipolar law pulse B, the positive polarity signal ps becomes as shown in (C), the negative polarity signal NS as shown in (d), and the first violation pulse V becomes the one shown in the flip-flop F1.
5, the second bipolar law pulse B is shifted to the flip-flop Fil,
Also, the first bipolar law pulse is applied to the flip-flop F24.
In addition, the second violation pulse V is shifted to the flip-flop F22.

Therefore, if there is no error pulse, the flip-flop F2
Since the output signal of the output terminal Q of 3 is "0" and the output signal of the NAND circuit 16 is "0", the output signal of the NOR circuit 24 is "1", which is different from the case in the conventional example. Similarly, the output signal of the NAND circuit 19 is "0", and the output signal of the NAND circuit 21 is "0".
The output signal of the first . Flip-flops F12 to F18 . of the flip-flops constituting the second shift register. F
22 to F2B are reset, and the unipolar (t) of the NRZ code outputted via the NAND circuit 18 and the flip-flop F30 becomes "0". That is, +e in FIG.
), violation pulses etc. inserted on the transmitting side are removed.

Furthermore, if the positive polarity signal Ps contains an error pulse E as shown in FIG.
The first pi-bolar law pulse B is applied to the flip-flop F24.
, when the second violation pulse (2) is shifted to the flip-flop F22, the output signal at the output terminal Q of the flip-flop F23 becomes "1". This output signal is input to the NOR circuit 24, so even if the output signal of the NAND circuit 16 becomes "O" by detecting the first violation pulse (2), the output signal of the NOR circuit 24 becomes "O".
0", and the error pulse E can be detected. Therefore, the output signal of the NAND circuit 19 remains "1", and the flip-flops Fil-F18°F21 to F28 constituting the first and second shift registers Since it is not reset, the unipolar signal of the NRZ code output via the NAND circuit 18 and the flip-flop F30 according to the contents shifted to the first and second shift registers is (
h). Such a unipolar signal is
The occurrence of an error can be detected by a parity check or the like.

As mentioned above, when error pulse E is mixed, B
8ZS code, therefore, B8ZS
This means that only the code can be detected and converted into the NRZ code. It can also be applied to BnZS codes other than n=8, and depending on the insertion position of the violation pulse, etc.
The first circuit added to the detection circuit, comparison circuit, and detection output section. The output stage of the second shift register will be selected.

〔Effect of the invention〕

As explained above, the present invention provides the comparison circuit 5,
Since it is used to identify whether or not an error pulse is mixed in the BnZS code, it is possible to remove violation pulses etc. inserted on the transmitting side only for correct BnZS codes, and make it a unipolar signal of the NRZ code. There are advantages.

Furthermore, since the comparator circuit 5 can have a simple configuration such as the NOR circuits 24 and 25, there is an advantage that the circuit configuration does not become complicated and the cost does not increase.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of the operation of an embodiment of the present invention.
FIG. 4 is a block diagram of the conventional example, and FIG. 5 is an explanatory diagram of the operation of the conventional example. ■、2 is the first. a second shift register; 3 is a detection circuit;
4 is a detection output section, and 5 is a comparison circuit.

Claims (1)

[Claims] First and second shift registers (1, 2) that separate a received bipolar signal of a BnZS code into a positive polarity signal and a negative polarity signal and shift them respectively; a detection circuit (3) for detecting a first violation pulse based on an output signal from a predetermined stage of the shift register (1, 2); The first and second shift registers (1
, 2) detects a BnZS code from the output signals of the plurality of stages, and converts the received bipolar signal into a unipolar signal of the NRZ code and outputs the decoder circuit (4). Output from the output stage near the shift position of the second violation pulse of the first and second shift registers (1, 2) at the time when the first violation pulse is detected by the circuit (3) A decoder circuit characterized in that a comparison circuit (5) is provided for comparing a signal and a detection signal from the detection circuit (3) to determine whether or not it is an error pulse.