JPH02206160A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a range into which impurities are implanted mutually by a method wherein a region into which first-type impurities are implanted and a region into which second-type impurities are implanted and separated by a definite distance by using a mask pattern. CONSTITUTION:P<+> ions 8 as first-type impurities are implanted by using the following as a mask: patterns of N-well resist masks 4 as first patterns whose end parts are situated on belt-shaped mask oxide film 2 and which have been formed between the mask oxide films 2; the mask oxide films 2. Then, B<+> ions 9 as second-type impurities are implanted by using the following as a mask: a pattern of a P-well resist mask 5 as a second pattern corresponding to a reversed pattern of the N-well resist masks 4; the mask oxide films 2. Then, this assembly is heat-treated; the individual impurities are diffused; an N-well 6 and P-wells 7 are formed. Thereby, a region into which the first-type impurities are implanted and a region into which the second-type impurities are implanted are separated by a definite distance; accordingly, when diffusion lengths of the individual impurities are made definite, a range into which the impurities are implanted mutually is reduced.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device having a P-well and an N-well on a semiconductor substrate, which is applied to highly integrated semiconductor integrated circuit elements, etc. be.

[Conventional technology]

When the minimum pattern size was about 5 to 3 μm, P-wells were often formed in N-type substrates, and from about 2 μm, N-wells were formed in P-type substrates, and then from 1.5 μm to In the 1.0Iim rule process, both an N-well and a P-well are formed in a P-type or N-type semiconductor substrate. This is the result of trying to optimize the impurity profile of transistors with as few steps as possible in line with so-called miniaturization.

A conventional method of manufacturing this type of semiconductor device will be explained with reference to FIGS. 6 and 7. First, when forming an N-well and a P-well to match the semiconductor substrate,
If misalignment of the wells occurs, problems such as occurrence of leakage, reduction in launch-up resistance, and reduction in withstand voltage between wells will occur, so it is convenient to align the wells to 1 in a self-aligned manner.

Now, FIG. 6 shows a method of forming N wells and P wells by ion implantation using the LOGO3 (selective oxidation) method.
and 5iJ452 are formed and after etching the Si3Nm 52 according to the pattern of the resist 53.

P” (phosphorus) 54, an impurity that forms the N-well
The figure shows the state in which ions have been implanted. In the same figure (b), after removing the resist 53, phosphorus 5 is removed by the LOCO3 method.
A mask oxide film 55 is formed at the position where ions of 4 are implanted,
B is an impurity that forms the P well.

A state in which (boron) 56 is implanted is shown. In the same figure (C1), an N well 57 and a P well 58 are formed by heat-treating and diffusing the implanted impurities.

When this method is used, the well boundaries of the N well 57 and the P well 58 are in contact with each other, so that they are formed in a self-aligned manner.

On the other hand, since the impurities of the N well 57 and the P well 58 enter each other through the well boundaries due to impurity diffusion,
There is always a region where the impurity distribution is unstable. That is, in FIG. 7, the well boundary portion 59 between the N well 57 and the P well 58 is at the same position as the position at the time of ion implantation;
Since the type and P type impurities diffuse outside the well boundary 59, they enter into each other's wells as shown by the dotted lines. Therefore, the part surrounded by the dotted line (indicated by diagonal lines) is a region with a low impurity concentration unlike other well parts, so no element can be formed in this part.

[Problem to be solved by the invention]

However, this conventional method of manufacturing a semiconductor device has the disadvantage that the region in which no element can be formed is equal to the sum of the respective diffusion lengths, and reaches approximately 10 μm. This value is larger than the element size, which has a minimum dimension of about 1.0 μm, and reduces the efficiency of integration.

On the other hand, by reducing the well diffusion length, the area where devices cannot be formed can be reduced, but the well diffusion length is closely related to circuit performance such as transistor performance and latch-up resistance. Therefore, the diffusion length cannot be reduced.

Therefore, an object of the present invention is to provide a method of manufacturing a semiconductor device that can reduce the area where elements cannot be formed without reducing the diffusion length of the well.

[Means to solve the problem]

A method for manufacturing a semiconductor device according to claim 11 includes the steps of: forming a band-shaped mask pattern in a shape along a predetermined well boundary on a semiconductor substrate; a step of diffusing a first type of impurity using a first pattern formed between mask patterns and the mask pattern as a mask; and a second pattern corresponding to an inverted pattern of the first pattern and the mask pattern. This process includes the step of diffusing the second type of impurity using the mask as a mask.

The method for manufacturing a semiconductor device according to claim (2) is the method according to claim (1).
In this case, the first pattern is formed of a positive resist, and the second pattern is formed of either a negative resist or a spin-on glass.

The method for manufacturing a semiconductor device according to claim (3) includes the steps of: forming a band-shaped mask pattern in a shape along a preset well boundary on a semiconductor substrate; and having an edge on the mask pattern. A step of patterning one of phosphorus glass and boron glass between the mask patterns, and diffusing phosphorus or boron, which becomes the other of the phosphorus glass and boron glass, using the one of the phosphorus glass and boron glass and the mask pattern as a mask. and a step of diffusing the one.

[Effect]

According to the method for manufacturing a semiconductor device according to claim (1), since the region where the first type of impurity is implanted and the region where the second type of impurity is implanted are separated by a certain distance due to the mask pattern, the diffusion length of each impurity is When is constant, the range in which impurities interpenetrate becomes smaller. Therefore, the region where elements cannot be formed can be reduced without reducing the diffusion length of the well compared to the conventional method.

According to the method of manufacturing a semiconductor device according to claim (2), when the first pattern is formed of a positive resist and the second pattern is formed of a negative resist 1- or a spin-on glass, the positive resist is formed into the second pattern. According to the method for manufacturing a semiconductor device according to claim (3), one of phosphorus glass and boron glass for forming one of the wells can be used as a mask. Since this is patterned between mask patterns and used as a mask for forming the other well, it is possible to reduce the number of masks.

〔Example〕

A first embodiment of this invention will be described based on FIGS. 1 and 2. In other words, the method for manufacturing this semiconductor device is as follows:
It consists of the steps from FIG. 1(a) to fdl.

In the step shown in FIG. 1(a), a mask oxide film 2, which is a band-shaped mask pattern, is formed along a preset well boundary on a semiconductor substrate 1. The mask oxide film 2 has a thickness of about 5.
In the example, the width is 5 μm. Note that the mask oxide film 2
does not need to be an oxide film formed by the LOCO5 method. 3
is 5j02.

The figure (bl) shows the pattern of the N-well resist mask 4, which is the first pattern formed between the mask oxide films 2 and having an end on the mask oxide film 2, and the pattern of the N-well resist mask 4, which has an end on the mask oxide film 2 and is formed between the mask oxide films 2, and P+ (phosphorus) 8, which is an impurity of type 1
is ion-implanted. At this time, the alignment between the N-well resist mask 4 and the mask oxide film 2 is approximately ±1.5 μm, which is sufficient. Therefore, a reduction projection exposure machine is sufficient for wafer level alignment, and a full-scale projection exposure machine may be used only for this portion.

In the same figure (cl is the second pattern of the P-well resist mask 5 corresponding to the inverted pattern of the N-well resist mask 4 and the second type of impurity B" (boron) using the mask oxide film 2 as a mask. In this case, before patterning the P well resist mask 5, the N well resist mask 4 shown in FIG.
remove. The alignment in this process is also shown in the same figure (b
) using the same method.

The same figure (dl is N after each impurity is diffused by heat treatment.
A state in which well 6 and P well 7 are formed is shown.

According to this embodiment, since the implantation region of the first type impurity and the implantation region of the second type impurity are separated by a certain distance due to the mask pattern, if the diffusion length of each impurity is constant, the impurities are mutually separated. The range of penetration becomes smaller. Therefore, without reducing the well diffusion length compared to conventional methods,
The area where elements cannot be formed can be reduced.

That is, as shown in FIG. 2, an N-well implantation region 10 into which phosphorus 8 is ion-implanted and a P-well implantation region 11 into which boron 9 is ion-implanted are separated by a certain distance X by the mask oxide film 2. They are not in contact as in the conventional example shown in FIG. 12 is a well boundary portion. Therefore, especially if this distance X is thicker than each diffusion length (then,
The width of the region surrounded by dotted lines (indicated by diagonal lines), which is not suitable for device formation because both impurities diffuse together, is
It can be reduced by about half from 0 μm to 5 to 6 μm. Moreover, the diffusion length of the well is not reduced. As a result, it is possible to increase the area where both the N well 6 and the P well 7 are not diffused, thereby increasing the area in which a substantial element can be formed, thereby making it possible to further increase the density of the semiconductor integrated circuit. Note that the mask oxide film 2, which prevents both wells from being diffused, must remain unchanged throughout the diffusion process of the picture well.

Furthermore, with such a configuration of the N well 6 and the P well 7, the interwell breakdown voltage can be improved from about 50V to about 100V or more.

Further, by making the width of the mask oxide film 2 at the well boundary portion 12 particularly large, a substrate region can be left.

A second embodiment of the invention will be explained with reference to FIG. That is, this method of manufacturing a semiconductor device includes a step of forming a mask oxide film 2, which is a band-shaped mask pattern along preset well boundaries on a semiconductor substrate 1, and a step of forming an edge on the mask oxide film 2. forming a pattern of phosphor glass (PSG) 13 between the mask oxide film 2 having a portion;
This process includes the steps of depositing boron glass (BSG) 14 using phosphorus glass 13 and mask oxide film 2 as masks, and simultaneously heat-treating phosphorus glass 13 and boron glass 14 to diffuse both impurities.

In this way, the phosphorus glass 13 and the boron glass 14 are used as diffusion sources, and the phosphorus glass 13 is used as the boron glass 14.
By using a mask of 1, the N well and P well are
Can be formed simultaneously using two masks. Therefore, the number of masks can be reduced compared to the first embodiment.

In addition, as a modification, a method may be used in which the boron glass 14 is patterned in the opposite manner to the above, the phosphorus glass 13 is deposited thereon, and these are heat-treated at the same time.

A third embodiment of the invention will be described with reference to FIG. That is, in the method of manufacturing this semiconductor device in the second embodiment, instead of depositing boron glass 14, B'' (boron) ions are implanted using mask oxide film 2 and phosphorus glass 13 as masks.

As a modification, the combination may be reversed to that described above, that is, boron glass may be patterned and phosphorus (P) may be ion-implanted.

A fourth embodiment of the invention will be explained with reference to FIG. That is, in the first embodiment, the N-well resist mask 4, which is the first pattern, is formed of a positive resist, and the P-well resist mask 5, which is the second pattern, is formed of a negative resist. is formed by. Here, a negative resist has the property of being polymerized by light irradiation and easily soluble in a highly polar solvent, and a positive resist has a property of being decomposed by light irradiation and easily soluble in a nonpolar solvent.

First, in FIG. 5 (al is a mask oxide film 5 on the semiconductor substrate 1).
A pattern of N well resist mask 4 is formed, and P well resist mask 4 is formed.
” (phosphorus) 8 is ion-implanted. In the same figure (b3, a negative resist, which is a P-well resist mask 5, is applied to the entire surface, and the negative resist is etched until the surface of an N-well resist mask 4 is exposed. Then, the entire surface is irradiated with light to harden the negative resist, and at the same time, the N-well resist mask 4 is photo-decomposed.However, the N-well resist mask 4 has already been subjected to heat treatment and does not undergo much photo-decomposition. (C1 removes the N-well resist mask 4 using a positive resist developer.

At this time, since the negative resist is hardly removed because the polarity is different, an inverted pattern of the N-well resist mask 4 is formed. Subsequently, B" (boron) 9 is ion-implanted. In the same figure (cll indicates heat treatment, and as a result, an N well 6 and a P well 7 are formed.

In this embodiment, the N-well resist mask 4 is a positive resist, and the P-well resist mask 5 is a negative resist.
Since the number of masks can be reduced, the number of masks can be reduced.

In addition, as a modification of this embodiment, spin-on glass (Spin On Glass) is used instead of the negative resist.
) can be used. In that case, beta is used instead of light irradiation, and oxygen plasma or various resist removal solutions or acids are used instead of a positive resist developer.

In addition, if you only want to reduce the number of masks, you can use both positive and negative resists on one mask, or even if you use only positive resists, you can use post-processing called image reversal (after exposure). exposed to an ammonia atmosphere,
It is possible to use a method in which the pattern is processed so that the pattern remains in the exposed area.

〔Effect of the invention〕

In the method for manufacturing a semiconductor device according to claim (1), since the first type impurity implantation region and the second type impurity implantation region are separated by a certain distance due to the mask pattern, the diffusion length of each impurity is kept constant. In this case, the range in which impurities penetrate into each other becomes smaller, and therefore, there is an effect that the area where an element cannot be formed can be reduced without reducing the diffusion length of the well compared to the conventional case.

In the method for manufacturing a semiconductor device according to claim (2), when the first pattern is formed of a positive resist and the second pattern is formed of a negative resist or spin-on glass, the positive resist is used as a mask for the second pattern. Therefore, it is possible to reduce the number of masks.

The method of manufacturing a semiconductor device according to claim (3) includes patterning one of phosphorus glass and boron glass for forming one of the wells between the mask patterns, and further patterning this for forming the other of the wells. This makes it possible to reduce the number of masks.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram for explaining the first embodiment of the present invention, FIG. 2 is an explanatory diagram for explaining the state of diffusion of impurities at the well boundary, and FIG. 4 is an explanatory diagram of the third embodiment, FIG. 5 is an explanatory diagram of the fourth embodiment, FIG. 6 is an explanatory diagram of the conventional example, and FIG. 7 is an explanatory diagram of the diffusion state of impurities at the well boundary. FIG. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Mask oxide film which is a mask pattern, 4... N-well resist mask which is a first pattern, 5... P-well resist mask which is a second pattern, 6 ...N well, 7...P well, 8...P" (phosphorus), 9...B" (boron) Patent applicant Matsushita Electronics Co., Ltd.

Claims (3)

[Claims] (1) A step of forming a band-shaped mask pattern along a preset well boundary on a semiconductor substrate, and a step of forming a band-shaped mask pattern having an edge on the mask pattern and between the mask patterns. a step of diffusing a first type of impurity using a first pattern and the mask pattern as a mask; and a second step of diffusing a first type impurity using a second pattern corresponding to an inverted pattern of the first pattern and the mask pattern as a mask.
and diffusing impurities of the type. (2) The method for manufacturing a semiconductor device according to claim (1), wherein the first pattern is formed of a positive resist, and the second pattern is formed of either a negative resist or a spin-on glass. (3) forming a band-shaped mask pattern along a preset well boundary on a semiconductor substrate; a step of patterning one of the glasses; and a step of diffusing phosphorus or boron, which is the other of the phosphorus glass and boron glass, using the one of the phosphorus glass and the boron glass and the mask pattern as a mask, and diffusing the one. A method for manufacturing a semiconductor device including: