JPH02202736A - Bit buffer circuit - Google Patents

Abstract

PURPOSE:To transfer all effective parts of transfer data at the time of transferring the data by providing a write address generating means, a slip control means, a read-out address generating means and a memory. CONSTITUTION:A write address generating means 2 inputs a data enable signal by using a write clock, detects its variation point, and applies a detecting signal as a write load signal to a write address generating part of the inside. Subsequently, the write address generating part generates successively write address from an initial value which is set and adds it to a memory 5, therefore, input data is written successively in parallel to the corresponding part, but the data is delayed by a repeated synchronous portion of the address. On the other hand, the write load signal detects a variation point by using a read-out clock by a slip control means 3, applies a detecting signal to a read-out address generating means 4 and generates successively a read-out address from an initial value and adds it to the memory 5. Accordingly, from the corresponding part, all effective parts can be transferred.

Description

[Detailed Description of the Invention] [Summary] For example, the bit and
Regarding buffer circuits, when transferring data, the purpose is to transfer all the valid part of the transferred data, and converts input data synchronized with the write clock to data synchronized with the read clock, which is asynchronous to the write clock. In a bit buffer circuit, data is written to the part corresponding to the input write address, and the memory from which the written data is read from the part corresponding to the input read address is in phase with the input data and the input data is in the same phase as the input data. A write load signal synchronized with the write clock is generated using the changing point of the data enable signal whose state changes depending on the valid part and invalid part, and the write load signal is used to sequentially write from the initial value set. write address generation means for generating an address; slip control means for generating a read load signal synchronized with the read clock using a change point of the write load signal; A read address generating means for sequentially generating read addresses from values is provided.

For this reason, a bit buffer circuit synchronizes the data from the transmission line with the device clock and transfers it to the synchronous terminal device, but a slip occurs due to the phase difference between the input clock and the device clock. Transfer data may be missing or duplicated.

Therefore, when transferring data, it is necessary to ensure that all valid parts of the transferred data can be transferred.

Furthermore, the valid part and invalid part of data are 1. For example, if the data is a telephone signal, the part of the telephone signal itself is the valid part;
Surplus bits added for device control, such as parity calculation results, are considered invalid parts.

[Industrial application field]

The present invention relates to a bit buffer circuit used, for example, in a synchronous terminal device for data transmission.

In general, the input side clock extracted from the data input via the transmission line is accompanied by jitter, so it is asynchronous with the clock used on the synchronous terminal equipment side. [Prior art] Figure 5 is a block diagram of a conventional example. , FIG. 6 shows an explanatory diagram of the operation of FIG. 5. Here, the symbols on the left side of FIG. 6 indicate waveforms corresponding to the same symbols in FIG. 5 below with reference to Figure 6.
The operation of the diagram will be explained.

First, the data shown in Figure 6 - ■ and ■ and the write clock (
(hereinafter abbreviated as WCK) is input.

Data synchronized with WCK is output (see Figure 6-■)
.

On the other hand, when WCK is added to FF 12 and read clock (hereinafter abbreviated as RCK) is added to FF 13,
At the rising point of these clocks, the output of FF 12.13 changes from 0 to 1, but this 1 changes from NAND gate 14.
NAND is taken and changes from 1 to 0. 7 then N
The output of the ANlog gate is τ in the delay circuit 15. It was delayed a lot.

Since FF 12.13 is reset, FF 12.13
The output of the NAND gate changes from 1 to 0, and the output of the NAND gate changes from 0 to 1. Therefore, at the rising point of the output of the delay circuit (hereinafter abbreviated as TCK), the output of FF 11 becomes FF
16 (see FIG. 6-■ to ■).

Then, the data synchronized with TCX is sent to FF17 with RCK.
Therefore, data synchronized with RCK is output (see Figure 6-■).

[Problem to be solved by the invention]

Here, FIG. 7 is an explanatory diagram of the problem; FIG. 7(a) is an explanatory diagram of the case of missing data, and FIG. 7(b) is an explanatory diagram of the case of data duplication.

First, in FIG. 7(a), the output of the FF 11 shown in FIG. 7-■ is input to the FF 16 using the TCK output from the delay circuit 15, but the output of the FF 11 shown in FIG. 7(a)-■1. ■As shown in 1, the RCK required to generate the dotted line TCK is not input, so FF 16. FF 11 data 3
cannot be input, and data 3 is missing (Figure 7(a)-■
.

■“See).

Next, in FIG. 7, all of the output of FF 11 is input to FF 16 using TCK (FIG. 7 (g)) -■,
■, ■"), but while data 5 is input to FF 16, RCK is input twice to FF 17, so data 5 is duplicated (Fig. 7 ■) - ■゛', ■′、■
For reference, a slip occurs in the part where the phase difference between WCK and RCK fluctuates, resulting in data loss and one duplication.

Since it is not known where this slip occurs, there is a problem in that a valid part of the data may be lost.

[Means to solve problems]

FIG. 1 shows a block diagram of the principle of the present invention.

In the figure, 5 is a memory in which data is written to the part corresponding to the input write address and written data is read from the part corresponding to the input read address, and 2 is in phase with the input data, and the memory 2 is in phase with the input data. A write load signal synchronized with the write clock is generated using the changing point of the data enable signal whose state changes depending on the valid part and invalid part, and the write load signal is used to sequentially write from the initial value set. This is a write address generation means that generates an address.

Further, 3 is a slip control means that generates a read load signal synchronized with the read clock using the change point of the write load signal, and 4 is a slip control means that sequentially reads from the initial value set using the read load signal. This is a read address generation means that generates an address.

[Effect]

In the present invention, a write clock is used to detect a change point of a data enable signal inputted to the write address generation means 2, and this detection signal is added to an internal write address generation section as a write load signal. Therefore, the write address generation section sequentially generates write addresses from the set initial value and adds them to the memory 5, so the input data is written to the corresponding sections in parallel in sequence, but the written data is generated at the repetition period of the write address. It will be extended by a minute.

On the other hand, the above write load signal is transmitted to the slip control means 3.
The change point is detected using the read clock, and this detection signal is synchronized with the read clock. Then, this detection signal is applied to the read address generation means to sequentially generate read addresses from the set initial value and add them to the memory, so that the written data is read from the corresponding portion.

Here, using the change point 2 of the data enable signal, for example, the change point from an invalid part to a valid part, the write load signal and read load signal are generated to force the write address and read address to initial values and align the phases. and make it the beginning of valid data.

At this time, if the speeds of the write clock and read clock are the same, the read addresses will be consecutive, missing, and there will be no duplication, but if they are different, the read address one before the initial value (which will be the address of the invalid part) will be missing. Therefore, invalid parts of the data are lost. Note that since initialization is not performed by anything other than the write load signal and the read load signal, the data written in the memory is sequentially read out using the read clock.

That is, when transferring data, all valid parts of the transfer data can be transferred.

〔Example〕

FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is an explanatory diagram of the operation of FIG. 2, and FIG. 4 is an explanatory diagram of the operation of FIG. 2 (when a slip occurs). Note that the symbols on the left side of FIGS. 3 and 4 indicate the operations of the portions with the same symbols in FIG.

Here, flip-flop 21. NAND gate 22
゜Write counter 23. Decoder 24. OR gates 25 to 29 are constituent parts of write address generation means 2;
Shift register 31. OR gate 32. Flip-flops 33, 34. The NAND gate 35 is a component of the slip control means 3, and the read counter 41. Decoder 4
2. The AND gates 43 to 47 are the constituent parts of the read address generation means 4, and the memory part 51. OR gate 52
．． Flip-flop 53 represents a component of memory 5.

The operation shown in FIG. 2 will be explained below with reference to FIGS. 3 and 4.

First, write data synchronized with the write clock (hereinafter abbreviated as WCK) is input to the memory 51 as shown in FIG. data enable signal (hereinafter referred to as
(abbreviated as Di) is input. Here, Figure 3-■ is D
i, the 1 part is the valid part of the write data, 0
The part indicates an invalid part, so the data 1~ in Figure 3-■
3 is the invalid part.

Data 4 to 90 are valid parts.

Now, the input Di is FF 21 and NAND gate 2
2 to generate a write load signal shown in FIG.

Therefore, the initial value 001 is loaded as the initial value, but
This -CTR is a 5-ary counter, for example, and sequentially outputs count values from 0 to 4 to the decoder 24 as shown in FIG. The decoder 24 sequentially outputs write addresses corresponding to count values 0 to 4.

The write address is added to the memory 51 by ORing with WCK in OR gates 25-29.

As a result, as shown in Figure 3-0, 1, for example, address 0
Data 89. Data 90 is sequentially written into the address 1 portion, but since the frequency of WCTR is divided by 5, the write data is extended to a length of 5 bits as shown in Figure 3-0. For this reason, the read clock (hereinafter referred to as R
Even if there is a change in the WC (abbreviated as CK), it is possible to correctly switch from WC to RCK.

Next, the write load signal is input to a 2, for example, 3-bit shift register (hereinafter abbreviated as SR) 31, and
When the outputs are ORed by the OR gate 32, the write load signal is stretched to a length of 3 bits as shown in FIG.

Here, the reason why the write load signal is extended is to provide phase margin when switching from WCK to RCK.
If you extend the clock by more than one bit, you can almost certainly change the clock.

Now, the write load signal extended to 3 bits (hereinafter referred to as the clock switching signal) is sent to FF33 and FP.
34. A readout load signal is generated through a differentiating circuit made up of a NAND gate 35, and a counter (hereinafter referred to as
(abbreviated as RCTR) 41 (see Figure 3 - ■, ■).

Therefore, the initial value 0 is loaded into RCTR41, and 0 to 4
Since the count value of is repeatedly output, the decoder 42 generates a corresponding read address and sequentially turns on the AND gates 43 to 47.

As a result, the data written in the memory 51 is read out, and the OR gate 52. FF 53 through RcK
2. Synchronized data is output (see Figure 3 - [Phase], ■). That is, if WCK and RCK are at the same speed.

The written data is output as read data.

However, if RCK is slower than WCK, when the read address is 3, as shown in FIG. 4(a)-[phase]°, the read load signal shown in FIG. 4(a)-■ is RCT.
Input to R41 and read address becomes 0.

Read data 3 is missing, but this portion is invalid data.

In addition, if RCK is faster than −〇, then in Fig. 4 (
As shown in b) - [phase]'', the read address becomes 0 and then becomes 0 again, so data 4 is duplicated but not lost.

That is, when transferring data, all valid parts of the transfer data can be transferred.

〔Effect of the invention〕

As described in detail above, according to the present invention, when transferring data, there is an advantage that all the valid portions of the transferred data can be transferred.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is an explanatory diagram of the operation of Fig. 2, and Fig. 4 is an explanatory diagram of the operation of Fig. 2 (slip occurrence time), 5th
The figure shows a block diagram of a conventional example, FIG. 6 shows an operation explanation diagram of FIG. 5, and FIG. 7 shows a problem explanation diagram. In the figure, 2 is a write address generation means, 3 is a slip control means, 4 is a read address generation means, and 5 is a memory. Source of the present invention"Sato block diagram 躬图 Conventional block diagram of Ita 11　Fig. α Task explanation diagram Figure 7

Claims (1)

[Claims] In a bit buffer circuit that converts input data synchronized with a write clock into data synchronized with a read clock asynchronous to the write clock, data is written to a portion corresponding to an input write address, A memory (5) from which written data is read from the part corresponding to the input read address, and a data enable signal that is in phase with the input data and whose state changes depending on the valid and invalid parts of the input data. write address generation means (2) that generates a write load signal synchronized with a write clock using the write clock, and sequentially generates write addresses from an initial value set using the write load signal; Slip control means (3) that generates a read load signal synchronized with the read clock using the change point; and read address generation means that sequentially generates read addresses from the initial value set using the read load signal. (4) A bit buffer circuit comprising: