JPH0220026A - Field effect type semiconductor device - Google Patents

Abstract

PURPOSE:To facilitate an increase in the width of a gate, and to easily obtain a high gain and a high output by forming a source electrode of a viahole structure oppositely to the open end of a pectinated toothlike drain electrode, forming a gate electrode on an active region between the source electrode and a drain electrode open end, and providing a gate electrode so formed in a U shape as to surround the drain electrode. CONSTITUTION:A second source electrode 10 having a viahole 20 is formed partly on an active region 12 oppositely to the open end of a drain electrode 104, and U-shaped gate electrodes 12, 25 are respectively formed between first source electrode 103, the source 10 and the electrode 104. Further, a gate electrode connecting conductor 35 is so provided as to connect the electrodes 15, 25 therebetween. The width lga of the part 25 of the gate electrode newly becomes an operating region to enhance an output. Further, since the distance from a gate power supply point to the open end of the electrode 15 is the same as that of a conventional case, its gain is not reduced.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Field of Application) The present invention relates to a field-effect semiconductor device, and particularly to a power-use field-effect semiconductor device used in microwave and millimeter wave bands. .

(Prior Art) Field-effect transistors made of gallium arsenide (GaAs) (hereinafter referred to as GaAs) are currently used as power amplifying elements for microwave communication systems, radar systems, etc.
(abbreviated as FET) is the mainstream.

Figure 2 shows a schematic top view of a power GaAs FET.

This will be explained.

An active region (102) (inside the dotted line) that becomes a channel is formed in a semi-insulating GaAs substrate (101) by ion implantation, and a source electrode (103) and a drain electrode, which are ohmic electrodes, are formed in the active region. (104) and the Schottky or pn junction gate electrode (105),
It has a structure in which a large number of them are arranged in one direction, the number determined by the desired output. The plurality of drain electrodes (104) and gate electrodes (+05) are formed by a drain electrode connecting conductor part (114) and a gate electrode connecting conductor part (114) formed on the semi-insulating GaAs substrate (101) outside the active region, respectively.
ITS), and each electrode has a comb-teeth shape. Further, both the conductor portions ((114).

(115)) is also used as a place for fixing bonding wires for electrical connection to an external circuit.

Furthermore, the source electrode (103) is shown in FIG.
As shown in the schematic cross-sectional view along line A), a through hole (101) is formed in the GaAs substrate (101) by etching,
G
It is electrically connected to the ground electrode (107) on the back surface of the aAs substrate.

The via-hole structure can greatly reduce the parasitic impedance component generated around the source electrode, which can increase the power gain of the transistor, and is particularly useful for improving the performance of power GaAs FIETs that operate in the microwave and millimeter wave bands above the U band. This is an advantageous structure for achieving this goal.

(Problems to be Solved by the Invention) By the way, there are two important points that must be taken into consideration when attempting to increase the gain with the above FET.

The first point is that there is a limit on the gate finger length (CRgf (FIG. 2)) in order to keep microwave attenuation due to gate resistance in the gate finger direction small. For example, in a 30GHzlFFET, 1 normal Q and f#8
It is designed to be 0μ or less, and the higher the frequency, the shorter the finger length needs to be.

The second point is multiple operating regions (area between source and drain)
The goal is to minimize the phase difference between the gate fingers and ensure uniform operation. To achieve this, the width of the active region in the direction perpendicular to the gate finger ((12t) (Figure 2)) should be set to the effective wavelength of the operating frequency (λart). It needs to be sufficiently small in comparison. Usually, as a guideline, it is about 1/8 or less of the effective wavelength.

For example, for frequency 300)Iz, λerr/8
L: 500 μm, and the higher the frequency, the smaller it needs to be.

On the other hand, in order to obtain high output, it is necessary to make the operating region (gate width = gate finger length x number of gate electrodes is used as an index to express its size) as large as possible.
The gate finger length and the active region width (12t) are subject to the above limitations, and the source electrode width ((Q,
) (FIG. 2)) requires a thickness of at least about 50 μm in order to form Pi7 holes stably and uniformly, so there is a limit to the number of gate electrodes arranged. For this reason, in particular, the F of this structure operates at ultra-high frequencies above the Ku band.
With ET, it becomes difficult to secure the required gate width,
Therefore, there was a problem in that it was difficult to obtain high output.

The present invention has been made in view of the above problems, and it becomes easier to increase the gate width, thereby making it easier to obtain high gain and high output.

[Structure of the invention]

(Means for Solving the Problems) In order to achieve this object, in the present invention, a source electrode having a via hole structure is formed opposite to the open end of a comb-toothed drain electrode, and the source electrode and the drain electrode The device is characterized in that a gate electrode is also formed on the active region between the open ends, and the gate electrode is formed in a U-shape so as to surround the drain electrode. In other words, the FET of the present invention includes a ground electrode formed on the back surface of a semi-insulating semiconductor substrate, and a plurality of ohms arranged in one direction on an active region forming a channel formed on the surface of the semiconductor substrate. a rectangular drain electrode, and a drain electrode connecting the drain electrodes to each other in a comb tooth shape on the semiconductor substrate outside the active region, with the open end of the drain electrode being inside the active region edge. a first source electrode formed on both sides of the drain electrode to be electrically connected to the ground electrode on the back surface of the semiconductor substrate through a via hole; a second source electrode electrically connected to the ground electrode through a via hole;
A U-shaped gate electrode is formed between a source electrode and a drain electrode so as to surround the drain electrode, and a gate electrode connecting conductor portion connects the gate electrodes.

(Function) In this structure, the part that was conventionally used as a conductor to simply connect gate electrodes becomes the gate electrode, so the gate width can be made larger without reducing the gain, resulting in higher A GaAs FET with high output power can be realized.

(Embodiment) An FET according to an embodiment of the present invention will be described below with reference to FIG. In addition, in the description, parts that are the same as in the prior art are indicated by the same reference numerals as in the prior art in the drawings, and the description thereof will be omitted.

Opposed to the open end of the train electrode (104) in FIG.
A second source electrode (lO
) is partially provided on the active region (12),
A U-shaped gate electrode (15, 25) is provided between the first source electrode (103) and the second source electrode (10) and the drain electrode (104). Further, a gate electrode connecting conductor portion (35) is provided for connecting the gate electrodes (15, 25) to each other.

With the above structure, the width (h,
) becomes a new operating region, and high output can be achieved. Moreover, since the distance from the gate feed point (the gate electrode (15°25) end of the gate electrode connecting conductor (35) closest to the gate electrode) to the open end of the gate electrode (15) is the same as in the conventional case, the gain is No decline occurs. For example, 30
GIIzf200m11 class FET is n,, H40μ
ya, Q and f'': 80 μm, and the number of gate electrodes is 10, so the gate width can be increased by n, lIX 5: 200 μI compared to the conventional FET structure (Fig. 2), and the gate width increases by about 25%, so the output can be increased by about 1 dB.

Note that a conductor may be formed to further connect the gate electrode connecting conductor portions (35) to each other, and this is advantageous because it becomes easier to fix the bonding wire when connecting to an external circuit using the bonding wire. Further, in this embodiment, a GaAs FET has been described, but it goes without saying that the present invention can also be applied to FETs using other semiconductor materials such as SL, InP, etc.

Furthermore, the present invention can also be applied to a monolithic integrated circuit (MMIC) in which the present FET is formed as a part.

〔Effect of the invention〕

As described above, according to the present invention, since the active region can be used effectively, integration can be achieved, and a field-effect semiconductor device with high gain and high output can be obtained, especially in the ultra-high frequency band. can.

[Brief explanation of the drawing]

FIG. 1 is a top view of a GaAs FET according to an embodiment of the present invention, FIG. 2 is a top view of a conventional GaAs FET,
FIG. 3 is a sectional view taken along line AA in FIG. 2. 10--------------- Source electrode 20 of part 2, 113----- Via hole 12.102 --- Bulk region 15 , 25.
105------ Gate electrode 35, 115---
- Gate electrode connection conductor part 103---
Source electrode 104 - drain electrode 114 --------------------
Drain Electrode Connection Conductor Department Agent Patent Attorney Norihiro Ogo
Husband diagram diagram diagram

Claims (1)

[Claims] A ground electrode formed on the back surface of a semi-insulating semiconductor substrate,
A plurality of ohmic rectangular drain electrodes are arranged in one direction on an active region forming a channel formed on the surface of the semiconductor substrate, and the drain electrodes are combed together on the semiconductor substrate outside the active region. A drain electrode connecting conductor part connects the open end of the drain electrode in the shape of a tooth so as to be inside the edge of the active region, and a ground electrode on the back surface of the semiconductor substrate and via holes are provided on both sides of the drain electrode for electrical connection. a first source electrode formed connected to the ground electrode; and a second source electrode formed at least partially on the active region on the open end side of the drain electrode and electrically connected to the ground electrode through a via hole. a U-shaped gate electrode formed between the first and second source electrodes and the drain electrode so as to surround the drain electrode, and a gate electrode connecting conductor portion that connects the gate electrodes. A field effect semiconductor device comprising: