JPH02199861A - Ferroelectric memory - Google Patents
Ferroelectric memoryInfo
- Publication number
- JPH02199861A JPH02199861A JP1017619A JP1761989A JPH02199861A JP H02199861 A JPH02199861 A JP H02199861A JP 1017619 A JP1017619 A JP 1017619A JP 1761989 A JP1761989 A JP 1761989A JP H02199861 A JPH02199861 A JP H02199861A
- Authority
- JP
- Japan
- Prior art keywords
- ferroelectric
- changed
- read out
- polarization
- deltap
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 27
- 230000010287 polarization Effects 0.000 claims abstract description 26
- 230000002269 spontaneous effect Effects 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims description 14
- 238000010438 heat treatment Methods 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052721 tungsten Inorganic materials 0.000 abstract description 2
- 239000010937 tungsten Substances 0.000 abstract description 2
- 101100491857 Columba livia ASL gene Proteins 0.000 abstract 4
- 238000010586 diagram Methods 0.000 description 7
- 230000007423 decrease Effects 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000001066 destructive effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002966 varnish Substances 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は強誘電体を用いたメモリに関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a memory using ferroelectric material.
従来の強誘電体メモリについては、アイ・ニス・ニス・
シー・シー・88(1988年)第130頁から131
頁(ISSCG8g、1988. p p、130−1
31)で論じられている。Regarding conventional ferroelectric memory, eye, varnish, varnish,
C.C. 88 (1988) pp. 130-131
Page (ISSCG8g, 1988. p p, 130-1
31).
上記従来技術は、第2図に示す構造、すなわち、スイッ
チングMOSトランジスタと強誘電体キャパシタを用い
たDRAM型のメモリセルが用いられていた。この従来
型のメモリセルの場合1強誘電体の分極という形で蓄え
られた記憶情報を1分極をもとに戻す際の電荷量変化で
読み出す。すなわち、記憶情報を読み出す際に情報が破
壊される問題点があった。The conventional technology described above uses a DRAM type memory cell having the structure shown in FIG. 2, that is, a switching MOS transistor and a ferroelectric capacitor. In the case of this conventional memory cell, stored information stored in the form of polarization of a ferroelectric material is read out by the change in the amount of charge when the polarization is returned to its original state. That is, there is a problem in that the information is destroyed when reading the stored information.
本発明の目的は、非破壊の記憶情報読み出しのできるメ
モリセルを提供することにある。An object of the present invention is to provide a memory cell from which stored information can be read out non-destructively.
上記目的を達成するために、本発明では第1図(b)に
示す強誘電体自発分極の温度依存性を利用する。すなわ
ち、読み出し時にメモリセルの温度を上昇させ、自発分
極が減少する際の蓄積電荷斌変化を読み出す方式を用い
る。In order to achieve the above object, the present invention utilizes the temperature dependence of ferroelectric spontaneous polarization shown in FIG. 1(b). That is, a method is used in which the temperature of the memory cell is increased during reading, and the change in accumulated charge when the spontaneous polarization decreases is read out.
本発明は1強誘電体キャパシタとキャパシタ中を貫く発
熱素子で構成されている。読み出し時に、発熱素子に電
圧を印加し発熱させ、強Mttt体キャパシタを加熱す
る。加熱された強誘電体は自発分極が減少し、この容量
減少に従ってキャパシタ電極電位が変化する。The present invention is composed of a ferroelectric capacitor and a heating element that penetrates through the capacitor. At the time of reading, a voltage is applied to the heating element to generate heat, thereby heating the strong Mttt body capacitor. Spontaneous polarization of the heated ferroelectric substance decreases, and the capacitor electrode potential changes as the capacitance decreases.
すなわち、キャパシタ電位Vは(1)式で与えられる。That is, the capacitor potential V is given by equation (1).
V=Q/C・・・(1)
(ここでQはM積電荷量、Cは強誘電体キャパシタの容
量値)この■の値は、強?R重体の自発分極減少に伴う
誘電率の減少ΔCによって(2)式の様に変化する。V=Q/C...(1) (Here, Q is the M product charge, and C is the capacitance value of the ferroelectric capacitor) Is the value of this ■ strong? It changes as shown in equation (2) due to the decrease ΔC in the dielectric constant due to the decrease in the spontaneous polarization of the R-heavy body.
ΔV=−−ΔC・・・(2) ここでΔ■はキャパシタ電位の変化量である。ΔV=−−ΔC...(2) Here, Δ■ is the amount of change in the capacitor potential.
ΔVの符号は強誘電体の分極ベクトルの向きによってプ
ラス又はマイナスとなるので、加熱時のキャパシタ電位
の符号の変化で分極ベクトルの向きを測定できる。Since the sign of ΔV is positive or negative depending on the direction of the polarization vector of the ferroelectric material, the direction of the polarization vector can be measured by the change in the sign of the capacitor potential during heating.
この方式を用いれば、分極ベクトルの向きを変えること
なく、その向きを読み出すことができる。Using this method, the direction of the polarization vector can be read out without changing the direction.
すなわち、非破壊読み出しが実現できる。That is, non-destructive reading can be achieved.
以下、本発明の一実施例を第1図を用いて説明する。 An embodiment of the present invention will be described below with reference to FIG.
第1図(a)はタングステン(W)を用いた電極14及
び18と、例えば、P b(Zrz−xTit−x)O
s等の強誘電体15を用いた強誘電体キャパシタ、及び
、このキャパシタを上下に貫く、例えば高抵抗の多結晶
Si 19とそのWからなる配線12゜17で構成され
た強誘電体メモリを示す、情報を書き込む時は、W配線
(It極)14と18に電位差を与え、両電極ではさま
れた強誘電体15に所望の向きの分極を生じさせる。FIG. 1(a) shows electrodes 14 and 18 using tungsten (W) and, for example, Pb(Zrz-xTit-x)O
A ferroelectric capacitor using a ferroelectric material 15 such as S, and a ferroelectric memory configured with wiring 12° 17 made of, for example, high-resistance polycrystalline Si 19 and its W, which pass through this capacitor up and down. When writing information as shown in FIG. 1, a potential difference is applied between the W wiring (It poles) 14 and 18, and the ferroelectric material 15 sandwiched between the two electrodes is polarized in a desired direction.
読み出し時には5W配線12と17に電位差を与え多結
晶5i19に電流を流し発熱させて強誘電体キャパシタ
を加熱する。At the time of reading, a potential difference is applied between the 5W wirings 12 and 17 to cause current to flow through the polycrystalline 5i 19 to generate heat and heat the ferroelectric capacitor.
加熱された強誘電体は第1図(b)に示すように自発分
wpが温度の変化量Δ1゛に対してΔPだけ減少する。As shown in FIG. 1(b), the heated ferroelectric material has a spontaneous component wp which decreases by ΔP with respect to a temperature change amount Δ1.
強誘電体キャパシタの誘電率Cは、真空中の誘電率ε0
、自発分極P、it界Eを用いて、の様に表わされる。The dielectric constant C of the ferroelectric capacitor is the dielectric constant ε0 in vacuum.
, spontaneous polarization P, and it field E, it is expressed as follows.
この誘電率は、温度変化ΔTに伴う自発分極変化ΔPに
よって、次式に示すΔεだけ変化する。This dielectric constant changes by Δε shown in the following equation due to a spontaneous polarization change ΔP accompanying a temperature change ΔT.
Δ P
Δε=□ ・・・(
4)S電率が八とだけ炭化すると容量も(5,2)式の
ようにΔCだけ変化するため、(6)式に示す電圧。ΔP Δε=□ ・・・(
4) If the S electric rate is carbonized by 8, the capacitance also changes by ΔC as shown in equation (5, 2), so the voltage shown in equation (6).
値ΔVだけ容量電極電位が変化する。The capacitor electrode potential changes by the value ΔV.
C= t−8/ T −(
5,1)ΔC=Δε ・ S/T
・・・(5,2)ΔV=−−ΔC・・・(6)
二二でCは強誘電体キャパシタの容量s、Tはそれぞれ
キャパシタの面積と強誘電体の厚さである。C=t-8/T-(
5,1)ΔC=Δε・S/T
(5, 2) ΔV=−−ΔC (6) where C is the capacitance s of the ferroelectric capacitor, and T is the area of the capacitor and the thickness of the ferroelectric, respectively.
自発分極の変化量ΔPは、分極ベクトルの向きによって
正、負の値をとるため、読み出し時の容量電極電位の変
化量Δ■は、分極ベクトルの向きに応じて、正または負
の値をとる。従って分極の方向を知ることができる。Since the amount of change ΔP in spontaneous polarization takes a positive or negative value depending on the direction of the polarization vector, the amount of change Δ■ in the capacitor electrode potential during readout takes a positive or negative value depending on the direction of the polarization vector. . Therefore, the direction of polarization can be known.
以上述べたように、本発明を用いることによって、非破
壊で強誘電体の分極ベクトルの方向、すなわち、分極ベ
クトルの形で蓄積された情報を読み出すことができる。As described above, by using the present invention, the direction of the polarization vector of a ferroelectric material, that is, the information stored in the form of the polarization vector can be read out in a non-destructive manner.
第3図は第1の実施例の強誘電体メモリの製造方法を示
す一実施例である。FIG. 3 is an embodiment showing a method of manufacturing the ferroelectric memory of the first embodiment.
5iOz等の絶縁膜11上に厚さが例えば500nmの
W等を用いた配線12を形成する(a)。A wiring 12 made of W or the like and having a thickness of 500 nm, for example, is formed on an insulating film 11 of 5iOz or the like (a).
その上に5iOz等の絶縁膜13を化学気相成長法(C
V D)等を用いて500nm程度の厚さに形成する(
b)。On top of that, an insulating film 13 of 5iOz or the like is formed by chemical vapor deposition (C
VD) etc. to a thickness of about 500 nm (
b).
さらに配線を兼ねた厚さ500nm程度の例えばWを用
いた電極14を形成する(C)。Furthermore, an electrode 14 made of, for example, W and having a thickness of about 500 nm and also serving as wiring is formed (C).
次いで強誘電体材料、例えば、B a T x OJl
tP b (Z rx−xT i z−x)On、
KNOa、 N a NOx。Then a ferroelectric material, e.g. B a T x OJl
tP b (Z rx-xT i z-x) On,
KNOa, N a NOx.
SbS I、C(NHz)An(SOa)zl 2Hz
O。SbS I,C(NHz)An(SOa)zl 2Hz
O.
(N HzCHzC○OH)s・His Oa、(N
Ha)zs 041(NHz)zcSe Cazs r
(CzHsCOOH)a等をスパッタリング法にて被着
させキャパシタ用絶縁改15を20nm〜1μm程度の
厚さに形成する(d)、上記膜厚は、酵すぎると露誘電
性を示さなくなる場合があるので20nm程度が薄膜化
の限界と考えられる1強誘電体膜15上に配線を兼ねた
厚さ500nm程度の、例えばWを用いた電極18を形
成する(e)1次いでCVD法などににより、厚さ50
0nm程度の、例えば5iOzのような絶縁膜16を形
成する(f)。(N HzCHzC○OH)s・His Oa, (N
Ha)zs 041(NHz)zcSe Cazs r
(CzHsCOOH)a etc. is deposited by sputtering method to form capacitor insulation modification 15 to a thickness of about 20 nm to 1 μm (d).The above film thickness may not exhibit dew dielectric properties if fermented too much. Therefore, about 20 nm is considered to be the limit for thinning the film. 1. Form an electrode 18 made of, for example, W, with a thickness of about 500 nm, which also serves as wiring, on the ferroelectric film 15. (e) 1. Next, by CVD method or the like, Thickness 50
An insulating film 16 of about 0 nm, for example 5 iOz, is formed (f).
次に5iOz16、W2B、誘電体15゜W 14 、
S i Ox 131C穴31を形成した後(g)、
全面に1例えば化学気相成長法を用いて5iOz等の絶
縁膜を被着し、異方性のドライエツチングによって穴部
31の側壁に絶縁層111を形成する(h)0次いで穴
31内に高抵抗の多結晶5i19を埋めた(j)1例え
ば厚さ500nmのW等を用いた配線17を形成する(
j)。Next, 5iOz16, W2B, dielectric 15°W 14,
After forming the S i Ox 131C hole 31 (g),
An insulating film 111 of 5 iOz or the like is deposited on the entire surface using, for example, chemical vapor deposition, and an insulating layer 111 is formed on the side wall of the hole 31 by anisotropic dry etching. Form a wiring 17 using, for example, W with a thickness of 500 nm (j) 1 filled with a high-resistance polycrystal 5i19 (
j).
本実施例では、絶縁膜として5iOzを用いたが、絶縁
性と製造上の問題がなければ、他の絶縁膜を用いても何
ら支障ない。さらに1本実施例では配線、電極材料とし
てWを用いているが、AQ。In this embodiment, 5 iOz was used as the insulating film, but there is no problem in using other insulating films as long as there are no problems with insulation or manufacturing. Furthermore, in this embodiment, W is used as the wiring and electrode material, but AQ.
Mo、(:u、pt、Au、Ag、Ti、TiN。Mo, (:u, pt, Au, Ag, Ti, TiN.
WS it、 Mo S it、超電導配線材料等、各
種低抵抗材料を使用することが可能であることは勿論で
ある。Of course, various low resistance materials such as WS it, Mo S it, superconducting wiring material, etc. can be used.
第4図(a)、(b)は、本発明の一実施例のメモリセ
ルの平面レイアウトを示す、41は2本の配線層を示す
、この2本は上下に重なっている。FIGS. 4(a) and 4(b) show a planar layout of a memory cell according to an embodiment of the present invention. Reference numeral 41 indicates two wiring layers, which are vertically overlapped.
41の下側配線は、発熱体への給電用第1配線、41の
上側配線は、強誘電体キャパシタの上側な極兼配線であ
る。42もまた2本の配線層が上下に重なったものであ
る。42の下側配線は、強誘電体キャパシタの下側電極
兼配線、42の上側配線は発熱体への給電用第2配線で
ある。43は給電用第1配線層と給電用第2配線層間に
形成した穴であり、内部に発熱体を埋め込む、この第4
図の断面構造は第1図と同じ構造を持つ。The lower wiring 41 is the first wiring for feeding power to the heating element, and the upper wiring 41 is the upper pole wiring of the ferroelectric capacitor. 42 also has two wiring layers stacked one above the other. The lower wiring 42 serves as the lower electrode of the ferroelectric capacitor, and the upper wiring 42 serves as a second wiring for feeding power to the heating element. 43 is a hole formed between the first wiring layer for power feeding and the second wiring layer for power feeding;
The cross-sectional structure of the figure has the same structure as that of FIG.
縦、横に形成した配線の各交点に1つのメモリセルを形
成することができるため、レイアウトが簡単で、高集積
のメモリを作製することができる。Since one memory cell can be formed at each intersection of vertically and horizontally formed wiring, a highly integrated memory with a simple layout can be manufactured.
本発明によれば、非破壊で蓄積情報を読み出すことがで
き、しかも、高集積のメモリを提供できる。According to the present invention, stored information can be read out non-destructively and a highly integrated memory can be provided.
第1図(a)は発明の一実施例の断面図、第1図(b)
は強誘電体の自発分極と温度の関係を示す特性図、第2
図は強誘電体を用いた従来例のメモリセルの回路図、第
3図(a)〜(j)は本発明の一実施例のメモリセルの
製造工程を示す断面図、第4図(a)及び(b)は本発
明の一実施例のメモリセルの平面レイアウト図である。
11−8iO2,12−W、13−8iOx、14−W
、 15−P b (Z rl−xT i t−x)O
a、16・・・5iOz、17・・・W118・・・W
、19・・・多結晶Si、111・・・5iOz、21
・・・スイッチングMOSトランジスタ、22・・・強
誘電体キャパシタ、23・・・ビット線、24・・・ワ
ード線、25・・・パルス型共通プレート、31・・・
穴、41・・・第1.第3配線層、42・・・第2.第
4配線層、43・・・抵抗用埋め込み多結晶Si。
〃 1 図
(it)
rOz
//1
S゛θ2
丁G
臨辱鮎
晃
図
頁
図
罵
図FIG. 1(a) is a sectional view of one embodiment of the invention, FIG. 1(b)
is a characteristic diagram showing the relationship between spontaneous polarization and temperature of a ferroelectric material, the second
The figure shows a circuit diagram of a conventional memory cell using a ferroelectric material, FIGS. ) and (b) are plan layout diagrams of a memory cell according to an embodiment of the present invention. 11-8iO2, 12-W, 13-8iOx, 14-W
, 15-P b (Z rl-xT i t-x)O
a, 16...5iOz, 17...W118...W
, 19... Polycrystalline Si, 111... 5iOz, 21
... Switching MOS transistor, 22... Ferroelectric capacitor, 23... Bit line, 24... Word line, 25... Pulse type common plate, 31...
Hole, 41...1st. 3rd wiring layer, 42... 2nd. Fourth wiring layer, 43...buried polycrystalline Si for resistance. 〃 1 Diagram (it) rOz //1 S゛θ2 Ding G Rinku Ayu Akira Diagram Page Diagram Abusive Diagram
Claims (1)
体によって構成された強誘電体キャパシタと、該強誘電
体キャパシタのほぼ中央をほぼ垂直につらぬく周囲を絶
縁された導電体を持つことを特徴とする強誘電体メモリ
。 2、導電体に電圧を供給する配線を、強誘電体キャパシ
タの上及び下に少なくとも1本ずつ有することを特徴と
する特許請求の範囲第1項記載の強誘電体メモリ。 3、導電体に電圧を供給する上下の配線が互いに交差す
ることを特徴とする特許請求の範囲第2項記載の強誘電
体メモリ。 4、強誘電体キャパシタを加熱することによって強誘電
体の自発分極の絶対値|P|を変化させ、その際の極性
P/|P|を測定することにより分極の極性を調べるこ
とを特徴とする強誘電体メモリの読み出し方法。[Claims] 1. A ferroelectric capacitor constituted by two intersecting electrodes and a ferroelectric material formed between them, and an insulating periphery extending approximately perpendicularly through the center of the ferroelectric capacitor. A ferroelectric memory characterized by having a conductive material. 2. The ferroelectric memory according to claim 1, further comprising at least one wiring for supplying voltage to the conductor above and below the ferroelectric capacitor. 3. The ferroelectric memory according to claim 2, wherein the upper and lower wirings for supplying voltage to the conductor cross each other. 4. The method is characterized by changing the absolute value |P| of the spontaneous polarization of the ferroelectric material by heating the ferroelectric capacitor, and examining the polarity of the polarization by measuring the polarity P/|P| at that time. How to read ferroelectric memory.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1017619A JPH02199861A (en) | 1989-01-30 | 1989-01-30 | Ferroelectric memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1017619A JPH02199861A (en) | 1989-01-30 | 1989-01-30 | Ferroelectric memory |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02199861A true JPH02199861A (en) | 1990-08-08 |
Family
ID=11948894
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1017619A Pending JPH02199861A (en) | 1989-01-30 | 1989-01-30 | Ferroelectric memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02199861A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100415741B1 (en) * | 1999-08-26 | 2004-01-24 | 세미콘덕터 테크놀로지 아카데믹 리서치 센터 | Nonvolatile ferroelectric memory and method of manufacture thereof |
-
1989
- 1989-01-30 JP JP1017619A patent/JPH02199861A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100415741B1 (en) * | 1999-08-26 | 2004-01-24 | 세미콘덕터 테크놀로지 아카데믹 리서치 센터 | Nonvolatile ferroelectric memory and method of manufacture thereof |
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