JPH07202138A - Ferroelectric memory element - Google Patents

Abstract

PURPOSE:To manufacture a stabilized element by a method wherein a ferroelectric capacitor and a paraelectric capacitor are connected to the gate electrode of a transistor which stores information, and another electrode which is not the common electrode of the paraelectric capacitor is connected to a drain terminal. CONSTITUTION:A ferroelectric thin film 28 is series connected to a ferroelectric capacitor which becomes the constituent element of an insulating film, and a normal dielectric capacitor 26 is series connected to a paraelectric capacitor 2 which becomes an insulating film. The common electrode 27 of the ferroelectric capacitor 1 and the paraelectric capacitor 2 is connected to the gate electrode of a transistor which stores information by changing the current capacity using the prescribed threshold value, and the other electrode which is not the common electrode 27 of the paraelectric capacitor 2 is connected to the drain terminal of the transistor. In order to read out information, voltage is applied between terminals 5 and 6, and the conductivity and non-conductivity of the transistor is detected. As a result, information can be read out without changing the condition of polarization of the ferroelectric film, namely, information can be non-destructively read out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nondestructive read ferroelectric memory device. More specifically, by using the voltage generated across the ferroelectric capacitor or paraelectric capacitor due to the spontaneous polarization of the ferroelectric thin film, the MOSF
The present invention relates to a ferroelectric memory element that performs ET switching.

[0002]

2. Description of the Related Art Recently, a non-volatile memory utilizing spontaneous polarization of a ferroelectric material has been attracting attention and vigorous research has been conducted. As the ferroelectric material, for example, PZT (lead zirconate titanate), PbTiO ₃ , Bi ₄ Ti ₃ O ₁₂ , BaMgF ₄ or the like is used. Among them, PZT is known to produce a film with good c-axis orientation when grown on a Pt electrode, and is considered to be a promising material for commercialization. There are two main types of non-volatile memory using this ferroelectric material.
The following structures are considered, and they are a capacitor type and a MFS (Metal-Ferroelectric-Semiconductor) FET (F
ield-Effect-Transistor) type.

The capacitor type has a capacitor structure in which a ferroelectric thin film is sandwiched between electrodes, and information is read by detecting the presence or absence of a reversal current flowing when the spontaneous polarization of the ferroelectric material is reversed. Is. Normally, a memory cell is configured by using a switching transistor for cell selection as shown in the equivalent circuit of FIG. On the other hand, the MFSFET type uses the ferroelectric thin film 12 instead of the gate oxide film of the MOSFET as shown in FIG. 20, and utilizes the fact that charges are induced on the semiconductor surface by spontaneous polarization of the ferroelectric. Then, the conductivity of the channel is changed to read the memory cell information nondestructively.

[0004]

However, while the capacitor type can form a good-quality ferroelectric thin film on the Pt electrode or the like, it is a destructive reading in which the direction of spontaneous polarization changes at the time of reading. There is a drawback that you have to rewrite because it destroys information.

The MFSFET type is capable of nondestructive reading without destroying information at the time of reading, but since the ferroelectric thin film is formed directly on the semiconductor substrate, the interface state density is large and unstable. Further, there is a problem of reaction between the ferroelectric substance and the semiconductor such as formation of an oxide film on the surface of the semiconductor, and it is difficult to obtain a stable element having good interface matching.

In order to solve such a problem, as an extension of the MFSFET type, the gate has a double structure, and the ferroelectric thin film 12 is formed between the upper electrode 13 and the lower electrode 11 as shown in FIG. A structure has been proposed in which the paraelectric thin film 10 is formed between the lower electrode 11 and the semiconductor surface (Japanese Patent Laid-Open No. 49-49).
131646). According to this structure, the spontaneous polarization of the ferroelectric substance is caused by the dielectric substance 10 sandwiched between the lower electrode 11 and the semiconductor surface.
It is possible to modulate the conductivity of the channel through the polarization of.

However, in this structure, most of the voltage applied between the upper electrode 13 and the source 8 has a good compatibility with the paraelectric thin film 10 (generally, a good match with the silicon semiconductor) due to the large dielectric constant of the ferroelectric substance. SiO ₂ ) is more likely to be absorbed,
A high voltage is required to reverse the polarization. In order to invert the polarization at a low voltage, it is necessary to make the paraelectric thin film 10 as thin as possible and use a material having a high dielectric constant. However, in the former case, there are problems such as increase in leak current and decrease in breakdown voltage. However, in the latter case, similarly to the problem of the interface between the ferroelectric and the semiconductor, the consistency of the interface between the high dielectric constant material and the semiconductor becomes a problem, and it is difficult to manufacture a stable element.

[0008]

A ferroelectric memory device according to the present invention comprises a ferroelectric capacitor having a ferroelectric thin film as a constituent element of an insulating film and a paraelectric capacitor having a paraelectric thin film as an insulating film. Are connected in series, the common electrode of the ferroelectric capacitor and the paraelectric capacitor is connected to the gate electrode of a transistor that stores the information by changing the amount of current at a predetermined threshold, The other electrode of the capacitor, which is not the common electrode, is connected to the drain terminal of the transistor.

Further, the ferroelectric memory element is characterized in that a read transistor is added to the drain terminal.

The ferroelectric memory element has a structure in which the ferroelectric capacitor and the paraelectric capacitor are interchanged.

[0011]

As a preparation for explaining the operation of the ferroelectric memory element of the present invention shown in FIG. 1, first, the ferroelectric capacitor 1 and the paraelectric capacitor 2 as shown in FIG. 2 are connected in series. When a voltage is applied to both ends, consider how the voltage is applied to each capacitor. For the sake of simplicity, the Qf-Vf hysteresis of the ferroelectric capacitor is assumed as shown in FIG. Qf is the electric charge accumulated in the electrode of the ferroelectric capacitor, and Vf is the voltage across it. Qr and Vc in FIG. 3 are respectively remanent polarization (Pr) × electrode area,
Coercive electric field (Ec) × film thickness. When the voltage across the paraelectric capacitor is Vn and the accumulated charge is Qn, Qf = Qn = Cn Vn = Cn (Vw-Vf) (1). Here, Vw is a voltage applied across the capacitors connected in series.

In FIG. 3, when the state is on the straight line I, Qf = -Qr, and from the equation (1), Vf = Vw + Qr / Cn.
(Corresponding to I'in FIG. 4). Whenever the state is on the straight line II, Vf = Vc (corresponding to II 'in FIG. 4). Similarly, when the state is III or IV, Vf is
= Vw-Qr / Cn, Vf = -Vc (III ', I in FIG. 4)
It corresponds to V '). From this, the behavior of Vf with respect to Vw is as shown in FIG. As can be seen from FIG. 4, Vw =
When 0, Vf = Vf0 = Vc or Vf = -Vf0 = -Vc, and when Vf = 0, Vw = Vw0 = Qr / Cn or-
Vw0 = -Qr / Cn. Vf0 is MOSF as described later
Since it is the voltage for switching ET, it must be higher than the threshold voltage of the transistor. Also,
Since Vw0 is a voltage required to invert the polarization of the ferroelectric thin film, it is desirable that it be smaller. After all, as the characteristics of the ferroelectric capacitor, it is required that Qr is small and Vc> Vth.

A characteristic feature of FIG. 4 is that even when the voltage Vw across the series capacitor is 0, there is a finite difference between the two ends of the ferroelectric capacitor, and a positive or negative 2 depending on the hysteresis of the ferroelectric. The value of voltage is to occur. At this time, a voltage having the same magnitude and the opposite polarity is generated across the paraelectric capacitor. Therefore, choose a ferroelectric material, paraelectric material, film thickness, electrode area, etc. so that this voltage becomes higher than the threshold voltage Vth of the MOSFET, and connect either end of either capacitor between the gate and source of the MOSFET. For example, the transistor can be held in either the on state or the off state while Vw remains 0V.

In practice, the P-E hysteresis of the ferroelectric thin film (P is the polarization charge density induced on the ferroelectric surface, E
The applied electric field) is as shown in FIG. 5, and accordingly, the relationship between the voltage across the series capacitor and the voltage across the ferroelectric capacitor is as shown in FIG.

If the gate-source capacitance of the MOSFET 3 in FIG. 1 has no voltage dependency, the equivalent circuit between the terminals 4 and 6 can be considered to be that shown in FIG. Therefore, it can be considered that the relationship between the voltage Vw applied between the terminals 4 and 6 in FIG. 1 and the voltage Vf applied to the ferroelectric capacitor 1 is also as shown in FIG. In reality, the capacitance between the gate and the source depends on the voltage and is asymmetric with respect to the positive / negative of the applied voltage. Therefore, as shown in FIG. 6, the Vw-Vf characteristic is not strictly symmetrical with respect to the origin. However, if this capacitance is sufficiently smaller than the capacitances of the capacitors 1 and 2, such effect can be ignored.

When the voltage Vw is 0 V, a voltage of + Vf0 or -Vf0 appears across the ferroelectric capacitor 1 in accordance with the polarization direction of the ferroelectric substance, as shown in FIG. At the same time, a voltage of equal magnitude and opposite polarity appears across the paraelectric capacitor 2, and thus between the gate and source of the MOSFET 3. If the MOSFET 3 is an n-channel, Vf = -Vf0
When Vf = + Vf0, it is turned on, and when Vf = + Vf0, it is turned off.
However, Vf0 is assumed to be higher than the threshold voltage Vth of the MOSFET. If the MOSFET 3 is a p-channel, Vf =
When + Vf0, it is turned on, and when Vf = -Vf0, it is turned off. In this way, the polarization state of the ferroelectric capacitor 1 can be associated with the on / off state of the transistor.

Information can be read out by applying a voltage between the terminals 5 and 6 and detecting conduction / non-conduction of the transistor. Therefore, the information can be read out without changing the polarization state of the ferroelectric film, that is, non-destructively. You can

To rewrite the information, for example, in the state of "a" in FIG. 6, after applying a voltage of Vw> Vsw, Vw =
When it is set to 0, the polarization state shifts to the state b, and the information is rewritten. Similarly, in order to change from the state a to the state b, it is sufficient to set the voltage Vw <−Vsw and then set Vw = 0.

When the ferroelectric capacitor 1 and the paraelectric capacitor 2 are replaced with each other, the gate and source of the MOSFET 3 are connected to both ends of the ferroelectric capacitor, so that the write voltage is positive (terminal 6) in the case of n-channel. Based on)
Is on, when it is negative, it is off, and vice versa for p-channel.

[0020]

【Example】

Example 1 FIG. 7 shows an equivalent circuit configuration for forming a memory cell using the ferroelectric memory element of the present invention.

The write operation is performed in the following procedure. A voltage is applied to the word line 15 of the cell to be written to turn on the cell selection transistor 14, and a voltage is applied to the bit line 16. The voltage applied to the bit line at this time corresponds to Vw in FIG. 9 and has an appropriate magnitude (> Vs).
If the pulse of w) is applied, the voltage (Vf0) across the paraelectric capacitor 2 when the bit line voltage is held at 0V
Can be changed from positive to negative or from negative to positive.
Since the absolute value of this voltage is set to be larger than the threshold voltage Vth of the transistor 3, the transistor 3 is held on or off.

In the read operation, the potential of the word line 15 of the cell to be read is raised to turn on the cell selecting transistor 14 and the potential of the bit line 16 is raised. The memory cell transistor 3 forming the memory element is conductive when it is on, and does not conduct when it is off. However, since the potential of the bit line at this time is also applied to both ends of the ferroelectric capacitor, it is necessary to suppress it so that the polarization of the ferroelectric thin film is not inverted. The on / off state of the cell is detected nondestructively by detecting the difference between these current values.

FIG. 8 shows an example of pulses applied to the word line 15 and the bit line 16 of the selected cell in these writing and reading operations. However, FIG. 8 shows a case where both the memory cell transistor 3 and the cell selecting transistor 14 are n-channel. When a positive pulse is applied to the bit line, the electrode on the side where the voltage across the paraelectric capacitor 2 is connected to the source of the transistor 3 becomes high potential, and the transistor is turned off. Conversely, when a negative pulse is applied to the bit line, it turns on. When the memory cell transistor 3 is a p-channel, on and off are reversed. At this time, the word line and bit line not including the selected cell are kept at 0V.

The above memory cell was actually manufactured as follows. The structure is shown in FIGS. FIG. 9 is a plan view of the memory cell. 10, 11, and 12 are cross-sectional views taken along alternate long and short dash lines a, b, and c in FIG. Two MOSFETs were formed by forming the polysilicon gate electrodes 17 and 18, the gate oxide films 19 and 20, and the n ⁺ impurity diffusion regions 21 to 24 on the p-type silicon semiconductor substrate 30 by a conventional technique. Both gate lengths are 1 μm. In order to electrically connect the source and drain of the two adjacent MOSFETs with the element isolation region sandwiched therebetween, a Pt electrode 25 is formed with a thickness of 200 nm by a sputtering method, and is used as a base electrode on the element isolation region. A dielectric Ta ₂ O ₅ thin film 26 (thickness: 50 nm) and a Pt electrode 27 (thickness: 200 nm) common to both the ferroelectric capacitor and the paraelectric capacitor were formed thereon by a sputtering method. Next, the ferroelectric PZT thin film 28 (thickness 300 n
m) is formed by MOCVD, the upper Pt electrode 29 (film thickness 2
00 nm) was formed by the sputtering method. The electrodes, the dielectric material, and the forming method may be any as long as desired characteristics can be obtained. To process these electrodes and dielectric film, a resist mask was formed into the shape by a photolithography technique, and then etching was performed. The area of the capacitor was 2 μm × 4 μm for the paraelectric capacitor and 2 μm × 2 μm for the ferroelectric capacitor. After that, the interlayer insulating film NSG3
2 was formed, and contacts 33 to 35 with Al wiring were formed. The contacts 33, 34 and 35 are connected to the sense amplifier, the ground line and the bit line, respectively. The gate of the memory cell transistor and the common Pt electrode of the ferroelectric capacitor / paraelectric capacitor are connected as shown by the Al wiring 36 in FIG.

Embodiment 2 Another embodiment of a memory cell using the ferroelectric memory element of the present invention is shown in the equivalent circuit of FIG. In this case, the cell line selection transistor is not used, and the word line 15 and the bit line 1
Only 6 writes and reads.

The pulse applied to the word line 15 and the bit line 16 of the selected cell at the time of writing and reading is shown in FIG.
become that way. The magnitude of the pulse applied to the bit line is the same as in the first embodiment. The transistor 3 is supposed to be an n-channel, but in the case of a p-channel, it goes without saying that on and off are reversed. At this time, the potentials of word lines and bit lines not including the selected cell are kept at 0V. At the time of writing, the inversion voltage is applied only to the selected cell, and half of the voltage is applied to the other cells or 0V remains.
Since the polarization inversion does not occur at a voltage half the voltage required for the polarization inversion, only the polarization of the selected cell can be inverted.

In the case of reading, as in the case of the first embodiment, a pulse that does not cause polarization reversal may be applied to the bit line 15 to detect the conduction state of the memory cell transistor 3.

15 to 18 show the structures of the memory cells actually manufactured. The forming method, forming conditions, materials, etc. are basically the same as those in the first embodiment.

[0029]

According to the present invention, a non-destructive readable ferroelectric memory cell can be realized by utilizing a normal MOSFET according to the prior art. Further, the inversion voltage can be reduced only by setting the film thickness and material of the ferroelectric capacitor and the normal capacitor. Especially as a paraelectric material, Si
O ₂ dielectric constant is larger than the SiN, if you choose Ta ₂ O ₅ or the like, the intensity difference of the dielectric constant of the dielectric is reduced, and a double structure of a ferroelectric thin film and SiO ₂ gate in MFSFET type It has a feature that the inversion voltage can be easily reduced as compared with the conventional one. In addition, since the base electrode of the ferroelectric thin film can be freely selected, a film with good orientation can be obtained, and therefore there is no difficulty at the interface between the ferroelectric and the semiconductor such as MFSFET, and the structure is simple and stable. A non-destructive read non-volatile memory can be provided.

[Brief description of drawings]

FIG. 1 is an equivalent circuit diagram of a ferroelectric memory element according to the present invention.

FIG. 2 is a diagram showing a series circuit of a ferroelectric capacitor and a paraelectric capacitor.

FIG. 3 is a diagram showing characteristics of the ferroelectric capacitor in FIG.

FIG. 4 is a diagram showing Vf-Vw characteristics in the circuit of FIG.

5 is a voltage Vw between terminals 4 and 6 in FIG.
FIG. 6 is a diagram showing a ferroelectric capacitor voltage Vf characteristic.

FIG. 6 is a diagram showing PE hysteresis characteristics of a ferroelectric thin film.

FIG. 7 is a diagram showing an equivalent circuit of a memory cell configured by using the ferroelectric memory element according to the first embodiment.

FIG. 8 is a diagram showing pulses applied to a bit line and a word line at the time of writing and reading of the memory cell in the first embodiment.

FIG. 9 is a diagram showing a planar configuration of a memory cell according to the first embodiment.

FIG. 10 is a diagram showing a cross section of a portion indicated by alternate long and short dash line a in the plan view of FIG. 12;

FIG. 11 is a diagram showing a cross section of a portion indicated by alternate long and short dash line b in the plan view of FIG. 12;

FIG. 12 is a diagram showing a cross section of a portion indicated by alternate long and short dash line c in the plan view of FIG. 12;

FIG. 13 is a diagram showing an equivalent circuit of a memory cell configured by using the ferroelectric memory element according to the second embodiment.

FIG. 14 is a diagram showing pulses applied to a bit line and a word line at the time of writing / reading of a memory cell in the second embodiment.

FIG. 15 is a diagram showing a planar configuration of a memory cell according to a second embodiment.

16 is a diagram showing a cross section of a portion of a dashed-dotted line a in the plan view of FIG.

FIG. 17 is a view showing a cross section of a portion indicated by alternate long and short dash line b in the plan view of FIG. 18;

FIG. 18 is a diagram showing a cross section of a portion indicated by alternate long and short dash line c in the plan view of FIG. 18;

FIG. 19 is a diagram showing an equivalent circuit of a conventional capacitor-type ferroelectric memory cell.

FIG. 20 is a diagram showing a cross-sectional structure of a conventional MFSFET type ferroelectric memory.

FIG. 21 is a diagram showing a cross-sectional structure of a conventional MFSFET type ferroelectric memory having a double gate.

[Explanation of symbols]

1 Ferroelectric Capacitor 2 Paraelectric Capacitor 3 MOSFET 4, 5, 6 Terminal 7 Silicon Semiconductor Substrate 8, 9 Source / Drain Impurity Diffusion Region 10 Paraelectric Thin Film 11 Lower Electrode 12 Ferroelectric Thin Film 13 Upper Electrode 14 Cell Selection Switching transistor 15 word line 16 bit line 17,18 polysilicon gate electrode 19,20 gate oxide film 21,22,23,24 n ⁺ impurity diffusion region 25 paraelectric capacitor underlying Pt electrode 26 paraelectric Ta ₂ O ₅ Thin film 27 Common for ferroelectric capacitors and paraelectric capacitors
Pt electrode 28 Ferroelectric PZT thin film 29 Upper Pt electrode of ferroelectric capacitor 30 Silicon semiconductor substrate 31 Element isolation region 32 Interlayer insulating film 33, 34, 35 Contact 36 Al wiring

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/8247 29/788 29/792

Claims (3)

[Claims] 1. A ferroelectric capacitor having a ferroelectric thin film as a constituent element of an insulating film and a paraelectric capacitor having a paraelectric thin film as an insulating film are connected in series, and the ferroelectric capacitor and the The common electrode of the paraelectric capacitor is connected to the gate electrode of a transistor that stores information by changing the amount of current at a predetermined threshold, and the other electrode of the paraelectric capacitor that is not the common electrode is connected to the gate electrode of the transistor. A ferroelectric memory element characterized by being connected to a drain terminal. 2. The ferroelectric memory element according to claim 1, wherein a read transistor is added to the drain terminal. 3. The ferroelectric memory element according to claim 1, having a structure in which the ferroelectric capacitor and the paraelectric capacitor are interchanged.