JPH02198286A - Flicker reduction device - Google Patents

Abstract

PURPOSE:To reduce a flicker by forming an intermediate vertical signal by referring to the number of the horizontal periods between vertical synchronous signals in a field before the preceding field in an original video signal. CONSTITUTION:A vertical synchronous signal VS for a vertical synchronous signal input terminal 18 is supplied to the clear terminal of a 11-bit counter 19 and supplied to the clear terminal of a sub counter 20, and the signal VS is supplied to the load terminal of a latch circuit 21. A 4fH clock signal supplied to a clock signal input terminal 22 is supplied to the clock terminals of the counters 19 and 20 and supplied to the respective clock terminals of the circuit 21 and a latch circuit 23. The counter 19 counts the 4fH clock signal between the signals VS and supplies 10 bits obtained by removing the least bit to the circuit 21 in order to output the 1/2 of this counted number. Whenever the signal VS is supplied to the circuit 21, the circuit 21 latches a number equivalent to the 1/2 of the counted number of the counter 19. Thus, the flicker can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a flicker reduction device suitable for use in a digital video tape recorder that reproduces PAL or SHCAM color video signals.

[Summary of the invention]

The present invention relates to a flicker reduction device suitable for use in a digital video tape recorder that reproduces PAL or SECAM color video signals, and in a flicker reduction device that reduces surface flicker by doubling the field frequency. By forming an intermediate vertical synchronizing signal placed between the vertical synchronizing signals of the original video signal with reference to the number of horizontal periods between the vertical synchronizing signals two fields before the original video signal, the slow speed of the video tape recorder can be adjusted. Vertical jitter during special reproduction of stills and the like is improved so that reproduced images with well reduced flicker can be obtained.

[Conventional technology]

Generally, the PAL or SECAM color video signal is a 50-field system with a vertical frequency of 50Hz.
When a color video signal of the PAL system or SECAM system is reproduced on a large screen, there is an inconvenience that flicker occurs and the display becomes relatively difficult to play. Therefore, a method has been proposed in which the field frequency of this color video signal is doubled to reduce flicker. Fig. 3 shows a flicker reduction device previously proposed by the present applicant. It shows a video signal input terminal to which a color video signal is supplied, and an analog Y/C separation circuit (
2) and a synchronization separation circuit (3) which separates the synchronization signal. This analog Y/C separation circuit (2) separates the luminance signal Y into color difference signals R-Y and B-Y (here, R is a red signal and B is a blue signal), and the luminance signal Y is analog- After being converted into a digital signal by the digital conversion circuit (4), it is supplied to the digital-to-analog conversion circuit (7) through a system of a noise reduction circuit (5) and field memories (6Y) (6Y').

In this case, the read control signal M8 of the field memory (6Y) (6Y') is the write control signal M. The luminance signal output to the digital-to-analog conversion circuit (7) is set as a luminance signal with twice the field frequency, and the analog luminance signal 2Y with twice the field frequency is sent to the RGB conversion circuit (8). supply Further, the color difference signals R-Y and B-Y separated by the analog Y/C separation circuit (2) are sent to R-Y, B-Y, and R-Y via the analog switch (9).

Serial color difference data like B-Y... is digitized by an analog-to-digital conversion circuit (10), and sent to memory (6C) (6G') via a color difference noise reduction circuit (11). supply to. This memory (
6G) (6C') has a 4-bit configuration and stores 8-bit serial data in parallel in 4-bit units.

The output signals of the memories (6G) (6C') are input to the flicker reduction circuit (12) in 8 bits, and color difference signals 2 (R-Y) and 2 (2) with twice the field frequency are input.
This flicker reduction circuit (12
) is output to the digital-to-analog conversion circuit (7). For this reason, memory (6C) (6C')! 7) Read control signal MR is write control signal M
. The frequency shall be twice that of . The analog field frequency obtained on the output side of this digital-to-analog conversion circuit (7) is R
This RGB conversion circuit (8) is supplied to the GB conversion circuit (8).
), the red light 2R has twice the field frequency.

It is configured to output a green signal 2G and a green signal 2B.

The synchronization separation circuit (3) separates the vertical synchronization signal ■ and the horizontal synchronization signal H8, and converts this horizontal synchronization signal H8 into, for example, 28
It is supplied as a reference signal to an AFC circuit (13) that generates a MHz clock signal. The clock signal from this AFC circuit (13) is supplied to the flicker reduction circuit (12), and this clock signal is sent to the memory (6Y).
(6Y') (6C) (6C') are supplied to the digital-to-analog conversion circuit (7), respectively. Also, the synchronous separation circuit (
3), the vertical synchronizing signal (1) is supplied to the flicker reduction circuit (12). This flicker reduction circuit (12) includes an analog Y/C separation circuit (2), an analog switch (9), and an analog-digital conversion circuit (4) (1
0), noise reduction circuits (5) (11), and a deflection circuit (14) that controls the horizontal and vertical deflection of the color cathode ray tube.
) as if to control it.

The operation of this flicker reduction device is shown in Figure 4 A, B,
To explain using the image and scanning line three-dimensional model in Figures A and H, in the PAL or SECAM system, the vertical frequency is
As shown in Figures A and B, the l field (15) and the i+1 field (16) are scanned increcally, and the interval between the l field (15), the i+1 field (16), the i+2 field (17), etc. is 50 Hz. However, with a 50-field system like this one, there is a problem of noticeable flickering when used as a large screen, so the field frequency was doubled to 100Hz, as shown in Figure 5A and B.
This reduces screen flicker when a large screen is used as an LHS.

This fifth image obtained by this flicker reduction device
Vertical synchronization signal ■ of the l field (15) in the figure.

As shown in FIG. 6B, the vertical synchronizing signal interval of the PAL or SECAM standard television signal as shown in FIG. 6A is 312.58 (H is the horizontal period). To form the vertical synchronizing signal as shown in FIG. 6B, after the vertical synchronizing signal 2 as shown in FIG. 6A from the synchronization separation circuit (3) is input, ] When applying such a flicker reduction device to a video tape recorder and obtaining a normal playback screen,
As mentioned above, a playback screen with reduced flicker can be obtained, but during special playback, such as slow playback or still playback, the vertical synchronization signal obtained at the output side of the synchronization separation circuit (3) is shown in FIG. 7A. The vertical sync signal is now 313.5.
H, 315, 5H.

313.5H, 315, 5H..., and the vertical synchronization signal V of the flicker reduction circuit (12) at this time.

As shown in FIG. 7B, there is a problem in that vertical jitter occurs due to variations between the vertical synchronizing signals and the reproduced screen becomes difficult to view. Furthermore, in the case of a forward picture search and a backward picture search, FIGS. 8A and 9
As shown in Figure A, the distance between the vertical synchronizing signals of the vertical synchronizing signal (■) obtained at the output side of the synchronizing signal separation circuit (3) is 296H and 330H, and the flicker reduction circuit (12)
The interval between the vertical synchronizing signals (1) in FIG. 8B and FIG. 9B is even more variable, and the reproduced screen becomes even more difficult to see due to vertical jitter, which is disadvantageous.

In view of the above, an object of the present invention is to provide a flicker reduction device that can effectively reduce surface flicker even during special playback of a video tape recorder.

[Means to solve the problem]

The flicker reduction device of the present invention is, for example, as shown in FIG. 1, in a flicker reduction device that doubles the field frequency to reduce surface flicker. Vertical synchronization signal■ of this original video signal.

It is formed with reference to the number of horizontal periods between vertical synchronization signals two fields before.

(effect) According to the present invention, the vertical synchronization signal V of the original video signal.

Since the intermediate vertical synchronizing signal 8 is formed by referring to the number of horizontal periods between vertical synchronizing signals two fields before V-, this intermediate vertical synchronizing signal V- is Vertical synchronization signal that can be located in the middle between synchronization signals and has double the frequency ■Can reduce the variation in the interval between vertical synchronization signals in 7, and can reduce vertical jitter Special playback of video tape recorders Good flicker reduction can be achieved even at times.

〔Example〕

Hereinafter, one embodiment of the flicker reduction device of the present invention will be described with reference to FIGS. 1 and 2.

In this example, the flicker reduction circuit (12
) Intermediate vertical synchronization signal ■. The process is as shown in FIG. That is, in Figure 1,
(18) indicates a vertical synchronizing signal input terminal to which the vertical synchronizing signal ■, from the synchronizing signal separation circuit (3) is supplied, and 11 indicates the vertical synchronizing signal ■, supplied to this vertical synchronizing signal input terminal (18). It is supplied to the clear terminal of the bit counter (19) and also to the clear terminal of the sub-counter (20), and this vertical synchronizing signal (2) is supplied to the load terminal of the latch circuit (21). Further, (22) indicates a clock signal input terminal to which a clock signal of four times the horizontal frequency 4fH is supplied, and 4f is supplied to this clock signal input terminal (22).

The clock signal is supplied to each clock terminal of the counters (19) and (20), and also to each clock terminal of the latch circuits (21) and (23).

The counter (19) counts the 41H clock signal between the vertical synchronization signals V3 and supplies 10 bits excluding the minimum bit to the latch circuit (21) in order to output the minus number of this count. ing. Therefore, the latch circuit (21) receives the vertical synchronization signal ■.

Each time the counter (19) is supplied, the count value of the counter (19) is latched. The 10-bit output signal of this latch circuit (21) is supplied to the latch circuit (23), and the vertical synchronization signal ■3 from the vertical synchronization signal input terminal (18) is supplied to the load terminal of this latch circuit (23). . Therefore, this latch circuit (23) latches the number of latches of the latch circuit (21) one vertical period ago. Also, sub counter (2
0) counts the 4fM clock signal between the vertical synchronization signals 73 and supplies this count signal A to one input terminal of the comparator circuit (24). Further, the output signal B of the latch circuit (23) is supplied to the other input terminal of the comparison circuit (24). This comparison circuit (24) is designed to output an output signal when the count signal A of the sub-counter (20) matches the output signal B of this latch circuit (23). Intermediate vertical synchronization signal■8
In FIG. 1, during normal playback of the video tape recorder, the vertical synchronizing signal input terminal (18) is supplied with a constant signal every 312.5H as shown in FIG. The latch circuit (21) is supplied with the vertical synchronization signal V of the interval, and the latch circuit (21) calculates the count number 1250 of the counter (19) between the vertical synchronization signals of the previous field when the vertical synchronization signal V is input. 625, and the latch circuit (23) also latches the latch circuit (21).
) latches the number of latches 625 in the previous field. Therefore, the vertical synchronization signal ■ is supplied to the sub-counter (20) and cleared, and when the sub-counter (20) subsequently reaches 625, an output signal is obtained from the comparator circuit (24), which is sequentially The vertical synchronization signal ■ is repeated as shown in FIG. 6C.

A vertical synchronization signal vH is obtained during the interval. In this case, the latch circuit (
The number of latches latched in the sub-counter (23)
0) is the count number of the counter (19) between vertical synchronizing signals two fields before the vertical synchronizing signal being counted, and this intermediate vertical synchronizing signal ■. is formed based on the number of horizontal periods 312.5H between vertical synchronization signals two fields before.

By inserting the intermediate vertical synchronizing signal (1) as shown in FIG. 6C into the vertical synchronizing signal Vs of the original video signal as shown in FIG. 6A, vertical A synchronization signal is obtained, and flicker can be reduced as well as in the conventional method. Further, special playback of a video tape recorder, such as slow or still playback, will be explained with reference to FIG. At this time, the second
As shown in Figure A, the interval between vertical synchronization signals is 313.5H.

A vertical synchronizing signal (2) which fluctuates as 315.5H, 313, 5H, . . . is obtained. When this vertical synchronizing signal VS+ of FIG. 2A is input, the latch circuit (21)
As shown in FIG. 2C, the latch circuit (23) between the vertical synchronization signals of the field before the vertical synchronization signal V31 counted by the counter (19) as shown in FIG.
21) latches 631 which was latched between vertical synchronization signals of the previous field. Therefore, when the subsequent vertical synchronizing signal VSZ is input, the latch circuit (21) latches 631 and the latch circuit (2) as shown in FIG. 2B.
3) latches 627 as shown in Figure 2C, so
After this vertical synchronization signal VSt is input, when the sub counter (20) counts 627, it outputs the intermediate vertical synchronization signal VMI. When the next vertical synchronization signal VSI comes, the latch circuit (21) latches 627. At the same time, the latch circuit (23) latches 631, so when the sub-counter (20) counts 631, it outputs the intermediate vertical synchronizing signal V□, and this is sequentially repeated to generate the intermediate vertical synchronizing signal as shown in the second figure. v4 is obtained, and an intermediate vertical signal is formed by referring to the vertical synchronization signal vs of the original video signal as shown in FIG. Add the synchronization signal ■ and the second
A vertical synchronizing signal of twice the frequency used in the flicker reduction circuit (12) as shown in the figure is obtained. Since the vertical synchronizing signal shown in FIG. 2E has almost no variation in vertical interval, vertical jitter is small, and flicker can be effectively reduced even during slow or still reproduction.

Also, according to this example, when performing a forward picture search, the eighth
As shown in FIG. 9C, when a pattern search is performed between the vertical synchronizing signals, as shown in FIG.

It goes without saying that the present invention is not limited to the above-described embodiments, and that various other configurations can be taken without departing from the gist of the present invention.

(Effects of the Invention) According to the present invention, vertical jitter during special playback such as slow playback and still playback of a video tape recorder is improved, and there is an advantage that a playback image with well reduced flicker can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an example of the main parts of the flicker reduction device of the present invention, FIGS. 2, 6, 7, 8, and 9.
The figures are diagrams for explaining the present invention, FIG. 3 is a configuration diagram showing an example of a flicker reduction device, and FIGS. 4 and 5 are diagrams for explaining FIG. 3. (1) is a video signal input terminal, (3) is a synchronous separation circuit, (
6Y) (6Y'), (6C) (6G') is memory, (12) is flicker reduction circuit, (18) is vertical synchronization signal input terminal, (19) is counter, (20)
is a sub-counter, (21) and (23) are latch circuits, (24) is a comparison circuit, and (25) is an output terminal.

Claims (1)

[Claims] In a flicker reduction device that doubles the field frequency to reduce surface flicker, an intermediate vertical synchronization signal placed between the vertical synchronization signals of the original video signal is placed two fields before the vertical synchronization signal of the original video signal. A flicker reduction device characterized in that the flicker reduction device is formed by referring to the number of horizontal periods between vertical synchronization signals.