JPH0219709B2 - - Google Patents

Description

[Detailed Description of the Invention] (Field of Application) The present invention relates to a motor servo system in a VTR, etc., where speed deviations due to variations between sets and changes in temperature and humidity are particularly problematic, and the use of an IC in the control section is a problem. The present invention relates to a motor speed steady-state error correction device for mass-produced products, which is a prerequisite.

(Background) An example of a conventional general digital speed control system will be described below with reference to FIG. In FIG. 1, 1 is a preset value generator, 2 is a preset circuit, 3 is a counter, 4 is a latch, 5 is a digital-to-analog converter, 6 is a volume, 7 is a motor drive circuit, and 8 is a motor. Further, 9 is a rotation detector, 10 is a pulse generator that generates a preset pulse 12 and a latch pulse 13,
11 is a clock pulse generator, 14 is a clock pulse, and 15 is a rotation detection signal.

The operation of this conventional example will be explained using the main waveform diagram shown in FIG. First, the rotational phase of the motor 8 is detected by the rotation detector 9, and at a certain phase (for example, a rising edge) of the detected signal 15, the pulse generator 10 converts the latch pulse 13 and preset pulse 12 into the clock pulse train 14. Occurs based on In the example of FIG. 2, from the rising edge of signal 15, in synchronization with the second clock pulse 14,
Latch pulse 13 whose pulse width is one clock period
is generated, and from this rising edge, a preset pulse 12 having a pulse width of one clock period is generated in synchronization with the fourth clock pulse 14.

The counting counter 3 stops from time A to B in FIG. 2, and counts the clock train 14 after time B. The pattern of changes in this count value is shown in FIG. 2, 16. That is, at a specific edge (for example, a rising edge) of the motor rotation detection signal 15, the counter 3 is first stopped and the counted value is held. next,
Latch pulse 1 generated from pulse generator 10
During the high period of 3, the count value of count counter 3 of FIG. 1 is transferred to latch 4 and held there. Based on the bit information of latch 4, digital-to-analog converter 5 outputs an analog conversion value. This output is applied to the motor drive circuit 7.

After this latching operation is completed, the pulse generator 1
While the preset pulse 12 output from 0 is high, the preset circuit 2 causes the counting counter 3 to
is preset. Thereafter, the counting counter 3 starts counting the clock 14 (after time B) and continues counting until the next rising edge of the motor rotation detection signal 15 is detected.

As the period of the rotation detection signal 15 of the motor 8 becomes longer, the operation time of the counting counter 3 becomes longer, and the bit information latched in the latch 4 also becomes a larger value. The motor 8 is accelerated because it is driven by a large voltage obtained by digital-to-analog conversion. Conversely, when the period of the signal 15 becomes shorter, the motor 8
is slowed down. That is, the motor 8 is subjected to negative feedback control and controlled several times so that it rotates at a constant speed.

In this system, the rotation speed of the motor 8 varies from device to device due to the amount of DC offset between each element. For this reason, an adjustment volume 6 is generally provided to cancel the offset amount and rotate at a predetermined speed.

However, conventionally, during mass production of home VCRs, etc., it has taken a considerable amount of time to adjust the offset using the adjustment volume 6.

For this reason, the conventional device has the disadvantage that it takes a long time to adjust the volume and increases labor costs. In addition to this, changes in characteristics due to changes in temperature and humidity of each element, etc., make design difficult and require a great deal of countermeasures.

(Purpose) The purpose of the present invention is to eliminate the volume that was conventionally provided for adjusting the motor rotation speed due to the offset of each element of the motor servo system, reduce adjustment time and labor costs, and adjust the temperature, humidity, etc. It is an object of the present invention to provide a self-correction system, that is, a steady-state speed error correction device for a motor, which automatically cancels the effects of changes and the like.

(Summary) The present invention is characterized by a monitoring counter that detects a speed deviation, a means for holding the count value of the counter and outputting an up or down signal, and an up-down signal that can be switched between up and down by the output of the means. A counter, a counting counter that uses each bit information of the up-down counter as a preset value, and means for converting the count value of the counting counter from D to A and applying it to the motor, and detects the rotation of the motor. The up-down pulse generated from the output of the detector is used as the clock for the up-down counter.

(Embodiment) An embodiment of the present invention will be described below with reference to the block diagram of FIG. 3 and the main waveform diagram of FIG. 4. In FIG. 3, 2' is a preset circuit, 20 is a monitoring counter, 21 is a latch, and 22 is an up-down counter. Further, 25 and 26 are a clock signal of the up/down counter 22 and an up/down switching signal. Furthermore, 23 and 24 in FIG.
The bit information of the monitoring counter 20 and counting counter 3 is illustrated in analog form, respectively.

The operation of this embodiment will be explained in detail below.

First, the frequency of the clock pulse 14 output from the clock pulse generator 11 is set to _SC , and the motor 8
Let _FG be the frequency of the rotation detection signal of The number of clocks counted during one period of 15 must be M= _SC / _FG (M is a constant value). In other words, if the rotation of the motor 8 can be controlled so that the clock number M is constant, the motor 8 can be controlled to operate at a desired rotation speed. This clock number M is a target value, and in this embodiment, the latch and comparator 21
is set in the latch and comparator 21 as a reference value.

Normally, the value L held in the latch 4 is converted into an analog quantity by a digital-to-analog converter 5. This converted output V is applied to the motor drive circuit 7. At this time, the frequency of the motor rotation detection signal is
Let _LM be the preset value of the counter 3 so that FG is obtained (here, L is the count value of the counter 3 for making the motor 8 reach a predetermined rotation period).

This preset value is actually determined by taking into consideration the time for stopping the counting counter 3 (time T in FIG. 4) in order to ensure latch and preset operations. That is, the value corresponding to the time T is decreased.

The above operation is similar to that of the conventional device.

In this embodiment, the preset value is not set to a fixed value as in the conventional device, but is variably controlled using bit information of the up-down counter 22.
This makes it possible to automatically detect and correct motor speed deviations caused by DC offset mismatch between components, temperature changes, and the like.

The operation of the characteristic parts of this embodiment will be explained in detail below. In this embodiment, the up-down switching signal 26 of the up-down counter 22 is the comparison result between the value C obtained by latching the count value of the monitoring counter 20 in the latch 21 and the target value, that is, M= _SC / _FG . That is, when the value latched by the monitoring counter 20 is larger than the above-mentioned M (C>M), the switching signal 26
switches the up-down counter 22 to up-count. On the other hand, when the C is smaller than the M (C<M), the up/down counter 22 is switched to down counting.

A specific example will be described in which the value C is compared with the predetermined number M using the latch 21. Latch 21
is 4 bits, the predetermined number M is 0111
and 1000. Then, if the count value C of the monitoring counter 20 is 0111 or less, the latch 2
“0” will be set in the MSB of 1, and on the other hand,
If it is 1000 or more, "1" will be set in the MSB. In other words, if C<M, the latch 21
“0” is set in the MSB, and if C>M, “1” is set in the MSB. If this MSB is used as the up-down switching signal 26, the latch 21 determines the magnitude of C and M, and the latch 21 outputs the up-down switching signal 26.
can occur.

Now, the motor rotation detection signal 15 with a predetermined frequency
(For signal a shown as a solid line in Fig. 4),
Motor rotation detection signal 15 whose cycle has become short due to speed deviation (signal b indicated by a broken line in Fig. 4)
When is detected, C<M, and the latch 21 outputs a switching signal 26 of "0" to switch to down counting. Therefore, the up-down counter 22 counts the up-down clocks 25 generated at the edges of the rotation detection signal 15, and decrements the counted value by one.

Each bit of information in the up-down counter 22 is initialized to match the preset value LM described above before operation, and the counter 3 initially counts this bit output as the preset value. If the analog value of the count value of the counter 3 at this time is represented by 24d in Fig. 4, when the up-down counter 22 performs a down-counting operation as under this condition, its output is set to the preset value. The counter 3 has a preset value LM
(24f in Figure 4) to start counting from a smaller preset value (24g in Figure 4) (24d in Figure 4) to an operation to start counting from a smaller preset value (24g in Figure 4). Shift to e).

Therefore, the value latched by the latch pulse 13 becomes smaller, and the voltage applied to the motor drive circuit 7 also becomes smaller. Therefore, while the ratio ΔV/ΔU at which the change ΔU in the period U of the motor rotation detection signal 15 causes the change ΔV in the analog conversion amount V is kept constant, speed control is performed at a low DC level at which the motor is decelerated.

Conversely, if the rotation is slower than the predetermined cycle, the analog display amount 24 of the counter 3 will be at a level higher than d, and the motor will be controlled in the direction of acceleration. Therefore, as long as the speed deviation exists, the preset value continues to be corrected. For this reason, the motor rotation detection signal is always controlled to have a predetermined value, that is, a period of 15a in FIG. 4.

In this embodiment, the clock pulse 25 applied to the up-down counter 22 is the motor rotation detection signal 1.
However, the clock pulses 25 are thinned out by providing a frequency divider to correct errors in the rotational speed of the motor 8. It is also possible to do it slowly. A similar operation can also be performed by connecting a dummy bit below the up-down counter 22.

Further, in the above embodiment, the latch 21 compares the count value C of the monitoring counter 20 with the predetermined number M, but a comparator is provided after the latch 21, and the reference value of the comparator is set as the reference value of the predetermined number M. Of course, the count value C and the value M may be compared in magnitude, and the up/down switching signal 26 may be output based on the comparison result.

Next, another embodiment of the present invention will be explained with reference to the block diagram of FIG. 5 and the time chart of FIG. 6. 27 in FIG. 5 receives the output 28 of the latch 21, compares this value C with predetermined values x, y, and determines x
This gate circuit transmits the signal 25 to the up-down counter 22 under the condition <c<y.

Here, the predetermined values x and y are indicators that the motor rotation speed has reached a certain level. That is,
In the first embodiment, since the self-correction function, which is a feature of the present invention, is operated from the time the motor is started, the up-down counter 22 once reaches the maximum value when the motor is started. (Of course, the up-down counter 22 is provided with a limiter that stops the clock at the maximum and minimum values.)
Thereafter, after the rotational speed increases and becomes faster than the desired value, it starts counting down.

On the other hand, as in this embodiment, the self-correction function is activated after the speed approaches the predetermined speed to some extent.
That is, when a clock is input to the up-down counter 22, the up-down counter 22 is drawn to the desired value without reaching the maximum value. Therefore, the rise time can be shortened.

FIG. 6 is used for concrete explanation of this embodiment. In FIG. 6, 30 and 31 indicate time points, 29 indicates time, and a' and b' indicate waveforms.

If the frequencies corresponding to time points 30 and 31 are the aforementioned y and x, then the up-down counter 22
A clock 25 is applied to.

(Effect) According to the present invention, the temperature and the distance between parts are automatically controlled.
Since speed deviations caused by DC offset variations etc. can be absorbed, the speed setting volume conventionally provided to absorb this speed deviation can be omitted. Therefore, it is effective to reduce labor costs for adjustment and to prevent performance deterioration due to the influence of temperature changes.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a conventional device, Fig. 2 is a waveform diagram of its essential parts, Fig. 3 is a block diagram of an embodiment of the present invention, Fig. 4 is a waveform diagram of its essential parts, and Fig. 5 is a diagram of its essential parts. FIG. 6 is a block diagram of another embodiment of the present invention, and FIG. 6 is a waveform diagram of its essential parts. 1... Preset value generator, 2... Preset circuit, 2'... Preset circuit, 3... Counter, 4, 21... Latch, 5... D-A converter, 7... Motor drive circuit, 8...Motor, 9...
...Rotation detector, 10...Pulse generator, 11...
Clock pulse generator, 20...monitoring counter,
22... Up-down counter, 27... Gate circuit.

Claims (1)

[Claims] 1. A rotation detector 9 that detects the rotation speed of the motor;
a clock pulse generator 11; a counting counter 3 to which a preset value is set and which counts clock pulses corresponding to the rotation period of the motor; means 4 for latching the counted value of the counting counter; and a pulse for actuating the preset and latch. a pulse generator 1 that generates synchronously with the output of the rotation detector;
0, a D/A converter 5 that converts the latched value into an analog signal, and a motor drive circuit 7 that drives the motor with the converted analog signal, and drives the motor at a target rotation speed. In a motor speed steady error correction device that controls rotation, a monitoring counter 20 measures the rotation period of the motor, and a count value C of the monitoring counter is compared with a preset target value M, and an up signal or means 21 for outputting a down signal, (L-M) (where L is a count value of the counter for reaching a predetermined rotation period of the motor) is preset, and the pulse generator detects the rotation. an up-down counter 22 that counts up-down pulses generated in synchronization with the output of the up-down counter and is controlled by the up or down signal; 1. A motor speed steady-state error correcting device, characterized in that a DC offset of a control system of the motor is automatically corrected by setting the preset value to a preset value. 2. The motor speed steady-state error correction device according to claim 1, wherein the up-down pulses generated by the pulse generator are thinned out and applied to the up-down counter. . 3. The invention as claimed in claim 1, further comprising a gate circuit that allows application of the up-down pulse to the up-down counter when the bit output of the monitoring counter is within a predetermined value range. The motor speed steady-state error correction device according to item 2.