JPS60211501A - Device for correcting steady-state speed error - Google Patents

Abstract

PURPOSE:To attain quick locking to a steady-state by decreasing the sensitivity of a DC offset means so as to cause an integration effect thereby suppressing overshoot at motor start. CONSTITUTION:An up-down counter 19 is set to the up-count mode when the period of an FG signal (a) exceeds a reference period, and set to the downcount mode when the period is below the reference speed, and a speed control signal is obtained based on the count value. A frequency divider circuit 24 is an interleaving element of a clock provided to reduce the clock count speed of the counter 19, frequency-divides a clock pulse at each leading of the signal (a) subjected to frequency division while interleaving the pulse, and the counter 19 counts the clock pulse subjected to frequency division. Thus, the entire system is stabilized, the leading characteristic is improved and the overshoot is eliminated. The interleaving element 24 is handled as a digital integration element.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a steady-state speed error correcting device for a motor, and more particularly to a steady-state speed error correcting device for correcting a DC offset in a motor control system.

[Background of the invention]

In a magnetic recording/reproducing device, it is necessary to keep the speed of the magnetic tape constant, and for this purpose, a speed control mechanism is provided to keep the rotational speed of the capstan motor constant. However, in conventional speed control mechanisms, the offset voltage of each element affects the speed control operation,
There was a drawback that the rotational speed of the capstan motor was maintained at a deviation from a desired value.

FIG. 1 is a block diagram showing an example of a conventional steady speed error correction device that solves such problems, in which 1 is a motor;
2 is a frequency generator, 3 is a pulse generator, 4 is a counter,
5 is a latch circuit, 6-digit digital adder, 7 is a reference preset value generator, 8 is a preset circuit, 9 is a counter, 1
0 is a latch circuit, 11 is a digital-analog converter, 1
2 is an adder, 13 is a phase control circuit, and 14 is an amplifier.

In the figure, when the motor 1 is rotating, a rotation signal α (hereinafter referred to as the FG multiplied signal) with a frequency corresponding to the rotation speed of the motor 1 is obtained from the frequency generator 2, and this FG signal α is a pulse generator. is supplied to the container 6. The pulse generator 3 generates a clock pulse C having a constant repetition frequency, a latch pulse h synchronized with the rise of this FG signal α, and a preset pulse d.

The counter 9 counts each preset pulse J (that is, F
Each time the G signal α rises, it is preset to a preset value held by the preset circuit 8, and clock pulses c'lz are counted from this preset value. The count value of the counter 9 is latched by the latch circuit 10 by the latch pulse b, and the latched count value is converted into an analog value by a digital-to-analog converter (hereinafter referred to as a D/A converter) 11. The analog value from the D/A converter 10, that is, the speed control signal, is added to the phase control signal from the phase control circuit 13 in the adder 12, and then added to the phase control signal from the phase control circuit 13.
The signal is amplified and supplied to the motor 1.

The count value of the counter 9 latched by the latch circuit 10 represents the period of the FG signal α, and the D/A converter 11 determines whether this period is a predetermined value when the motor 1 rotates at a desired steady speed. The period below C is called the reference period)To
Female speed control signal? As the count value from the latch circuit 10 is generated, all the analog values are generated. This causes the motor 1 to rotate at a predetermined steady speed.

By the way, if only such an operation is performed, an offset voltage will be generated in the D/A converter 11 etc., so the speed control signal supplied to the motor 1 will not be offset by this amount. The rotation will deviate from the steady speed by this amount.

For this purpose, a counter 4, a latch circuit 5, a digital adder 6. A reference preset value generator 7 is provided, and the preset value of the counter 9 is fully adjusted by the preset circuit 8, thereby eliminating the influence of the offset voltage mentioned above. I'm trying to remove it.

That is, the counter 4 is supplied with the clock pulse C and the preset pulse d, is preset to a constant predetermined value at the same time as the counter 9, and is also supplied with the clock pulse cf.
Count. Then, when the counter 4 counts one period of the FG signal α, the count value at this time is latched in the latch circuit 5. This latched count value is supplied to a digital adder 6, which combines this count value with the reference period T. The difference between the count value (hereinafter referred to as reference count value) required for Become.

Here, the reference preset value is the preset value of the counter 9 when the above offset voltage does not occur. Further, the reference count value is the count value of the counter 4 for one cycle of the FG signal α when the motor rotates at a desired steady speed and the cycle of the FG signal α is the reference cycle To.

Therefore, if the above-mentioned offset voltage occurs and the motor is rotating at a deviation from the desired steady speed, the latch circuit 5
The count value of the counter 4 that is latched differs from the reference count value by an amount corresponding to the deviation amount of the rotational speed of the motor 1.

The digital adder adds or subtracts the reference preset value by the difference between the count value latched by the latch circuit 5 and the reference count value, and sets the preset value of the counter 9 to a value that can completely cancel out the offset voltage.

For example, the count value latched by the latch circuit 5 when the FG signal α is reference/standard synchronization TO, that is, the reference count value? "'o, o, i, o" and motor 1
The count value latched by the latch circuit 5 when is at a constant rotational speed is larger than the reference count value; 1.
If 0゜1.0'', then the difference between these degrees is ゜1,0,0゜0
” is added to the reference preset value and becomes the preset value of the counter 9.

FIG. 2 schematically shows the entire offset voltage correction operation, with the horizontal axis representing the period of the FG signal α and the vertical axis representing the period of the FG signal α.
The output level of the /A converter 11 is measured, and the actual mA and the dashed line B represent the level changes when the count value f of the counter 9 is converted into an analog value by the D/A converter 11, respectively.

Now, when the preset value of the counter 9 is zero, the output level obtained by directly supplying the count value of the counter 9 to the D/A converter 11 is as shown by the solid line A, corresponding to the period T of the FG signal α. The period of the FG signal α is the reference period T. In this case, the output level of the D/A converter 11 is assumed to be the level VP for point P.

Under such conditions, if an offset voltage ΔV is generated in the D/A converter 11 etc., and therefore the rotational speed of the motor 1 is lower than the desired steady speed, in this case, the latch circuit 10 The count value of the counter 9 latched at is naturally larger than the reference count value, and therefore,
The output level of the D/A converter 11 becomes the level VQ at point Q, which is higher than point P by offset voltage ΔV. The period of the FG signal α at this time is T, (>To).

At the same time, the counter 4, latch circuit 5, and digital adder 6 increase the preset value of the counter 9 by an amount corresponding to the difference between these periods TI m 10, that is, by the amount corresponding to the offset voltage ΔV. The change in analog value corresponding to the count value of counter 9 is
It is shifted from the solid line A to the dashed-dotted line B.

Therefore, if the period of the FG signal α is 11, the output level of the D/A converter 11 will be higher than the level at point R, that is, the level VQ at point Q, by ΔV,
As a result, the rotational speed of the motor 1 increases, and the period T of the pG signal α decreases toward the point S.

Furthermore, when the offset voltage ΔV has a polarity opposite to that described above, the preset value of the counter 9 is similarly decreased to reduce the rotational speed of the motor 1.

In this way, the period of the FG signal α becomes the reference period T. The rotation of the motor 1 is controlled so that the desired steady speed is achieved, and the offset of the rotational speed is minimized.

Note that when the motor 1 is started, the phase side is 8.

The night circuit 13 is not operating and only outputs a constant voltage.

By the way, since such a steady speed error correction device does not include an integral element, when the motor 1 is started, the counter 4. There is a drawback that an overshoot occurs depending on the sensitivity of the DC offset removing means such as the digital adder 6, and the motor 1 rotates abnormally, prolonging the transition period to the steady speed state.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a steady speed error correction device that eliminates the drawbacks of the prior art described above, completely suppresses overshoot at the time of starting a motor, and enables rapid retraction to a steady speed state.

[Summary of the invention]

In order to achieve this object, the present invention is characterized in that the sensitivity of the DC offset removing means is reduced to produce an integral effect, thereby making it possible to suppress overshoot.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a block diagram showing an embodiment of the steady speed error correction device according to the present invention, in which 1 is a motor, 15 is an FG signal detector, 16 is a counter, 17 is a clock pulse generator, and 18 is a latch circuit. , 19 is an up/down counter,
20 is a counter, 21 is a latch circuit, 22 is a D/A converter, 23 is a motor drive circuit, and 24 is a frequency dividing circuit.

FIG. 4 is a waveform diagram showing main signals in FIG. 3, and signals corresponding to those in FIG. 3 are given the same symbols. In addition,
In FIG. 4, the count values of counters 1 (S, 20) in FIG. 3 are shown in analog form.

In FIGS. 3 and 4, an FG signal α from a frequency generator (not shown) is supplied to an FG signal detector 15, and a latch pulse h1 and a preset pulse d are formed at the rising edge of the FG signal α.

The counter 16 is preset every preset pulse d, counts all the clock pulses from the clock pulse generator 17, and the counting period of the counter 16 is equal to the reference period T mentioned above. The reference count value is set so that the most significant bit of the count value of the counter 16 is inverted at the same time as the total value is exceeded. For example, if the counter 16 has a 4-bit configuration, after being preset, the counter 16 will be 'o, o, o, o', '1, 0, 0°0', 0,
1,0,0. ",...", and when the count value becomes "1, 1, 1.0" and the next clock pulse C is supplied, the count value becomes "0, 0, 0...".
1” and the most significant bit is reversed from 0” to ’1”.
From then on, the most significant bit of the count value is held at 1''.In this case, after the counter 16 is preset, the count value is 1°1.1.0'' and 0,0,0.
．． 1'' is set to be the reference period To.In other words, the up-count period of the counter 16 has passed the reference period Tok, and the first supply is 0.
．． 11.

The repetition frequency of the clock pulse C is set according to the bit configuration of the counter 16 so that the most significant bit of the count value of the counter 16 is inverted from 0" to "1" by the clock pulse C.

The count value n1 of the counter 16 is latched by the latch circuit 18 by the latch pulse b. Therefore, the most significant bit of the count value latched by the latch circuit 18 is "0" when the FG multiplied signal period is less than the reference period 7 degrees, and is "1" when it exceeds the reference period 76.

The up/down counter 19 operates when the most significant bit of the count value latched by the latch circuit 18 is 1'' (that is, when the period of the FG signal α exceeds the reference period Tok)
, is set to up-count mode, and conversely, when the most significant bit of the count value is 0'' (that is, when the FG multiplied signal period is less than or equal to the reference period To), it is set to down-count mode. According to the set counting mode, the up/down counters 19, 12, . . . count all the clock pulses formed from the rising edge of the FG signal α.

The count value of this up/down counter 19 is used as a preset value of the counter 20.

That is, the counter 20 is preset to the current count value of the up/down counter 19 by the preset pulse d from the FG signal detector 15, and counts up the clock pulse C&- from the clock pulse generator 17. The count value n of the counter 20 is latched by the latch circuit 21 by the latch pulse b, and the latched count value is converted by the Dμ converter 22 to obtain a speed control signal. This speed control signal is supplied to the motor drive circuit 23, and the speed of the motor 1 is controlled.

By the way, when designing the circuit, it is assumed that no offset voltage occurs in the output voltage of the D/A converter 22, etc.
The preset value of counter 20 is set to generate a speed control signal that causes the motor to rotate at a desired steady speed. This preset value is called fNB. In this case, the count value of the counter 20 latched by the latch circuit 21 is the count value p, the output voltage obtained by conversion by the D/A converter 22 is V, and the motor 1 is at the desired steady The value is such that it rotates at a speed, and the period of the FO signal α is the reference period T. be equivalent to.

However, if an offset voltage exists in the output voltage of the D/A converter 22, the motor 1 will be rotating at a speed different from this desired steady speed.

Therefore, if the motor 1 is now rotating at a speed slower than the desired steady speed, the period of the FG signal α is (
ro+ΔT) (where Δr>o), the count value latched by the latch circuit 21 is large, and the output voltage of the D/A converter 22 is (V1+ΔV). That is, the steady speed error correction device is locked in this state.

At this time, the most significant bit of the count value latched by the latch circuit 18 is 1'', so the up/down counter 19 is set to up count mode, and the FG
A signal detector 15 counts clock pulses formed from the rising edge of the pa signal a.

Here, if this clock pulse is formed at every rising edge of the FG signal α, the up/down counter 19 continues to count up every period of the FG signal α, and at the same time, the preset value of the counter 20 is α
Increases by 1 every cycle. Therefore, counter 20
The count value gradually shifts by 1 every count period from the change of one line. Along with this, the count value latched by the latch circuit 21 increases and the D/A converter 2
The output voltage of motor 2 increases, and the rotational speed of motor 1 increases.

As a result, the period of the FG signal α decreases, so the count value latched by the latch timing of the latch circuit 21 tends to become smaller, but since the preset value of the counter 20 is increasing sequentially, The rotational speed of the motor 1 increases and the period of the FG signal α continues to decrease.

, 15.

The preset value is NA), and the period of the FG signal a is approximately the reference period T. Then, the output voltage of the D/A converter 22 is V, which is 10ΔV. The count characteristic of the counter 20 at this time is shifted upward from the straight line A' to the apex line B', and the motor 1 has a cycle of FG reliability α of T. V1 + ΔV, which offsets the DC offset ΔV, so that
It rotates at an operating point.

In the above control, the DC offset is in the opposite direction, the clamp, V,
The same process is performed even if the signal occurs in the direction of −ΔV, and the motor 1 always has the period of the FG signal α equal to the reference period T. It rotates while being locked in this state.

When this system is conveniently approximated using linear elements, it is represented by the block diagram shown in FIG. In the figure, 25 is an adder, 26 voltage amplification elements, 27 is a motor drive element,
2B is a motor, a 29-digit adder, and 30 a self-correction element.

The transfer function pA of the voltage amplification element 26, hereinafter, the transfer function of the motor drive element 27, the motor 28, and the self-correcting 1K element 30 are respectively approximated as "JS, j-f-TS," and 16 degrees. The relationship between the output ω of the system and the disturbance ΔV is expressed as follows.

Tonashi, the imaging coefficient ζ is When AD>1, ζ is approximately determined by T.

By increasing Ti, ζ also increases and the system becomes non-oscillatory. Here, T is the period of the clock pulse of the clock pulse down counter 9 in FIG. 3, and increasing Ti corresponds to making this period thicker, that is, making the frequency of this clock pulse coarser. Physically speaking, if the clock count speed of the up-down counter 9 is made too fast, the trapezoidal wave characteristic shown in FIG.

In FIG. 3, the frequency divider circuit 24 is a clock thinning element provided to reduce the clock count speed of the up/down counter 19, and is a clock thinning element provided to reduce the clock count speed of the up/down counter 19.
The clock pulses formed at each rising edge of the FG signal α are thinned out and frequency-divided, and the up-down counter 19 counts the frequency-divided clock pulses. For this,
The entire system is stabilized, the rise characteristics are improved, and overshoot is eliminated. This thinning element 24 may be an up/down counter or the like, and can be treated as a digital integral element.

FIG. 6 is a block diagram showing another embodiment of the steady-state speed error correction device according to the present invention, in which 31 is a logic circuit, 32 is a switch circuit, and 33 is an input terminal. are given the same sign.

Further, FIG. 7 is a waveform diagram showing the signals of each part in FIG. 6, where υ is the rotational speed of the motor, and the symbols corresponding to those in FIG. 6 are given.

In FIGS. 6 and 7, when the motor 1 is stopped, the motor stop signal e supplied from the input terminal 33 is at "H" (high level).

When the motor 1 is started at time to, the motor stop signal ε becomes L'' (low level), and the logic circuit 31 is reset at the falling edge of the motor stop signal ε.For this reason, the output of the logic circuit 31 becomes L''. , the switch circuit 32 closes to the contact α side.Moreover, the motor 1 rapidly accelerates, and the rotation speed V rapidly increases.The frequency divider 24 detects the rise of the FG signal α from the FG signal detection circuit 15. A pulse per edge is provided,
The pulse frequency divided by this total frequency division ratio is sent to the switch circuit 32.
A pulse frequency-divided by the frequency division ratio is output to the contact α of the switch circuit 32. In addition, here, Dl
>n. Therefore, the up/down counter 19
A coarse pulse frequency-divided by this division ratio D1 is supplied as a clock pulse.

The rotation speed V of the motor 1 is a desired steady speed V. When the period is below, the period of the FG signal α is the reference period T. Since it is as follows, the most significant bit of the count value latched by the latch circuit 18 is '0'', and this is outputted from the latch circuit 18 as 'H'.

At time t, the rotation speed V of the motor 1 is a desired steady speed ν.

When the count value exceeds 1, the most significant pit of the count value latched by the latch circuit 18 becomes ``°1'', its output f becomes L'', and the up/down counter 19 enters the down count mode, but other states change. Shina XA. For this purpose, motor 1 is decelerated.

At time t, the rotation speed V of the motor 1 is a desired steady speed ν.

Then, the output f of the latch circuit 18 becomes 6H" again, and the up/down counter 19 becomes the up-count mode. At the same time, the logic circuit 31 is triggered by the rising edge of the output f, and its output becomes 6H". The switch circuit 32 is then switched to the contact side. Therefore, the up/down counter 19 is supplied with a dense pulse whose frequency is divided by the frequency division ratio by 20 degrees from the frequency divider 24 as the clock pulse l.

As described above, the up/down counter 19c reaches the time t.

Since coarse clock pulses yk are counted between -62 and the system smoothly approaches a stable state, from time t onward, fine clock pulses yk are counted and speed corrections are frequently performed. Therefore, the start-up characteristic when the motor starts up becomes faster, and fine speed correction is performed during steady state.

□ [Effects of the Invention] As explained above, according to the present invention, when starting the motor,
This technology can significantly reduce vibration and overshoot in the start-up characteristics of the system, and quickly bring the motor to the desired steady speed state. A steady state speed error correction device can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional steady-state speed error correction device, FIG. 2 is a schematic diagram showing the offset voltage correction operation of FIG. 1, and FIG. 3 is a block diagram showing an example of a conventional steady-state speed error correction device. A block diagram showing one embodiment, FIG. 4 is a waveform diagram showing the main signal system in FIG. 3, FIG. 5 is a block diagram showing the system in FIG. 3 approximated by linear elements, and FIG. Block diagram showing another embodiment of the steady speed error correction device according to the invention, No. 7
The figure is a waveform diagram showing signals at various parts in FIG. 6. 1...Motor 15...FG signal detector 16...
Counter 17...Clock pulse generator 18...Latch circuit 19...Up/down counter 20...Counter 21...Latch circuit 22...
Digital-analog converter 23... Motor drive circuit 24... Frequency divider 31... Logic circuit agent patent attorney
Akio Takahashi, 23゜Figure 1 Figure 2 Figure 3 Figure 7 Figure 5 %6 Ward 7

Claims (1)

[Scope of Claims] A detector that detects a rotation signal with a frequency corresponding to the rotation speed of a motor and generates a preset pulse, a latch pulse, and a first clock pulse with the same period as the rotation signal, and a detector that generates a preset pulse, a latch pulse, and a first clock pulse with the same period as the rotation signal, and a preset pulse that is set by the preset pulse. a first counter that counts second clock pulses, and a count value representing one cycle of the rotation signal at the first counter according to the latch pulse; a first latch circuit that latches;
a divider that divides the first clock pulse;
an up/down counter whose mode is set by the count value latched by the latch circuit and counts clock pulses from the branching unit; and an up/down counter whose mode is set by the count value latched by the latch circuit; and the count value of the up/down counter is preset by the preset pulse and the second clock pulse is a second counter that counts, a second latch circuit that latches the count value of the second counter by the latch pulse, and a digital circuit that is supplied with the output of the second latch circuit and that generates a control signal for the motor. - A steady-state speed error correction device comprising an analog converter and configured to be able to reduce a transient state at the time of starting the motor. (2. The steady-state speed error correction device according to claim (1), wherein the branching unit has a branching ratio that is different between within a certain period of time when the motor is driven and after the certain period of time has elapsed.