JPH02196347A - ランタイム監視装置 - Google Patents
ランタイム監視装置Info
- Publication number
- JPH02196347A JPH02196347A JP1018067A JP1806789A JPH02196347A JP H02196347 A JPH02196347 A JP H02196347A JP 1018067 A JP1018067 A JP 1018067A JP 1806789 A JP1806789 A JP 1806789A JP H02196347 A JPH02196347 A JP H02196347A
- Authority
- JP
- Japan
- Prior art keywords
- microcomputer
- interface
- monitoring
- monitoring interface
- control microcomputer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012544 monitoring process Methods 0.000 claims abstract description 39
- 238000012545 processing Methods 0.000 claims description 18
- 230000004044 response Effects 0.000 claims description 5
- 238000012806 monitoring device Methods 0.000 claims description 4
- 230000006870 function Effects 0.000 abstract description 12
- 238000000034 method Methods 0.000 abstract description 8
- 230000009977 dual effect Effects 0.000 description 15
- 230000002093 peripheral effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Landscapes
- Debugging And Monitoring (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1018067A JPH02196347A (ja) | 1989-01-26 | 1989-01-26 | ランタイム監視装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1018067A JPH02196347A (ja) | 1989-01-26 | 1989-01-26 | ランタイム監視装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02196347A true JPH02196347A (ja) | 1990-08-02 |
| JPH0529936B2 JPH0529936B2 (enrdf_load_stackoverflow) | 1993-05-06 |
Family
ID=11961330
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1018067A Granted JPH02196347A (ja) | 1989-01-26 | 1989-01-26 | ランタイム監視装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02196347A (enrdf_load_stackoverflow) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59117646A (ja) * | 1982-12-25 | 1984-07-07 | Fujitsu Ltd | デバツグ用コンソ−ル制御回路 |
| JPS60231242A (ja) * | 1984-04-28 | 1985-11-16 | Toshiba Corp | マイクロプロセツサ開発支援装置 |
-
1989
- 1989-01-26 JP JP1018067A patent/JPH02196347A/ja active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59117646A (ja) * | 1982-12-25 | 1984-07-07 | Fujitsu Ltd | デバツグ用コンソ−ル制御回路 |
| JPS60231242A (ja) * | 1984-04-28 | 1985-11-16 | Toshiba Corp | マイクロプロセツサ開発支援装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0529936B2 (enrdf_load_stackoverflow) | 1993-05-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5594890A (en) | Emulation system for emulating CPU core, CPU core with provision for emulation and ASIC having the CPU core | |
| EP0814404B1 (en) | Debugging apparatus for debugging a program | |
| US6311292B1 (en) | Circuit, architecture and method for analyzing the operation of a digital processing system | |
| US4486827A (en) | Microprocessor apparatus | |
| US6175913B1 (en) | Data processing unit with debug capabilities using a memory protection unit | |
| US7434103B2 (en) | Program processing device | |
| JPS60171558A (ja) | デ−タ処理システム | |
| US7203819B2 (en) | Program processing device | |
| US7437283B2 (en) | System for evaluating target board by using evaluation microcomputer in which storage of environment data are powered by evaluation tool | |
| JP3380827B2 (ja) | エミュレータ装置 | |
| JPH02196347A (ja) | ランタイム監視装置 | |
| JPH0477833A (ja) | デバッグ環境を備えた集積回路 | |
| EP0378242B1 (en) | Integrated circuit with a debug environment | |
| JPH08272770A (ja) | マイクロコントローラディベロップメントシステム | |
| Deiss | A FASTBUS controller module using a multibus MPU | |
| US7194401B2 (en) | Configuration for in-circuit emulation of a program-controlled unit | |
| JPH10187480A (ja) | エミュレータ | |
| JPS59202547A (ja) | デバツグ装置 | |
| JP2002049606A (ja) | マルチｃｐｕシステム | |
| JP2002268911A (ja) | 電子計算機用開発支援装置 | |
| JPH0652333A (ja) | シングルチップ・マイクロコンピュータ | |
| JPH086920A (ja) | 情報処理装置 | |
| JPS62269237A (ja) | デ−タプロセツサ | |
| JPH0477834A (ja) | インサーキットエミュレータ | |
| JPH08147191A (ja) | エミュレータおよびそれを用いたマイクロコンピュータ開発支援装置 |