JPH02195416A - Information processor - Google Patents

Abstract

PURPOSE:To efficiently transmit plural signals by a comparatively simple counterplan without introducing noise by interrupting a signal in a transmission line synchronously with a device. CONSTITUTION:A signal is transmitted from the device 1 to an interface cable 3 through an interface board 6. When an address signal 2 is generated in case of reading out data from a memory in the device 1 by a device 2, a memory reading signal 1 is turned to 'L' at time T1 after a fixed time from the generation of the signal 2, and at time T2 after the lapse of a fixed data undefined period, a data signal 3 is determined. The device 2 fetches data at the falling time T4 of a signal 4. The period from the T1 to the T2 for the signal 3 is set up so that a signal itself such as data is not transmitted and the signal 3 is disconnected from the cable 3 in the period from the T1 to the T2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device in which a signal transmission path is made robust against external signals.

[Conventional technology]

The inside of a general information processing device is composed of a unitized electronic circuit board or unit device made up of a combination of many functional elements, and each of these units is connected via a transmission line via an electrical connector. has been done. However, while signals are exchanged simultaneously on all transmission lines, mutual interference occurs, resulting in unexpected erroneous transmissions between the lines or signals with undesired waveforms being transmitted within the lines. In particular, interface circuits between the central processing unit of digital circuits and external devices have been equipped with dampers to prevent signal energy attenuation, but transmission paths have been made possible without special measures. The configuration was such that the lines were set as short as possible, and the energy between each other was kept to a minimum to prevent noise from being generated in the surrounding area, and the lines were sufficiently spaced for transmission.

In addition, since the signal path and the interface circuit were always connected to the signal transmission path, the signal path was sent without any timing or protection measures against external signals, and there was no need to send it. Even the traffic lights were running on the signal path. In the transmission path of such equipment, signals are likely to influence each other, and unnecessary signals are flowing through the transmission path, which affects the signal that should have a normal waveform, causing the signal to become distorted. Sometimes there was noise.

If you are trying to solve the effects of such noise with a cable alone, you can take measures by making the cable a shielded structure, or you can use a configuration in which the signal line and ground line are combined in the cable and sent as a twisted pair. The structure was such that the signal lines were bundled and separated into layers, and a shielding material was wrapped between them to separate each layer.

FIG. 6 is a cross-sectional view of the conventional interface cable 3, where . is 26 ground signal lines 01 to 026,
◎ indicates 16 signal lines S1 to S1B arranged in a disorderly manner. Therefore, noise is likely to be generated between each of the signal lines S1 to S16 due to mutual induction, and although shielding alone can prevent noise from the outside, it cannot prevent noise due to mutual induction between the signal lines. Since twisted pairs always pair with the ground wire, if cables of the same thickness are used, only half the number of signal wires passing through the cable can actually be used to send signals. In a configuration in which shielding material is wound between each layer, the cable becomes thicker than necessary. To send about 100 deer signals, the cables should be approximately 15mm to 20mm long.
Either the thickness of the cable should be about 1.0 mm, or the connection configuration should be made with two separate cables.Either way, the cost would increase, and the cable would occupy a large volume, making it difficult to place it in a limited space. I can't. Additionally, as the number of cables increases, the number of connectors required at the terminations doubles. This further increases costs.

[Problem to be solved by the invention]

SUMMARY OF THE INVENTION The present invention is intended to solve these problems, and aims to efficiently send a plurality of signals without introducing noise using relatively simple measures.

[Means to solve the problem]

The present invention provides a plurality of devices for mutually transmitting and receiving signals, a transmission line connected between the plurality of devices for signal transmission, and means for cutting off signals in the transmission line in synchronization with the devices. It is characterized by

〔Example〕

The present invention will be described in detail below based on the drawings.

FIG. 1 is a schematic diagram of the apparatus used in the example.

l is to device, 2 is device B, 1 and 2 are to device A
, B are connected to the connector 4.6 via the interface cable 3.

A signal is sent from the device A of No. 1 to the interface cable via the interface port 6.

In the present invention, when sending this signal, the interface port 6
For the interface cable 3, measures have been taken to improve the timing of signal transmission or within the transmission path, and the technical details thereof are as follows.

In FIG. 2, necessary signals and unnecessary signals in the embodiment will be explained.

The basic timing chart when device B shown in FIG. 1 reads the memory in device A is shown in the second diagram.
As shown in the figure.

When signal 2, which is an address signal, is generated, signal 1, which is an MRD (memory read signal), becomes Low at T1 after a certain period of time. Next, at T2 after a certain period of time, signal 3, which is a data signal, is set to be determined. This signal 3 must be fixed until T3, which is a certain period of time.

Device B takes in data at T4, which is the falling edge of signal 4. Signal 4 is a clock signal, and in this embodiment, the period is 100 ns (10 MHz).

The above is the basic time chart of signals during memory read. In this embodiment, the period between T1 and T2 of signal 3 is unnecessary data, and is a period that does not need to be sent to the transmission path.

In addition, the output signal of signal 3 immediately after T1 has an unstable waveform with vibration due to the line capacitance or inductive component of the cable 3, which causes a negative effect on other signals due to mutual induction within the cable. It's easy to become. Settings are made so that signals such as data are not sent between T1 and T2 in signal 3, and even if they are sent, the receiving end is set in an insensitive state. In this embodiment, the shortest time from T1 to T2 is 230 ns, but as mentioned earlier, the 150 ns at the beginning of the signal is particularly likely to be the cause, and it is necessary to take measures for this period.

Using Figure 3, signal 3 connects cable 3 from TI to T2.
A circuit configuration that is more open-ended will be explained.

2 is device B, 3 is a cable, 4 and 5 are connectors, and 6 is an interface port. Its circuit configuration is 7
is a bidirectional pass buffer element (748C245), and points F and G are input/output PINs for signal 3. Point E is the transmission direction switching manual DIR (bin 1), and signal 3 goes from point F to point G in a low state. Point D is a gate enable signal (pin 19), which opens the gate when it is low.

8 is a pull-up resistor, which is 10Ω in this embodiment, and 9 is a resistor, which is 68Ω in this embodiment. Further, 10 is a capacitor of 1000 pF in this embodiment. This 8.9.10 constitutes a signal delay circuit of approximately 160 ns. 11 and 12 are inverters (74HCO4), and 13 is a two-man-powered AND element (74HCO8). 14.15.16.17 are pull-up resistors,
In this embodiment, Ω is used for 10.

The basic configuration of the interface circuit 6 has been described above. Next, the operation of this circuit will be explained according to the time chart shown in FIG.

At T1, the A point signal l, which is a memory read signal, falls to LOW. Point B, which is the inverted signal, becomes High immediately, but point C, which is the inverted signal, becomes High after about 160 ns due to the CR delay circuit configured in 8.9.10.
The potential is maintained at High until it becomes Low. As a result, it takes approximately 160ns after signal 1 becomes low.
During this period, the gate enable signal remains High, so the signal 3 is disconnected between the F point and the G point.

Therefore, as shown in Fig. 4, from T1 to T3, signal 3 is sent up to point F, but at point G, from T5 to T3.
Signals are sent only until then.

During the period from T1 to T5, no uncertain and unnecessary data signals are sent to the cable side.

The shortest time from T1 to T2 is 230 ns, but the disconnected time is about 160 ns from T1 to T5, so the period from T2 to T3 required for signal 3 is connected. Approximately 7 Or*s from T5 to T2
is the margin. In order to prevent early signals, which are the most harmful and uncertain data, from being transmitted to the cable, 16
0ns is a sufficient effective interval.

FIG. 5 is a cross-sectional view of the interface cable 3 according to the present invention, in which 26 ground signal lines Q are shown, and 16 signal lines P are arranged in approximately three layers. A signal line P is arranged in the middle layer, a ground line Q is arranged in the intermediate layer, and other signal lines R are arranged in the outer core layer. This may be increased to 6 or 7 layers by providing multiple layers of ground lines.

What is placed in close proximity to the signal line P is the ground line or the signal line P itself, but the signal line P is a wire that easily generates noise.
The period from 1 to T2 is a data confirmation period, so there is no problem in operation. Therefore, by adopting such a structure for arranging the signal line and the ground line, the problem can be solved without increasing the total number of thin wires in the cable and without increasing costs.

Above, we have explained the embodiment using memory read, but
Since it can be applied when determining data in the exchange of various data, it can be applied to various storage devices, communication devices, etc.

Furthermore, although the cable has been described as having three layers, it is conceivable that the cable may have four or more layers, with the even-numbered layers serving as ground wire layers.

〔Effect of the invention〕

The interface circuit of the present invention as described above eliminates the need to send unnecessary signals that cause noise to the cable, so unnecessary noise interference within the cable can be avoided, and multiple signals efficiently,
It can be sent with fewer errors. As a result, stable operation is guaranteed between devices that are relatively apart, and the present invention can be applied in the same way to devices that will become multi-functional in the future or connect peripheral devices in series, increasing the connection interval. It is something that can be done.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an outline of a configuration device according to an embodiment of the present invention. FIG. 2 is a diagram showing the timing of an embodiment according to the present invention. FIG. 3 is a diagram of an interface circuit showing an embodiment according to the present invention. FIG. 4 is a time chart diagram of an interface circuit according to an embodiment of the present invention. FIG. 5 is a sectional view of an interface cable according to an embodiment of the present invention. FIG. 6 is a sectional view of a conventional cable. 1: Device A 2: Device B 3: Interface cable 4.5: Connector 6: Interface port Applicant Seiko Epson Corporation Agent Patent attorney Kizobe Suzuki and 1 other person Figure 2

Claims (1)

[Claims] A plurality of devices that mutually transmit and receive signals, a transmission line connected between the plurality of devices for signal transmission, and a means for cutting off signals in the transmission line in synchronization with the devices. Information processing equipment.