JPH02194511A - Ceramic capacitor - Google Patents

Abstract

PURPOSE:To realize a large capacity by keeping a small shape and to reduce a defect by a method wherein an electrode layer is not a complete face shape but has a structure containing a part not covering a dielectric layer. CONSTITUTION:In a ceramic capacitor in which at least two or more electrode layers have been formed via a dielectric porcelain layer, the electrode layers are not a complete face shape but are formed as a mesh structure having small hole parts not covering the dielectric layer; an average thickness of the electrode layers is formed to be 2mum or lower. Alternatively, the electrode layers are not the complete face shape but may have a structure having small groove parts not covering the ceramic dielectric layer from a part from which an electrode is extracted to the outside toward other parts. In addition, one of the mutually adjacent electrode layers may be a face shape not containing a defect and the other may be a structure having a part not covering the ceramic dielectric layer. Thereby, it is possible to prevent a defect by a strain between the electrode and the dielectric layer; when an area ratio of the part not covering the dielectric layer among the electrode layers is set to a proper value, drop in capacity can be suppressed to be small and cost of the electrode can be reduced.

Description

[Detailed description of the invention] Industrial applications The present invention relates to ceramic capacitors.

BACKGROUND OF THE INVENTION In recent years, multilayer capacitors are rapidly becoming popular due to the demand for smaller ceramic capacitor elements and larger capacitance. In addition, due to the demand for higher frequency circuits and higher reliability of components, it has become necessary to use ceramic multilayer capacitors for capacitors of 1μF and above, where conventionally aluminum electrolytic capacitors and tantalum electrolytic capacitors were used. are doing. In order to obtain a large-capacity ceramic multilayer capacitor while keeping the element shape small, it is necessary to use a dielectric with a high dielectric constant, reduce the thickness of the dielectric, and increase the number of internal electrode layers that make up the capacitance. It becomes necessary.

However, as the thickness of the dielectric layer decreases and the number of internal electrode layers increases, distortion tends to occur inside the laminate due to the difference in firing shrinkage and expansion coefficient between the ceramic phase and the metal phase. It has problems such as the occurrence of defects such as interlayer 11M and cracks.

In response, the inventors have proposed a ceramic multilayer capacitor in which a lead-based dielectric is used and the dielectric layer and electrode layer are made thinner.

Problems to be Solved by the Invention In view of the above problems, it is an object of the present invention to provide a ceramic capacitor that achieves a large capacity while maintaining a small size and has fewer defects.

Means for Solving the Problems The present invention presents three means, which are characterized in that, taken together, the electrode layer has a structure that is not completely planar but has a portion that does not cover the dielectric 1d. A means corresponding to claim 1 is that the electrode layer has a network structure having pores. A means corresponding to claim 2 is that each electrode has a structure in which each electrode has a narrow groove that does not cover the dielectric material from a portion extending to the outside of the electrode toward other portions. A means corresponding to claim 4 resides in that every other electrode layer has a structure that is not completely planar but has a portion that does not cover the dielectric layer.

Effect: In the ceramic capacitor having the above structure, defects due to strain between the electrode and the dielectric layer can be prevented.

In addition, the area ratio of the part of the electrode layer that does not cover the dielectric layer is determined by adjusting the dielectric thickness and the size of each part of the part that does not cover the dielectric layer. It would be possible to suppress the decrease in capacity due to the absence of the metal to a small extent, and reduce the electrode cost.

Example Embodiments of the present invention will be described below with reference to the drawings.

Example 1 A material represented by the following compositional formula was used as the composition of the dielectric layer.

Pb+, aq (Mg+/3Nb21t) +! , 7T
iΩ19 (N it/2WI·2)t+,++ot The dielectric powder was manufactured according to a normal ceramic manufacturing method. The dielectric powder is regular ceramic 5! It was made into a sheet on an organic film using a manufacturing method. Palladium black powder or normal Y&fine palladium powder is used as the starting material for the internal electrodes, and in some cases, 20 wt% of the same powder as the dielectric material with an average particle size of 0.1 μm is added to these powders. 10 wt % of ethyl cellulose resin was added as a binder to the inorganic powder, and 80 wt % of a solvent was added to form a slurry using a three-roll mixer. This electrode paste was printed on a dielectric sheet by a screen printing method using screen meshes with different amounts of ink applied. The dielectric layers were stacked in 1, 2, and 3 layers and had a film thickness of 10 zz m after firing. Dummy layers were formed above and below, and 51 electrode layers were laminated so that the internal J pole layer was alternately drawn out at the center to form a laminated chip.

After burning out the binder, the laminated chip was baked in air at 1000° C. for 2 hours. After firing, a silver paste was applied to the cross section of the laminated chip where the internal electrodes were exposed and baked to form external electrodes. In the produced ceramic multilayer capacitor, the area surrounded by the end line where the internal electrodes are exposed at the intersection l and the end line of the side surface 0I11 in the projection plane of the alternately overlapping portion of the electrode layers is -/ W
It was 2°97mm2.

The ceramic we created! [Capacitor element is 20℃, 1
k l (z, the capacitance and tan δ were measured using an alternating current signal voltage of 1), and the internal electrode layers of 10 samples were polished perpendicularly to the electrode surface to expose them. By pattern analysis, we calculated the average diameter of the electrode, the average diameter of pores that do not cover the dielectric layer in the internal electrode, and the actual occupancy z of the electrode relative to the external area of the electrode layer. We checked for peeling and cracks in the living room.

Regarding capacitance, the appearance rate of capacitance for each dielectric film thickness with respect to z=1 was determined.

Table 1 shows each sample number, dielectric thickness, electrode film thickness, average pore diameter, ratio y/x of dielectric thickness X to average pore diameter y, internal electrode occupancy z, capacity appearance rate, tan δ indicates the number of defects in 10 samples. Further, FIG. 1 shows sample numbers having y/x and z near the range shown in claim 3.

(Margins below) As is clear from Table 1 of Comparative Examples outside the scope of claim 3, the internal electrode layer of the first layer is smaller than 2 μm! 1) In a structure having pores that do not cover the dielectric layer, stacking faults are less likely to occur even in an element with a high number of stacked layers including 61 electrode layers as in the example.

Furthermore, a dielectric thickness and a pore diameter of 2 within the range described in claim 3 have a capacity of 90% or more compared to a structure in which the internal electrode layer has a complete plate-like internal electrode. This has the advantage of being able to obtain the following properties, which also makes it possible to reduce the cost of internal electrodes.

Example 2 A material represented by the following compositional formula was used as the composition of the dielectric layer.

Ba+, seT ill, 7eZrl! , 3a03:
The MnO20, 1vt% dielectric powder was manufactured according to a conventional ceramic manufacturing method. The dielectric powder was formed into a sheet on an organic film using a conventional ceramic manufacturing method. Regular fine palladium powder was used as the starting material for the internal electrodes, and 8 wt% of ethyl cellulose resin was added as a binder to these inorganic powders, and 50 wt% of a solvent was added! It was made into a slurry using a Miki roll mixer. This electrode paste was printed on a dielectric sheet L by a gravure printing method. This gravure plate consists of a continuous thin line pattern from the internal electrode lead-out end toward the inside. The dielectric layers were stacked in 1, 2, and 3 layers and had a film thickness of 1271 rn after firing. A dummy layer was placed under L, and the electrode layer was made into a 51-layer stack with a thickness of 1/4 inch so that the internal electrode layers were drawn out alternately at the center.

After burning out the binder, the laminated chip was fired in air at 1350° C. for 2 hours. For each fired laminated chip, a silver paste was applied to the cross section where the internal electrode was exposed and baked to form the external electrode. The fabricated ceramic multilayer capacitor has the area surrounded by the pitch W (alternately on the surface) where the electrode layers overlap, the edge line on the end surface where the internal electrodes are exposed, and the edge line on the side surface ζ. l
2°88 opening per oval, average electrode thickness of linear part 2.27
It was 1m.

The prepared ceramic multilayer capacitor element was heated at 20°C and 1
k f (z, measure the physical characteristics and tan δ with alternating current signal voltage IV) Furthermore, for 10 samples, the internal electrode layer was polished perpendicular to the electrode surface to expose it, and by pattern analysis of the SEM photograph of electrode 1, The average line width and average spacing (width of narrow grooves) y of the electrodes were measured, the occupancy rate of the internal electrodes was calculated, and the presence or absence of delamination and cracks in the sample was confirmed.Also, the capacitance was determined for each dielectric material. The appearance rate of capacity for the film thickness with occupancy = 1 was determined.

Table 2 shows each sample number and dielectric material r5. x, line 111, line spacing y and internal electrode occupation'>G z, ratio y/x of dielectric thickness X and line spacing FM y, capacity xi, t a, n δ, trial r
↓Indicates the number of defects in 10 cases. Further, FIG. 2 shows a sample number having T5Hz occupied by the y/

(Hereinafter, the remainder []) Table 2: Comparative examples outside the scope of the present invention marked with tt indicate comparative examples outside the scope of claim 3. A structure having grooves is less likely to cause stacking defects even in an element with a high number of stacked layers including 51 electrode layers as in the example. Furthermore, a dielectric thickness and a pore diameter of 2 within the range described in claim 3 have a volume of 90% or more compared to a structure in which the internal electrode layer has a complete plate-like internal electrode. This has the advantage of being able to obtain the following properties, which also makes it possible to reduce the cost of internal electrodes.

Example 3 A material represented by the following compositional formula was used as the material of the dielectric layer.

Ba+1lsTit1. vlIZr@, toOt: M
The nO20,1wtX dielectric powder was manufactured according to a conventional ceramic manufacturing method. The dielectric powder was formed into a sheet on an organic film using a conventional ceramic manufacturing method. Ordinary fine palladium powder was used as the starting material for the internal electrodes, and 8 wt% of ethyl cellulose resin was added as a binder to these inorganic powders, and 50 wt% of a solvent was added.
The slurry was made into one layer using this roll mixer. This electrode paste was printed on the dielectric sheet (1) by a gravure printing method using an ink-coated gravure plate. The gravure plate for printing the internal electrode layer uses a plate consisting of a thin linear pattern continuous from the internal electrode lead-out end towards the inside ζ and a plate consisting of a pattern that can form a complete plate-like electrode on the entire surface. Internal electrode layers were printed using these plates, and the laminated 6A main layer had a thickness of 12 Bm after firing, and 1.2.3 layers were used. This was used as a dummy layer in 1.1, and 51 electrode layers were stacked so that the internal electrode layers were alternately drawn out from the center. The average thickness of the linear electrode portion after firing was 2.2 μm.

After burning out the binder, the laminated chips were fired in air at 1350° C. for 2 hours. After firing, a silver paste was applied to the cross section of the laminated chip where the internal electrodes were exposed and baked to form external electrodes. The manufactured ceramic laminated capacitor has an area surrounded by the end line and the side edge line where the internal electrodes are exposed is 2 per layer. It was ゜88mnp'.

The prepared ceramic IRN capacitor element was heated at 20°C and 1
8 songs and jan δ were measured with alternating current at kHz and signal voltage of 1 mm, and the internal electrode layers of 10 samples were exposed by polishing perpendicular to the electrode surface, and pattern analysis of SEM photographs of the electrode parts revealed that Measure the average width of the electrodes (15 mm)
The sample was also checked for delamination and cracks.

In addition, regarding the capacitance, the occupancy T factor for each dielectric film thickness =
The appearance rate of capacity for that of 1 was determined.

Table 3 shows each test N number, dielectric material J, line 11, and line spacing y.
It also shows the internal electrode occupancy z, the ratio y/x of the dielectric degree X and the line spacing y, the capacitance yield M rate, j a n δ, and the number of defects in 10 samples. Further, FIG. 73 shows sample numbers having y/'

(The following is a blank space) Table 3 Marks indicate comparative examples outside the scope of the present invention.As is clear from Table 3, the marks indicate comparative examples outside the scope of the present invention. If the layer has a structure in which each layer has a narrow groove that does not cover the dielectric material L, even in an element with a high number of laminated layers and electrodes of 51.7Δ as in the example, there will be defects in the stack j'. Hard to occur. Furthermore, the dielectric thickness and pore diameter within the scope of claims on page 31 are 90% compared to those in which the internal electrode layer has a complete plate-like internal electrode. % or more, and this range is also wider than that of Example 1.2. This should also make it possible to significantly reduce the cost of internal electrodes.

Example 41 As the composition of the dielectric layer, a material represented by the following compositional formula was used.

Pt)+8s(Mg+・:+Nb2zt) s7T i
i+, +9(N i+·2W+···2)S,++O:+ The dielectric powder was manufactured according to a normal ceramic manufacturing method. The dielectric powder was formed into a sheet into an organic film compound using a conventional ceramic manufacturing method. Palladium black powder or ordinary fine palladium powder is used as the starting material for the internal electrodes, and some of them are added with an average particle size of 0. 1
Add 20wt% of powder of the same quality as the dielectric layer of μm11 and use lowt as a binder to these inorganic powders.
% of ethyl cellulose resin and 80 wt % of solvent were added to form a slurry using a three-roll mixer. This electrode paste was printed on a dielectric sheet by a screen printing method using a different screen printing method using an ink applicator. For the internal electrode layer, one having a complete plate shape and the other having a structure having pores were alternately formed on the IJlj. The dielectric layer has a film thickness of 07 zm after firing.
2.3 layers were stacked and used. Dummy layers were formed above and below, and 51 electrode layers were laminated so that internal electrode layers were alternately protruded from the center to form a laminated chip.

After burning out the binder, the 112 chips were fired in air at 1000° C. for 2 hours. After firing, a silver paste was applied to the cross section of the laminated chib where the internal electrodes were exposed and baked to form external electrodes.

The manufactured ceramic multilayer capacitor has an area of 2°97m1I+2 per layer, which is surrounded by the edge line and the side edge line where the internal electrodes are exposed alternately on the projected plane of the parts of the electrode layers that alternately face each other to the east. And ivy.

The fabricated ceramic multilayer capacitor element was heated at 20℃ and 1K.
Measure the capacitance and tanδ with alternating current of Hz and signal voltage of 1■,
Furthermore, for 10 samples, the internal electrode layer was polished perpendicular to the electrode surface to expose it, and pattern analysis of the SEM photograph of the electrode part was performed to determine the average thickness of the electrode and the pores that do not cover the dielectric layer in the internal electrode. The average diameter of the sample and the actual occupancy z of the electrode relative to the external area of the electrode layer were measured, and the presence or absence of interlayer peeling and cracks in the sample was also confirmed. Regarding capacitance, the appearance rate of capacitance for each dielectric film thickness with respect to z=1 was determined.

Table 4 shows each sample number, dielectric thickness, electrode film thickness, average diameter of pores, and ratio of dielectric thickness X to average diameter of pores y/x, z.
, capacity appearance rate, tan δ, and number of defects in 10 samples. Further, FIG. 4 shows sample numbers having y/x and internal electrode occupancy rates near the range indicated in claim 7.

Table 4: Comparative examples outside the scope of the present invention are marked with Comparative examples outside the scope of the present invention.As is clear from Table 4, the internal electrode layer does not cover the dielectric layer. -pj! The structure that each has is 5xI7! as in the example. Stacking faults are less likely to occur even in devices with a high number of laminated electrode layers. Furthermore, in the case where the dielectric thickness and the pore diameter are within the range described in claim 3, the internal electrode layer has a volume of 90% or more compared to the case where the internal electrode is in the form of a complete plate. It has the advantage that @ can be obtained, and this range is also wider than that of Example 1.2. This also allows for further reduction of internal electrode costs.

Although not mentioned in this embodiment, it is obvious from this embodiment that when the structure of the electrodes to be baked in a disk capacitor is configured as in this embodiment, a large capacity can be obtained with a small amount of electrodes used.

Effects of the Invention The ceramic capacitor of the present invention has few defects even when the ceramic capacitor has a laminated structure with a high number of laminated layers. In addition, if the conditions are selected, a large capacity can be obtained with a small amount of electrode usage.
Electrode costs can be reduced.

[Brief explanation of the drawing]

FIGS. 1 to 4 are graphs showing sample numbers having y/x and internal electrode occupancy rates near the range indicated in the claims of the present invention. Name of agent: Patent attorney Shigetaka Awano 1 name, 1 name! /
11 of the so-called 1tT13 range of 1tT13;

Claims (7)

[Claims] (1) In a ceramic capacitor in which at least two or more electrode layers are formed through a dielectric ceramic layer, the electrode layer is not completely planar but has a network structure with pores that do not cover the dielectric layer. A ceramic capacitor characterized in that the average thickness of the electrode layer is 2 μm or less. (2) In a ceramic capacitor in which at least two or more electrode layers are formed through a dielectric ceramic layer, the electrode layer is not completely planar, and extends from the part where the electrode is drawn out to the other parts. A ceramic capacitor characterized by having a structure having a narrow groove portion that does not cover a ceramic dielectric layer. (3) The occupancy rate of the area where the electrode actually exists relative to the area of the outer shape of the electrode layer of the ceramic capacitor is z, the thickness of the dielectric layer is x μm, and the average value of the diameter of the pores or the width of the narrow groove in the electrode layer. The ceramic capacitor according to claim 1 or 2, wherein the ceramic capacitor is in the following range, where yμm is y/x≦1 z≧0.5+0.5 (y/x). (4) In a ceramic capacitor in which at least two or more electrode layers are alternately laminated with dielectric ceramic layers in between, one of the adjacent electrode layers has a defect-free surface and the other does not cover the ceramic dielectric layer. A ceramic capacitor characterized by having a structure. (5) A claim characterized in that one of the adjacent electrode layers of the ceramic capacitor has a planar shape with no defects and the other has a network structure that is not completely planar and has pores that do not cover the dielectric layer. 4. The ceramic capacitor described in 4. (6) Adjacent electrode layers of a ceramic capacitor have one surface with no defects and the other with a perfect surface, and cover the ceramic dielectric layer from the part where the electrode is drawn out to the other parts. 5. The ceramic capacitor according to claim 4, wherein the ceramic capacitor has a structure having a narrow groove portion. (7) Among the adjacent electrode layers of a ceramic capacitor, the occupancy rate of the area where the electrodes actually exist relative to the external area of the layer that is not completely planar is z, and the thickness of the dielectric layer is x μm.
, the average value of the pore diameter or narrow groove width in the electrode layer is yμ
7. The ceramic capacitor according to claim 5, wherein m is in the following range: y/x≦1 z≧0.35+0.65 (y/x).