JPH02193241A - Communication controller - Google Patents

Abstract

PURPOSE:To prevent the extension of the processing time without having an influence upon a memory by using an idle area in a stack at the time of overflow of the stack where a processing request will be stored. CONSTITUTION:When a stack 3 where processing request information already designated by a central processing unit 1 will be stored overflows, a stack address control circuit 21 changes the overflow stack 3 by a stack pointer detection signal 17, an overflow address select signal 27, and an idle stack holding register 29 and outputs an overflow stack address signal 28 for the purpose of store processing request information in another idle stack 3, and this signal 28 passes a selector 22 to become the address of this stack 3. Then, the overflow stack 3 is changed to another idle stack 3. Thus, extension of the processing time is prevented without having an influence upon the memory.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is applied to a communication control device. The present invention relates to overflow processing when processing request information from firmware and each control unit is temporarily stacked.

〔overview〕

The present invention provides a communication control device that is connected to a central processing unit and performs processing by temporarily stacking firmware and processing request information from each control unit. By making the empty area available for use, the processing time is prevented from increasing without affecting memory.

[Conventional technology]

Conventionally, this type of communication control device has been composed of a plurality of stacks that store firmware and processing request information from each control section, and a stack pointer that indicates a read/write position within the stack. The stack where processing request information is stored is determined by the processing level, and if processing request information is concentrated at a specific processing level and the stack overflows, new processing request information is read from each control unit using an input/output command and stored in memory. However, when the stacked processing request information is processed and the stack overflow is cleared, the processing request information stored in memory is sequentially re-stacked.

[Problem that the invention seeks to solve]

In the conventional communication control device described above, when processing request information is concentrated at a specific processing level and the stack overflows,
Since the data is temporarily stored in the memory, the data storage area of the memory is reduced, and the processing time required to temporarily move the storage area of the processing request information from the stack to the memory and then return it to the stack is disadvantageous.

The present invention aims to eliminate such drawbacks and to provide a device that can prevent an increase in processing time without affecting memory.

[Means for solving problems]

The present invention includes a plurality of stacks that store processing request information from a central processing unit, and stack control means provided corresponding to each of the stacks, and each of the stack control means controls a pointer of the stack. In the communication control device, the stack control circuit includes a pointer control section for detecting an overflow, and an overflow detection section for detecting an overflow, and is connected to the central processing unit and commonly controls the stack. An overflow status holding register that holds an address, an empty stack holding register that holds the address of a stack with an empty area, a stack address signal from the central processing unit, and an address signal indicating an overflowed stack from the overflow status holding register. The present invention is characterized in that it comprises an address comparator that compares the processing request information and a stack address control circuit that controls the storage of processing request information into a stack with an empty area indicated by the empty stack holding register.

[Effect]

When a stack overflow is detected by the overflow detection section of the stack control means, the overflow status holding register of the stack control circuit holds the address of the overflowed stack, and the empty stack holding register holds the address of the stack with an empty area. . On the other hand, the address decoder outputs an address decode signal for the stack specified by the stack address signal from the central processing unit, and the address comparator compares this address decode signal with the overflow signal from the overflow status holding register to control the stack address. A circuit performs control to store processing request information in a stack with an empty area based on outputs from an address comparator, a stack control means, and an empty stack holding register, and a selector stores processing request information in an empty stack under this control.

This makes it possible to prevent an increase in processing time without affecting memory when the stack in which processing request information is to be stored overflows.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the stack control circuit 2 of the embodiment of the present invention, and FIG. 3 is a block diagram showing the configuration of the stack control means of the embodiment of the present invention. FIG.

The embodiment of the present invention includes a plurality of stacks 3 for storing processing request information from the central processing unit 1, and stack control means 4 provided corresponding to each of the stacks 3. , a stack control circuit 2 that is connected to a central processing unit 1 connected to a bus 30 and that commonly controls the stack 3, including a pointer control unit 5 that controls the pointer of the stack 3, and an overflow detection unit 6 that detects overflow. This stack control circuit 2 includes an overflow status holding register 18 that holds the address of the stack that has overflowed, an empty stack holding register 29 that holds the address of the stack 3 that has an empty area, and a an address decoder 19 that outputs an address decode signal of the stack designated by the stack address signal; an address comparator 20 that compares this address decode signal with an address signal indicating the overflowed stack 3 from the overflow status holding register 18; A stack address control circuit 2 that controls storing processing request information in a stack 3 with an empty area indicated by an empty stack holding register 29
1, and a selector 22 that selects a stack address signal for storing processing request information in the stack. A memory 31 is connected to the bus 30, and the plurality of stacks 3 are connected to the line interface 31, respectively.

Processing request information from the central processing unit 1 is connected to the stack control circuit 2 via a data address signal 11 and to the stack 3 via a data address signal 12.

The stack control circuit 2 functions as an interface with the central processing unit 1, and controls processing request information when the stack 3 overflows.

The pointer control section 5 of the stack control means 4 controls the write and read stack pointers, and the overflow detection section 6 detects stack overflow and sends a detection signal to the stack control circuit 2 shown in FIG. 1 using an overflow detection signal 14. Notice. Further, the stack control means signal 13 shown in FIG. 1 is the write stack pointer signal 1 shown in FIG.
5 and a read stack pointer signal 16.

Next, the operation of the embodiment of the present invention configured as described above will be explained. When an overflow of the stack is detected by the overflow detection section 6 of the stack control means 4 shown in FIG. 2, the stack control circuit 2 shown in FIG. 1 is notified by an overflow detection signal 14.

In the stack control circuit 2, the overflow signal 14 detected by the overflow detection section 6 shown in FIG.
9, and the stack address decoder 19 is designated by the stack address signal 24 from the central processing unit 1.
The address decode signal 25 from and the stack overflow signal 26 are compared by the address comparator 20,
The overflow address select signal 27 indicates whether there is an overflow.

If the stack 3 storing processing request information has not overflowed, the stack address signal 24 is sent to the selector 22.
It passes through and becomes the address of stack 3.

If the stack 3 designated by the central processing unit 1 has already overflowed, the overflow address select signal 27 output from the address comparator 20 and the stack pointer detection output from the pointer control unit 5 shown in FIG. The signal 17 is notified to the stack address control circuit 21.

The stack control circuit 21 receives the stack pointer detection signal 17
The overflow stack address is changed to the overflowing stack 3 designated by the central processing unit 1 by the overflow address select signal 27 and the empty stack holding register 29, and the processing request information is stored in the empty stack 3. A signal 28 is outputted, passes through the selector 22, and becomes the address of the stack 3. This allows the overflowing stack 3 to be changed to another empty stack 3.

〔Effect of the invention〕

As explained above, according to the present invention, when the stack in which processing request information is to be stored overflows, an empty area in the stack is used to prevent an increase in processing time without affecting memory. There is an effect that can be done.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of a stack control circuit according to an embodiment of the present invention. FIG. 3 is a block diagram showing the configuration of the stack control means according to the embodiment of the present invention. 1... Central processing unit, 2... Stack control circuit, 3
...Stack, 4...Stack control means, 5...
Pointer control unit, 6... overflow detection unit, 11.
12... Data address signal, 13... Stack control means signal, 14... Overflow detection signal, 15
...Write stack pointer signal, 16...Read stack pointer signal, 17...Stack pointer detection signal, 18...Overflow status holding register, 1
9... Address decoder, 20... Address comparator, 21... Stack address control circuit, 22... Selector, 23... Processing request information, 24... Stack address signal, 25... Address decode signal, 26
...Stack overflow signal, 27... Overflow address select signal, 28-... Overflow stack address signal, 29... Empty stack holding register, 30... Bus, 31... Memory, 32... line interface.

Claims (1)

[Scope of Claims] 1. A plurality of stacks for storing processing request information from a central processing unit, and stack control means provided corresponding to each of the stacks; A communication control device comprising a pointer control section for controlling a pointer and an overflow detection section for detecting an overflow, and a stack control circuit connected to the central processing unit and commonly controlling the stack, the stack control circuit comprising: An overflow status holding register that holds the address of an overflowed stack; an empty stack holding register that holds the address of a stack with an empty area; and a stack address signal from the central processing unit and the overflowed stack from the overflow status holding register. and a stack address control circuit that controls the storage of processing request information into a stack with an empty area indicated by the empty stack holding register. Control device.