JPH02192288A - Chroma signal storage circuit - Google Patents

Abstract

PURPOSE:To save a memory capacity by sectioning an input chroma signal at a period of fSC and outputting the data for one period for the plural number of times when only the data of one period in plural consecutive period is stored in a memory and outputted. CONSTITUTION:A chroma signal inputted from a terminal (a) is sampled by an A/D converter 5 and written in a memory 6. In this case, the sampling and write clock are implemented intermittently and four times of consecutive sampling and four times of pauses are executed alternately. An output from the memory 6 is given intermittently, but during data is outputted, a switch 9 selects a memory output and the switch 9 selects an output of a shift register 10 during the pause period thereby inputting a consecutive sampling data to a D/A converter 8. That is, the same waveform is outputted twice by circulating the waveform subjected to representative sampling by the shift register 10. Thus, the memory capacity is saved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit for storing chroma components of a video signal.

[Conventional technology]

The frequency components of the chroma signal are approximately 48!12, which is the color subcarrier (NTSC: 3.12).
58 MIIZ), and the color signal itself practically only includes frequency components up to about Q and 58H2.

Therefore, one conventional method has been to demodulate the color signal and sample it at a low sampling frequency to save memory space.

An example of the configuration of this method is shown in FIG. A chroma signal is input from a terminal a, and a color demodulation circuit 51 reproduces color difference signals RY and BY. The (i) of R-Y and B-Y is alternately selected by the switch 52 and sampled by the A/D converter 53. After the sampling data is stored in the memory 54, the data is transferred to the D/A converter. RY at 551 and 552,
Each of B and Y is output separately and sent to the color modulation circuit 56.
The signal is returned to the chroma signal. A sampling clock is input to the terminal C, and normally a color subcarrier fsc (3.58HtL7 in the NTSC system) which is produced as a subsidiary in the color demodulation circuit 51 is used.

The A/D converter 53 operates at this 3.58 Hf1z, but since it samples R-Y and B-Y alternately, the sampling frequency of the color difference signal is 1.79) I
Hz. As mentioned above, the practical color difference band is 0.5 M
Hz, a sampling frequency of 1.79 MHz is sufficient. If the chroma signal is directly sampled, the color subcarrier will be 3 times (approximately 10.781
Since a sampling clock of 1z) or higher is required,
By demodulating, the memory capacity can be reduced to 1/3.

Another method in the prior art is to convert the chroma signal to a lower frequency. For example 4.38H2
By multiplying the reference frequency by the chroma signal, the chroma signal can be converted to the 0.7 MHz±0.58IIZ (7) band. The maximum frequency after changing vA is 1.2) IHz
Therefore, as in the prior art described above, color subcarriers (3,
58HIIZ) enables sampling.

[Problems to be Solved by the Invention] The above-mentioned conventional chroma signal storage circuits all perform processing such as demodulation and frequency conversion at the analog signal stage, so they have the disadvantage of requiring phase adjustment and level adjustment. . In particular, phase information is an important parameter for chroma signals, so it is impossible to cut corners in phase adjustment. Also, A
Although it is possible to perform demodulation and frequency conversion operations at the stage of digital data after /D conversion, it is not generally used because it is expensive.

[Means to solve the problem]

The chroma number storage circuit of the present invention includes means for generating a color subcarrier tsc synchronized with the color burst of an input chroma signal, and sampling the input chroma signal at a frequency obtained by multiplying the fSC by n (n is an integer of 3 or more). and n consecutive samples from the sampling series every time the f 8C is counted m times (m is an integer of 2 or more)! i:
It has means for extracting, and means for repeatedly outputting the n consecutive samples m times.

[Effect]

While the conventional storage circuit described above lowers the frequency band of the storage signal, the present invention improves the correlation between the waveforms of adjacent periods when the waveform of the chroma signal is divided by the color subcarrier period. Focusing on the fact that the waveform is high, one waveform of a plurality of consecutive cycles is used to represent the waveforms of a plurality of cycles.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of a chroma signal storage circuit according to the present invention.

Terminal a is a chroma input terminal and is connected to A/D converter 5 and f lie generation circuit 1 . The output of the A/D converter 5 is connected to a memory 6, and the output of the memory 6 is connected to the input of a switch 9.

The output of switch 9 is connected to a four-word shift register 10, and the output of shift register 10 is connected to D/A converter 8 and another input of switch 9. D/
The output of the A converter 8 is output as a chroma signal from the terminal. On the other hand, the fsC generation circuit 1 generates a color subcarrier f8C synchronized with the color burst of the input chroma signal, and supplies it to the 4-coupled multiplier 2 and the 2-frequency divider 3.

Quadruple multiplier 2 creates a clock that is four times as large as fSC, and
This is used as an operation clock for word shift register 10 and D/A converter 8. The f9C frequency clock generated by the 2 frequency divider 3 is used for switching the switch 9 and as a gate signal for the gate circuit 4. The gate circuit 4 gates the output clock of the quadruple multiplier 2 with the output of the frequency divider 3, thereby creating intermittent locking, and
Converter 5. This is used as the operating clock for the write/read control circuit 7.

Next, the operation of this embodiment will be explained according to the flow of chroma signals. The chroma signal input from terminal a is sampled by A/D converter 5 and written into memory 6. At this time, the sampling and self-clocking are intermittently, and the four consecutive samplings and the four pause operations are performed alternately. The output from the memory 6 is also intermittent, but the switch 9 selects the memory output during the period when data is being output, and the switch 9 selects the output of the shift register IO during the pause period, so that the D/A converter 8
Continuous sampling data is input to . That is, by passing the representatively sampled waveform in the shift register 10 once, the same waveform is output twice.

FIG. 2 is a block diagram of a second embodiment of the chroma signal storage circuit of the present invention.

In this embodiment, a 4-word shift register 11 and a switch 12 are provided between the A/D converter 5 and the memory 6 in the first embodiment, and the 4-word shift register 11 is replaced with the switch 9 and the 4-word shift register 10. 13.14 and switch 1
5 is provided.

Next, the operation of this embodiment will be explained.

Half of the data of the output of A/D converter 5 is sent to switch 1.
2 to the memory 6, and the remaining half of the data is supplied to the memory 6 through 4.
After passing through the word register 11, it is supplied to the memory 6 through the other input of the switch 12. Since the switch 12 is switched every four samplings, the data written to the memory 6 is for four out of eight A/D samplings. The output from the memory 6 is input to a 4-word shift register 13, and the output of the shift register 13 is input to a shift register 14. Also, switch 1
5 selects the outputs of the memory 6 and shift register 13, or selects the outputs of shift registers 13 and 14, and is connected to the D/A converter 8. Since the switch 15 is switched every fSO, the same waveform is output to the D/A converter 8 twice in succession.

The advantage of this embodiment is that it is suitable for a memory whose bit configuration is x4 bits. Furthermore, since the write/read control circuit 7 operates with a continuous clock, it can be used in common with the control circuit of the luminance signal storage circuit used with the circuit of the present invention.

(Effects of the Invention) As explained above, the present invention can convert input chroma signals to f80
Conventional methods save memory capacity by dividing the data into cycles, storing only one cycle's worth of data in the memory out of multiple consecutive cycles, and outputting that one cycle's worth of data multiple times when outputting. It has the same effect as above, and since analog processing is not performed on the chroma signal, there is no need to adjust the hue or level, and the manufacturing cost can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of the chroma signal storage circuit of the present invention, FIG. 2 is a block diagram of a second embodiment of the chroma signal storage circuit of the present invention, and FIG. 1 is a block diagram of a conventional example of a signal storage circuit. FIG. 1...f SO generation circuit, 2... Multiplier, 3...
2 frequency divider, 4... gate circuit, 5... A/D converter, 6... memory, 7... write/read control circuit,
8...D/A converter, 9.12.15...Switch, 10.11.13゜14...4 word shift register, 51...Color demodulation circuit, 52...Switch, 53
...A/D converter, 54...Memory, 551.55
2...D/A converter, 56...color modulation circuit, 57...
...2 frequency divider, 58... Inverter, a... Chroma signal input terminal, b... Chroma signal output terminal, C... Sampling clock input terminal.

Claims (1)

[Claims] 1. Means for generating a color subcarrier f_S_C synchronized with a color burst of an input chroma signal, and the f_S_C
means for sampling the input chroma signal at a frequency that is multiplied by n (n is an integer of 3 or more), and f_S_C m times (
(m is an integer of 2 or more) A chroma signal storage circuit comprising means for extracting n consecutive samples from the sampling series every time the count is performed, and means for repeating and outputting the consecutive n samples m times.