JPH02192207A - Fm detection circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for a bipolar capacitor by providing an integration circuit extracting a DC bias component from an output of a detection circuit and a feedback circuit feeding back the DC bias component obtained at the integration circuit to the detection circuit. CONSTITUTION:A DC bias component obtained from an integration circuit 4 extracting the DC bias component from an output of an FM detection circuit 1 is fed back negatively to the detection circuit 1 via a feedback circuit 6 and no DC bias output is generated at an FM demodulation output terminal 3. That is, the DC bias component obtained by the integration circuit 4 is given to the FM detection circuit 1 via the feedback circuit 6 to restore the DC bias output caused from the detuned FM detection circuit 1 to a reference DC level. Thus, the fluctuation of the DC component superimposed on the output of the FM detection circuit 1 due to detuning is suppressed and it is not required to insert a bipolar capacitor between stages.

Description

[Detailed Description of the Invention] C. Technical Field of the Invention] This invention relates to an improvement in an FM detection circuit used, for example, in an FM receiver, and in particular, the present invention relates to an improvement in an FM detection circuit used in, for example, an FM receiver. FM detection circuit designed to suppress fluctuations [Prior art] FM receivers generally convert a high frequency signal from an antenna into an intermediate frequency signal using a local signal, and then detect this intermediate frequency signal using an FM detection circuit. It is designed to obtain a demodulated output.

In this case, the FM detection circuit detects the FM component in the intermediate frequency signal,
That is, it has a function of converting frequency fluctuations based on 10.7 MHz into an output level.

Therefore, it is well known that when the reception frequency is in a detuned state, a phenomenon occurs in which a DC biased output based on a so-called S-curve output is superimposed on the FM demodulation output.

When a DC biased output is produced by this FM detection circuit, the operating point of the circuit connected to the subsequent stage will fluctuate due to the biased output, and even if the downstream circuit has a considerable dynamic range, it will not be possible to demodulate it. This has the disadvantage of generating distortion in the output.

To prevent such problems, a bipolar capacitor is generally inserted between the output end of the FM detection circuit and the next stage to block the biased DC output generated by the FM detection circuit.

[Problem to be solved by the invention]

However, this bipolar capacitor can also cause distortion to the demodulated output, so it is preferable to avoid using a bipolar capacitor, and even when integrating the circuit, it is possible to create a circuit that does not require a capacitor between stages. is desired.

The present invention has been made in view of the problems of the conventional FM detection circuits described above, and it is an object of the present invention to provide an FM detection circuit that does not require the insertion of a bipolar capacitor as described above.

[Means to solve the problem]

In order to solve the above problems, the FM detection circuit made according to the present invention includes an integrating circuit for extracting a DC biased component from the output of the detection circuit, and a circuit for feeding back the DC biased component obtained from this integrating circuit to the detection circuit. It is characterized in that it is equipped with a feedback circuit.

[For production]

According to the above configuration, the DC bias component obtained by the integrating circuit is brought to the FM detection circuit via the feedback circuit, and has the effect of returning the DC bias output caused by detuning the FM detection circuit to the reference DC potential. Let's do it. As a result,
The DC component superimposed on the output of the FM detection circuit is suppressed from fluctuating due to detuning, and there is no need to insert a bipolar capacitor between stages.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.
In the figure, 1 is 10°7 MH brought to input end 2
This is an FM detection circuit which receives an intermediate frequency signal of z and performs FM detection on it, and 3 is an output terminal for FM demodulation output. Reference numeral 4 denotes an integrating circuit for extracting a DC bias component from the output of the detection circuit 1, and 5 is an output terminal of this DC bias component.

The DC biased component obtained by the integrating circuit 4 is negatively fed back to the detection circuit 1 via the feedback circuit 6.
The FM demodulation output terminal 3 is configured so that no DC biased output is generated.

FIG. 2 is a wiring diagram showing more specifically the embodiment of the present invention shown in FIG.

That is, 1 is an FM detection circuit, which includes a phase comparator 11 equipped with an input terminal 2 for an intermediate frequency signal, a loop filter 12 that smoothes the output of this phase comparator 11, and an FM detection circuit that generates oscillation by the output of this loop filter 12. A so-called phase-locked loop (P L L
) has a detection configuration.

The VCO 13 has first and second transistors Ql and Qt whose emitters are commonly connected and whose respective bases are connected to mutually opposing collectors, and between the collectors of the first and second transistors Qt = Qt. A parallel resonant circuit consisting of an inductance L+ and a capacitance Ct connected to a transistor Q3 forming a variable current source connected to the emitters of the transistors Q+ and Qz, and a resistor R1 connected to the emitter of the transistor Q3
A transistor Q whose emitters are differentially connected via
4, and transistors Q, Q6 constituting a constant current source connected to the emitters of the transistors Q, Q, respectively, and the collectors of the transistors Q2 and Q4 are connected to a power source E.

A pair of output terminals of the loop filter 12 is a transistor Q3* which functions as an oscillation frequency control input terminal of the VCO.
Transistors Q, , Q are connected to each base of Q4 and also serve as the vC0130 oscillation output terminal.

Each collector end of is connected to the phase comparator 11.

Regarding the VCO13 explained above, for example,
It is disclosed in No. 257606.

On the other hand, the demodulated output from the PLL detection circuit, that is, the pair of outputs of the loop filter 12 has an emitter that is connected to the resistor R.
Transistor Q? connected through 2? , Qll. This transistor q,,q,
A transistor Q, which constitutes a constant current source, is attached to each emitter of
,Q,, are connected. The collector of transistor Q is connected to the collector of one transistor Qll of a pair of transistors Q, . The collector of is connected to the collector of one transistor QI3 of a pair of transistors Q, , Q, , Q, and S forming the second current mirror circuit.

Further, the collector of the transistor Q1□ constituting the first current mirror circuit is connected to the transistor Q, . . . Q, constituting the third current mirror circuit.

It is connected to the collector of one transistor Q4 of Q18.

The collector of the transistor QI4 forming the second current mirror circuit and the transistor Ql? forming the third current mirror circuit. The collector ends of each are connected in common, and an integrating capacitor C2 and a resistor R1 are connected to the connection point.
A reference power source E2 is connected through the reference power source E2, and this common connection point constitutes the DC biased output terminal 5 of the detection circuit 1.

Further, the collector terminals of the transistor Qts constituting the second current mirror circuit and the collector terminals of the transistor QIs constituting the third current mirror circuit are commonly connected, and a reference power source E is connected to the connection point via a resistor R4. are connected, and this common connection point constitutes the demodulation output terminal 3 of the detection circuit 1.

The DC biased output terminals 5 are connected to a differentially connected transistor Q! whose emitters are commonly connected to each other and whose emitters are connected to a transistor QI9 constituting a constant current source. . , Qt
, one transistor Q! l is connected to the base of the other transistor Q,. A comparison is made with reference power supply E4 connected to the base of .

Its collector is connected to the collector of one of the transistors Q, . . . , Q, 3 constituting the fourth current mirror circuit.

The other transistor Q! constituting the fourth current mirror circuit! The collector of □ is connected to the transistor Qt4. which constitutes the fifth current mirror circuit. Q,s,Q! Connected to the collector of one transistor Q0 of &! The collectors of the other transistors Qta y Qll are connected to the emitters of the transistors Q, , Q4 constituting vCo of the detection circuit 1.

In the above configuration, the pair of outputs of the FM detection circuit 1 is the transistor Q? - applied to each base of Qs. At this time, if the collector current of the transistor Q is I2, the current 11 is passed through the first current mirror circuit to the third transistor Q0 to Q1. Current mirror circuit 2 is reflected in a second current mirror circuit consisting of transistors Q13 to Qls.

Therefore, the output terminal 3 is provided with an FM demodulated output consisting of It It, and the output terminal 5 is provided with an output obtained by integrating the components of II and II by the capacitor C2, that is, a DC biased output from the detection circuit 1.

The DC output provided to this output terminal 5 is applied to a transistor Q21 constituting a negative feedback section 6 and compared with a reference power source E4.

The collector current I is reflected through a fourth current mirror circuit consisting of transistors Q2□ and Q2 to a fifth current mirror circuit consisting of transistors Qga to Q0.

The current I3 acts as a sink current for the emitter current of the transistor Qs = Qa that constitutes the VCO of the detection circuit 1, and changes the oscillation frequency of the VCO.

Therefore, when the DC biased output generated at the output terminal 3 due to detuning attempts to change from a predetermined value, the current 2 changes, and as a result, the oscillation frequency of the VCO changes to the center frequency (10,
7MHz).

As described above, even if the tuning is detuned with respect to the reference frequency, the DC biased output described above is negatively fed back to the detection circuit, and as a result, the DC potential at the FMul modulation output terminal 3 can be kept constant.

〔effect〕

As is clear from the above explanation, according to the present invention, the DC value at the demodulation output terminal of the FM detection circuit can always be kept constant, so there is no need to insert a bipolar capacitor as in the conventional case, making it suitable for integrated circuits. A detection circuit can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a wiring diagram showing a specific example thereof. 1...FM detection circuit, 2...Intermediate frequency signal input terminal,
3...FM demodulation output end, 4...Integrator circuit, 5...
DC bias component output terminal, 6... feedback circuit. No.

Claims (1)

[Claims] A detection circuit that receives an intermediate frequency signal and performs FM detection on the intermediate frequency signal; an integrating circuit that extracts a DC bias component from the output of this detection circuit; and a feedback circuit for feeding back to the detection circuit, and the DC value in the demodulated output from the detection circuit is
An FM detection circuit characterized by suppressing fluctuations due to detuning.