JPH02192208A - Fm detection circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for a bipolar capacitor by providing an integration circuit extracting a DC bias component from an output of a detection circuit and a feed follow circuit applying feed-follow to the DC bias component obtained at the integration circuit to an output terminal of the detection circuit. CONSTITUTION:A DC bias component obtained from an integration circuit 4 extracting the DC bias component from an output of an FM detection circuit 1 is superimposed on an output of the detection circuit 1 via a feed-follow circuit 6 and no DC bias output is generated at an FM demodulation output terminal 3. That is, the DC bias component obtained by the integration circuit 4 is given to the FM detection circuit 1 via the feed-follow circuit 6 to restore the DC bias output caused from the detuned FM detection circuit 1 to a reference DC level. Thus, the fluctuation of the DC component superimposed on the output of the FM detection circuit 1 due to detuning is suppressed and it is not required to insert a bipolar capacitor between stages.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an improvement in an FM detection circuit used in, for example, an FM receiver. FM detection circuit designed to suppress fluctuations [Prior art] FM receivers generally convert a high frequency signal from an antenna into an intermediate frequency signal using a local signal, and then detect this intermediate frequency signal using an FM detection circuit. It is designed to obtain a demodulated output.

In this case, the FM detection circuit detects the FM component in the intermediate frequency signal,
That is, it has a function of converting frequency fluctuations based on 10.7 MHz into an output level.

Therefore, when the reception frequency is in a detuned state, it is well known that a phenomenon occurs in which the DC biased output is superimposed on the FM demodulation output based on the so-called S-curve output.

When a DC biased output is produced by this FM detection circuit, the operating point of the circuit connected to the subsequent stage will fluctuate due to the biased output, and even if the downstream circuit has a considerable dynamic range, it will not be possible to demodulate it. This has the disadvantage of generating distortion in the output.

To prevent such problems, a bipolar capacitor is generally inserted between the output end of the FM detection circuit and the next stage to block the biased DC output generated by the FM detection circuit.

[Problem to be solved by the invention]

However, since this bipolar capacitor can also cause distortion to the demodulated output, it is preferable to avoid using a bipolar capacitor, and even when the circuit is integrated, it is possible to create a circuit that does not require a capacitor to be inserted between stages. is desired.

The present invention has been made in view of the problems of the conventional FM detection circuits described above, and it is an object of the present invention to provide an FM detection circuit that does not require the insertion of a bipolar capacitor as described above.

[Means to solve the problem]

In order to solve the above problems, the FM detection circuit constructed according to the present invention includes an integrating circuit that extracts a DC biased component from the output of the detection circuit, and a DC biased component obtained from the integrating circuit that is connected to a demodulation output terminal of the detection circuit. The present invention is characterized in that it is equipped with a feed follow circuit for following the feed.

[For production]

According to the above configuration, the DC bias component obtained by the integrating circuit is brought to the demodulation output terminal of the FM detection circuit by the feed follow circuit, and at the output terminal of the FM detection circuit, the DC bias component obtained by detuning the FM detection circuit is brought to the demodulation output terminal of the FM detection circuit. It acts to pull the parasitic output back to the reference DC potential. As a result, F.M.
The direct current component superimposed on the output of the detection circuit is suppressed from changing due to detuning, and there is no need to insert a bipolar capacitor between stages.

〔Example〕

Hereinafter, embodiments of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG.
This is an FM detection circuit which receives an intermediate frequency signal and performs FM detection on it, and 3 is an output terminal for FM demodulation output.

Reference numeral 4 denotes an integrating circuit for extracting a DC bias component from the output of the detection circuit 1, and 5 is an output terminal for the DC bias component.

The direct current biased component obtained by the integrating circuit 4 is superimposed on the output of the detection circuit 1 via the feed follow circuit 6, so that no direct current biased output is generated at the FM demodulation output terminal 3.

FIG. 2 is a wiring diagram showing more specifically the embodiment of the present invention shown in FIG.

In other words, 1 is an FM detection circuit which receives an intermediate frequency signal from an intermediate frequency amplifier from an input terminal 2, and this is 10.7.
This is a well-known Fordracher detector consisting of a phase shifter 11 that shifts the phase by 90 degrees in MHz, and a multiplier 12 that multiplies the output of this phase shifter 11 by an input intermediate frequency signal.

One of the pair of outputs of the Ford Lacher detector 1 is connected to a transistor Q constituting a first current mirror circuit.
+, Qt, Q3.

The other of the pair of outputs of the Ford Lacher detector 1 is connected to the collector of one transistor Q4 among the transistors Qa, Qs, and Qb constituting the second current mirror circuit.

The collector of the transistor Qt among the transistors Ql to Qz constituting the first current mirror circuit is connected to the third transistor Qt.
The transistor Qt that constitutes the current mirror circuit of
= Connected to the collector of one transistor Q among Qa, and the collector of the other transistor Qll is connected to the collector of one transistor QS among the transistors Q4 to Q constituting the second current mirror circuit. It is connected. These transistors Q8 and Q,
A reference power source E is applied to the common connection point of both collectors of
It is configured as an output terminal of FM demodulation output terminal 3.

Further, the collector of one transistor Qh among the transistors Q4 to Q6 constituting the second current mirror circuit is connected to the collector of one transistor Q of the transistors Q*@Q111 constituting the fourth current mirror circuit. It is connected.

The collector of the other transistor Q,
Transistors Q1 to Q constituting the current mirror circuit of
, one transistor Q.

are commonly connected to the collectors of , and an integrating capacitor C is connected between the connection point and the reference potential point. Both transistors Ql, Q,. The common collector terminal of constitutes the output terminal 5 of the DC bias voltage of the detection circuit 1, and the common collector terminal of the resistor R
2 via the FMy1. It is connected to the control output terminal 3.

In the above configuration, the pair of outputs of the FM detection circuit I serve as control outputs for the collector current of the transistor Q constituting the first current mirror circuit and the collector current of the transistor Q4 constituting the second current mirror circuit.

If the collector current of the transistor Q is Ill, and the collector current of the transistor Q4 is Io, the current 1 is reflected as the collector current of the transistor Q@ of the third current mirror circuit constituted by the transistors Q4-Qs. Further, the current I8 is reflected in the collector current of the transistor Q constituting the second current mirror circuit.

Therefore, output terminal 3 has 1. -I, resulting in an FM demodulated output consisting of -I.

Furthermore, the current II is copied to the collector of the transistor Q3, and the current Xt is transferred to the collector of the transistor G through a fourth current mirror circuit consisting of the transistors
It is copied to the collector of l+s.

Therefore, an output obtained by integrating the component of the current 1r Ig by the capacitor C, that is, an inverted output of the DC biased output from the detection circuit 1, is provided to the terminal 5, which is connected to the resistor R2.
It is added to the FM demodulation output at the output terminal 3 via the FM demodulation output.

Therefore, when a DC biased output is generated at the output terminal 3 due to detuning, an inverted output of the DC biased output of the same level is generated at the output terminal 5, and is applied to the terminal 3 via the resistor R2. The parasitic output is canceled and F is output from terminal 3.
The AC component in the M demodulated output is superimposed on the reference potential.

Therefore, even if the frequency is detuned from the reference frequency, the DC biased output described above is added to the FM demodulation output as a cancellation component, and as a result, the DC potential at the FM demodulation output terminal 3 can be kept constant.

〔effect〕

As is clear from the above explanation, according to the present invention, the DC value at the demodulation output terminal of the FM detection circuit can always be kept constant, so there is no need to insert a bipolar capacitor as in the conventional case, making it suitable for integrated circuits. A detection circuit can be provided.

Further, since the DC biased output is added to be canceled by the feed follow circuit, its operation is extremely stable.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a wiring diagram showing a specific example thereof. 1...FM detection circuit, 2...Intermediate frequency signal input terminal,
3...FM demodulation output end, 4...Integrator circuit, 5...
DC bias component output terminal, 6... feed follow circuit.

Claims (1)

[Claims] A detection circuit that receives an intermediate frequency signal and performs FM detection on the intermediate frequency signal; an integrating circuit that extracts a DC bias component from the output of this detection circuit; A feed follow circuit for feed following the demodulation output end of the detection circuit, and the DC value in the demodulation output from the detection circuit is suppressed from fluctuating due to detuning.
M detection circuit.