JPH02192195A - Connection structure of plural circuit boards - Google Patents
Connection structure of plural circuit boardsInfo
- Publication number
- JPH02192195A JPH02192195A JP1011023A JP1102389A JPH02192195A JP H02192195 A JPH02192195 A JP H02192195A JP 1011023 A JP1011023 A JP 1011023A JP 1102389 A JP1102389 A JP 1102389A JP H02192195 A JPH02192195 A JP H02192195A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- semiconductor device
- connection
- electrodes
- sealing cover
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000463 material Substances 0.000 claims description 7
- 238000010292 electrical insulation Methods 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 abstract description 62
- 238000007789 sealing Methods 0.000 abstract description 23
- 238000000034 method Methods 0.000 abstract description 20
- 239000000853 adhesive Substances 0.000 abstract description 10
- 238000003466 welding Methods 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 30
- 239000000758 substrate Substances 0.000 description 20
- 230000001070 adhesive effect Effects 0.000 description 8
- 229910002482 Cu–Ni Inorganic materials 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 6
- 239000000956 alloy Substances 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 230000007547 defect Effects 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- 229920005989 resin Polymers 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 230000002950 deficient Effects 0.000 description 3
- 230000005489 elastic deformation Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000007639 printing Methods 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229920002050 silicone resin Polymers 0.000 description 1
- 229920002379 silicone rubber Polymers 0.000 description 1
- 239000004945 silicone rubber Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/301—Assembling printed circuits with electric components, e.g. with resistor by means of a mounting structure
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/328—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding
Landscapes
- Multi-Conductor Connections (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
- Combinations Of Printed Boards (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、たとえば半導体素子などが形成されたL積回
路基板と、プリント基板、フレキシブル基板、ガラス基
板、あるいはセラミック基板などの回路基板とを電気的
に接続するために好適に実施される複数の回路基板の接
続構造に関する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides electrical connection between an L-product circuit board on which semiconductor elements are formed, and a circuit board such as a printed circuit board, a flexible board, a glass substrate, or a ceramic board. The present invention relates to a connection structure for a plurality of circuit boards that is suitably implemented for connection to a plurality of circuit boards.
従来の技術
近年、I C(Int+4rated C1rcuit
)なとの半導体集積回路基板の集積度の増加に伴って入
出力端子数も増大する傾向にある。これを受けて従来性
われていたような、半導水基板の入出力端子を配線基板
の電極に、金やアルミニウムなとの導線を用いて電気的
に接続するワイヤボンディング方式に変わって、半導体
基板上の入出力端子に突起状の電極を設けて配線基板上
の電極に一括して接続するフリップチップ方式が行われ
ている。Conventional technology In recent years, IC (Int+4rated C1rcuit
) As the degree of integration of semiconductor integrated circuit boards increases, the number of input/output terminals also tends to increase. In response to this, the conventional wire bonding method, in which the input/output terminals of a semiconducting water board are electrically connected to the electrodes of a wiring board using conductive wires such as gold or aluminum, is being used. A flip-chip method is used in which protruding electrodes are provided on the upper input/output terminals and connected all at once to electrodes on the wiring board.
このフリップチップ方式によって、電極の接続を半田付
けではなく圧接によって行うことは、次の(a)〜(c
)などの利点を有する。With this flip-chip method, the electrodes are connected by pressure welding rather than soldering, as shown in the following (a) to (c).
) and other advantages.
(a)接続時において半導体基板と回路基板とを加熱す
る必要がないので、半導体基板および回路基板を熱によ
って損傷することがない。(a) Since there is no need to heat the semiconductor substrate and the circuit board during connection, the semiconductor substrate and the circuit board are not damaged by heat.
(b)半田付けによる接続を行わないので、回路基板の
電極月利が親半田金属材料に限定されな(c)半導体基
板は回路基板に対して圧接によって固定されるだけであ
るがら、接続後に半導体基板の回路素子に不良が生じた
場合の半導体基板の交換が容易に可能である。(b) Since the connection is not made by soldering, the electrode monthly rate of the circuit board is not limited to the parent solder metal material. (c) Although the semiconductor board is only fixed to the circuit board by pressure welding, after the connection The semiconductor substrate can be easily replaced when a defect occurs in a circuit element of the semiconductor substrate.
このような利点から、導電性コネクタを介して圧接する
方法、金属材料がち形成した突起電極を圧接する方法な
と、近年、様々な方法が提案されている。Due to these advantages, various methods have been proposed in recent years, such as a method of press-contacting via a conductive connector and a method of press-contacting a protruding electrode formed of a metal material.
たとえば特開昭61−242041.特開昭61−25
9548.特開昭63−150930においては、弾性
を有する導電性の突起電極を回路基板上に形成する方法
が開示されている。このような弾性および導電性を有す
る突起電極を用いることによって、接続部に前記導電性
コネクタなどの中間介在物を介在させる必要がない。さ
らに突起電極自体が弾性を有するので、突起電極が有す
る高さの不揃いや接続される回路基板の「うねり」など
を圧接時にこの弾性によって吸収させることができる。For example, JP-A-61-242041. Japanese Unexamined Patent Publication No. 61-25
9548. JP-A-63-150930 discloses a method for forming elastic, conductive protruding electrodes on a circuit board. By using such a protruding electrode having elasticity and conductivity, there is no need to provide an intermediate object such as the conductive connector at the connection portion. Further, since the protruding electrodes themselves have elasticity, irregularities in height of the protruding electrodes and "undulations" of the circuit board to be connected can be absorbed by this elasticity during pressure contact.
発明が解決しようとする課題
上述の方法においては全て、スクリーン印刷などの印刷
法や、回路基板上に形成する突起電極の位置に対応して
透孔が形成されたマスク板を介した光照射によって、回
路基板上に予め役作された導電性インクを選択的に硬化
させる方法で突起電極を形成している。印刷法やマスク
板を用いたフォトリソグラフィ法ては、微小なピッチ幅
を有する電極に対応して微小な突起電極を形成すること
は困難である。したがって微小ピッチ幅を有する電極間
を相互に接続することができないという問題点があった
。Problems to be Solved by the Invention All of the above-mentioned methods employ printing methods such as screen printing or light irradiation through a mask plate in which through-holes are formed corresponding to the positions of protruding electrodes to be formed on the circuit board. In this method, protruding electrodes are formed by selectively curing conductive ink that has been applied in advance on a circuit board. With a printing method or a photolithography method using a mask plate, it is difficult to form minute protruding electrodes corresponding to electrodes having a minute pitch width. Therefore, there was a problem that electrodes having a minute pitch width could not be connected to each other.
本発明の目的は、上記した問題点を解決して微細ピッチ
幅を有する電極間を相互に接続することがてきるように
した複数の回路基板の接続構造を提供することである。SUMMARY OF THE INVENTION An object of the present invention is to provide a connection structure for a plurality of circuit boards, which solves the above-mentioned problems and allows interconnection of electrodes having fine pitch widths.
課題を解決するための手段
本発明は、少なくとも一方表面に回路配線が形成された
基材と、前記回路配線に接続領域て電気的に接続され、
残余の領域て上記基材から弾性および電気絶縁性を有す
る介在体を介在して離間した接続用電極とを含む第1回
路基板と、第1回路基板上の接続用電極の前記残余の領
域と対応する位置に接続用電極が形成された第2回路基
板とを含み、
第2回路基板の接続用電極に第1回路基板の接続用電極
の上記残余の領域を対向させて、これらを圧接した状態
て固定するようにしたことを特徴とする複数の回路基板
の接続構造である。Means for Solving the Problems The present invention provides a base material having circuit wiring formed on at least one surface thereof, and electrically connected to the circuit wiring at a connection region,
a first circuit board including a connection electrode whose remaining region is spaced from the base material with an intervening body having elasticity and electrical insulation properties; and the remaining region of the connection electrode on the first circuit board. and a second circuit board on which connection electrodes are formed at corresponding positions, and the remaining areas of the connection electrodes of the first circuit board are opposed to the connection electrodes of the second circuit board, and these are pressed together. This is a connection structure for a plurality of circuit boards, characterized in that the circuit boards are fixed in a fixed state.
作 用
本発明においては、第1回路基板の基材の少なくとも一
方表面に回路配線が形成され、この回路配線に接続用電
極の接続領域が電気的に接続される。また接続用電極の
残余の領域は、前記基材に弾性および電気絶縁性を有す
る介在体を介在して離間して設りられる。また第2回路
基板には、第1回路基板上の接続用電極の前記残余の領
域と対応する位置に接続用電極が形成される。このよう
な構成を有する第1回路基板の接続用電極の上記残余の
領域は、第2回路基板の接続用電極に対向され、これら
第1および第2回路基板は相互に圧接した状態で固定さ
れる。Function In the present invention, circuit wiring is formed on at least one surface of the base material of the first circuit board, and the connection region of the connection electrode is electrically connected to the circuit wiring. Further, the remaining regions of the connection electrodes are provided at a distance from the base material with an intervening body having elasticity and electrical insulation properties interposed therebetween. Further, a connection electrode is formed on the second circuit board at a position corresponding to the remaining area of the connection electrode on the first circuit board. The remaining region of the connection electrode of the first circuit board having such a configuration is opposed to the connection electrode of the second circuit board, and the first and second circuit boards are fixed in pressure contact with each other. Ru.
したがって本発明によれば、第1回路基板上に前記介在
体を介在して接続用電極を微細ピッチで形成することが
可能である。また第1および第2回路基板の各接続用電
極の高さの不揃いや回路基板の「うねり」などは、圧接
時の介在体の弾性変形によって吸収され、安定した均一
な接続構造を得ることができる。また第1および第2回
路基板の少なくとも一方の回路基板に実装された電子部
品に不良が発生した場合などにおいては、容易に他方の
回路基板から一方の回路基板を取去って、不良のない新
たな回路基板と交換することがてきる。Therefore, according to the present invention, it is possible to form connection electrodes at a fine pitch on the first circuit board with the intervening body interposed therebetween. In addition, irregularities in the heights of the connection electrodes of the first and second circuit boards and "waviness" of the circuit board are absorbed by the elastic deformation of the intervening body during pressure welding, making it possible to obtain a stable and uniform connection structure. can. In addition, in the event that a defect occurs in an electronic component mounted on at least one of the first and second circuit boards, one circuit board can be easily removed from the other circuit board and a new, non-defective circuit board can be easily removed. You can replace it with a new circuit board.
実施例
第1図は、本発明に従う第1回路基板である半導体装置
1の斜視図である。半導体装置lは、続述される回路配
線が形成された基材である基板2上に、前記回路配線の
接続領域で電気的に接続さぺ
れた接続用電極3が、基板2上に弾性および電気絶縁性
を有する介在体4を介在して離間した状態て後述される
方法に従って形成されている。Embodiment FIG. 1 is a perspective view of a semiconductor device 1, which is a first circuit board according to the present invention. In the semiconductor device 1, on a substrate 2, which is a base material on which circuit wiring, which will be described later, is formed, a connecting electrode 3, which is electrically connected in a connection area of the circuit wiring, is provided on the substrate 2 with elastic and They are formed in a spaced-apart manner with an intervening body 4 having electrical insulation properties interposed therebetween, according to a method described later.
第2図は、半導体装置1が第2回路基板である回路基板
5に実装された状態を示す斜視図である。FIG. 2 is a perspective view showing a state in which the semiconductor device 1 is mounted on a circuit board 5, which is a second circuit board.
第2図においては、半導体装置1の実装状態を明示する
ために半導体装置1および封止用カバ一体6の図面手前
を破断して示す。回路基板5上には、半導体装置1の接
続用電極3と対応する位置に接続用電極7が形成されて
いる。したがってこの回路基板5の各接続用電極7に半
導体装置1の対応する各接続用電極3が対向し、これら
半導体装置1および回路基板5は圧接状態で固定されて
いる。In FIG. 2, the front side of the drawing of the semiconductor device 1 and the sealing cover unit 6 is cut away to clearly show the mounting state of the semiconductor device 1. A connection electrode 7 is formed on the circuit board 5 at a position corresponding to the connection electrode 3 of the semiconductor device 1 . Therefore, each connection electrode 3 of the semiconductor device 1 is opposed to each connection electrode 7 of the circuit board 5, and the semiconductor device 1 and the circuit board 5 are fixed in a press-contact state.
封止用カバ一体6の上面には凹部6aが形成されており
、半導体装置1はこの封止用カバ一体6の凹部6aによ
って回路基板5側に押圧されて圧接されている。A recess 6a is formed in the upper surface of the sealing cover 6, and the semiconductor device 1 is pressed against the circuit board 5 by the recess 6a of the sealing cover 6.
第3図は第1図の切断面線l11−Iから見た断面図で
あり、第4図は第3図の一部拡大断面図である。半導体
装置1の基板2は、シリコンあるいはガリウムヒ素など
のウェハ上に拡散層が形成され、これによって多数のト
ランジスタや夕゛イオードなどが形成された半導体集積
回路を構成している。FIG. 3 is a sectional view taken along the section line l11-I in FIG. 1, and FIG. 4 is a partially enlarged sectional view of FIG. The substrate 2 of the semiconductor device 1 has a diffusion layer formed on a wafer of silicon or gallium arsenide, and constitutes a semiconductor integrated circuit in which a large number of transistors, diodes, etc. are formed.
半導体装置1は、基板2の最上層に電極8が形成され、
この電極8の接続用電極3か形成される接続領域以外の
部分には、たとえばSiN、SiO2、PSG(ガラス
)、あるいはポリイミドなどからなる表面保護層9が被
覆されている。また基板2の被覆された表面保護N9の
周縁部には、弾性および電気絶縁性を有する介在体4が
所定の厚み11で形成されている。この介在体4および
表面保護層9から表出した電極8表面には、接続用電極
3が後述の方法によって、たとえば第1図および第4図
などに示される形状て形成されている。In the semiconductor device 1, an electrode 8 is formed on the top layer of a substrate 2,
A portion of the electrode 8 other than the connection region where the connection electrode 3 is formed is coated with a surface protection layer 9 made of, for example, SiN, SiO2, PSG (glass), or polyimide. Further, an elastic and electrically insulating intervening body 4 having a predetermined thickness 11 is formed at the peripheral edge of the surface protection N9 that the substrate 2 is coated with. On the surface of the electrode 8 exposed from the intervening body 4 and the surface protection layer 9, a connecting electrode 3 is formed in the shape shown in, for example, FIGS. 1 and 4 by a method described later.
介在体4としては、硬化後弾性体となる電気絶縁性樹脂
、たとえばシリコーン系樹脂、ポリイミド系樹脂などが
用いられる。また接続用電極3としては、たとえばA1
、Ti、C(1−N16金、Auなどからなる多層構造
を有する金属膜によって構成される。As the intervening body 4, an electrically insulating resin that becomes an elastic body after hardening, such as silicone resin or polyimide resin, is used. Further, as the connection electrode 3, for example, A1
, Ti, C (1-N16 gold, Au, etc.).
介在体4は、半導体装置1の基板2上に予め光硬化性樹
脂をたとえばスピンコードあるいはロールコートなどの
方法によって一様に塗布する。この塗布された光硬化性
樹脂を、第1図に示されるように基板2上の周縁部のみ
が硬化されるように選択的に透孔が形成されたマスク板
を介して紫外線を照射する。これによって基板2上の周
縁部のみが硬化され、周縁部によって囲まれる領域は未
硬化の状態とされる。この未硬化の領域を、現像液を用
いてエツチングすることによって、たとえば11=10
〜20μmの厚さを有する所定の形状の介在体4として
形成することができる。The intervening body 4 is formed by uniformly applying a photocurable resin onto the substrate 2 of the semiconductor device 1 in advance by, for example, a method such as spin cord or roll coating. The applied photocurable resin is irradiated with ultraviolet rays through a mask plate in which through holes are selectively formed so that only the peripheral portion of the substrate 2 is cured, as shown in FIG. As a result, only the peripheral portion on the substrate 2 is cured, and the area surrounded by the peripheral portion is left uncured. By etching this uncured area using a developer, for example, 11=10
It can be formed as an intervening body 4 having a predetermined shape and having a thickness of ~20 μm.
この介在体4の厚み11が10〜20μmよりも薄い場
き、たとえば11−1〜3μrn程度では、半導体装置
1が回路基板5上に実装される際に電極37が有する凹
凸を介在体4によって吸収することができず、したがっ
て半導体装置1と回路基板5との密着性が悪くなってし
まう。また11が厚い場き、たとえば11=50μm程
度では、光硬化性樹脂からなる介在体4を紫外線などに
よって選択的に硬化する際にその境界部分が不鮮明とな
り、したがってパターン形成の精度が低下してしまう。When the thickness 11 of the intervening body 4 is thinner than 10 to 20 μm, for example, about 11-1 to 3 μrn, the intervening body 4 can eliminate the unevenness of the electrode 37 when the semiconductor device 1 is mounted on the circuit board 5. Therefore, the adhesion between the semiconductor device 1 and the circuit board 5 deteriorates. In addition, when 11 is thick, for example, when 11 = 50 μm, the boundary portion becomes unclear when the intervening body 4 made of photocurable resin is selectively cured by ultraviolet rays, etc., and the accuracy of pattern formation decreases. Put it away.
半導体装置1の基板2上には、上述した介在体4の形成
が行われた後に接続用電極3の形成が行われる。接続用
電極3は、たとえばA1.Ti、Cu−Ni合金、Au
からなる多層i造を有する金属膜によって形成される。On the substrate 2 of the semiconductor device 1, the connection electrode 3 is formed after the above-mentioned intervening body 4 is formed. The connection electrode 3 is, for example, A1. Ti, Cu-Ni alloy, Au
It is formed of a metal film having a multilayer structure consisting of:
このうちA1層、Ti層、Cu−Ni会金層などは、半
導体装置1の基板2上に、予めたとえば蒸着法やスパッ
タリング法などの薄膜形成技術を用いて所定の厚さに一
様に形成する。次に、これらの金属層上に、たとえばス
ピンコードなどの方法によってフォトレジスト層を形成
し、所定の温度でプリベークした後、接続用電極3を形
成したい部分のみ選択的にパターン形成したマスク板を
用いてフォトレジスト層を露光し、所定の現像液を用い
てフォトレジストパターンを形成する。次に、この7オ
トレジストパターンをマスクとして各金属層を順次エツ
チングし、フォトレジスト層を剥離することによって所
定の金属層パターンを形成する。さらにこれら金属層の
最上部には、A L1層がたとえば無電解めっきによっ
て形成される。Among these, the A1 layer, the Ti layer, the Cu-Ni alloy layer, etc. are uniformly formed to a predetermined thickness on the substrate 2 of the semiconductor device 1 using a thin film forming technique such as vapor deposition or sputtering. do. Next, a photoresist layer is formed on these metal layers by, for example, a method such as a spin code, and after prebaking at a predetermined temperature, a mask plate is formed which is selectively patterned only in the portion where the connection electrode 3 is to be formed. A photoresist layer is exposed using a photoresist, and a photoresist pattern is formed using a predetermined developer. Next, each metal layer is sequentially etched using the seven photoresist patterns as a mask, and the photoresist layer is peeled off to form a predetermined metal layer pattern. Further, on top of these metal layers, an A L1 layer is formed, for example, by electroless plating.
上記A1層は、層厚1000 rr m程度に形成する
ことが好ましく、基板2上に形成されているAI電極8
との密着性の観点からAlが用いられる。このA1層上
に形成されるTi層は、層厚300 rr m程度が好
ましく、耐食性およびA1層の酸化防止用として積層す
る。またCu−Ni合金層は、3 Q Q nm程度が
好ましく、後述されるAU層との密着性の観点からCu
が用いられる。しかしCuだけでは酸化し易いために、
NiとのCu−Ni合金として用いる。このようにA1
層、Ti層、Cu−Ni合金層が形成された上には、さ
らに全体の酸化防止用としてAu層が、好ましくは10
00 ri rn程度の厚みで形成される。The above A1 layer is preferably formed to have a layer thickness of about 1000 rr m, and is similar to the AI electrode 8 formed on the substrate 2.
Al is used from the viewpoint of adhesion to. The Ti layer formed on this A1 layer preferably has a layer thickness of about 300 rr m, and is laminated for corrosion resistance and oxidation prevention of the A1 layer. Further, the Cu-Ni alloy layer preferably has a thickness of about 3 Q Q nm, and from the viewpoint of adhesion with the AU layer described later, Cu
is used. However, since Cu alone is easily oxidized,
Used as a Cu-Ni alloy with Ni. Like this A1
On top of the Ti layer, the Cu-Ni alloy layer and the Ti layer, an Au layer is further formed to prevent oxidation of the whole.
It is formed with a thickness of about 00 ri rn.
第5図は上述のようにして接続用電極3が形成された半
導体装置1を回路基板5に封止用カバー体6を用いて実
装する工程を示す断面図であり、第6図は半導体装置1
が回路基板5上に実装された状態を示す断面図である。FIG. 5 is a sectional view showing the process of mounting the semiconductor device 1 on which the connection electrode 3 is formed as described above on the circuit board 5 using the sealing cover body 6, and FIG. 1
FIG. 3 is a cross-sectional view showing a state in which is mounted on a circuit board 5. FIG.
したがって第6図は、第2図の切断面線Vl−Vlから
見た断面図である。Therefore, FIG. 6 is a sectional view taken along the section line Vl--Vl in FIG. 2.
予め介在体4が介在されて接続用電極3が形成された半
導体装置1は、その接続用電極3が形成された面とは反
対面が封止用カバ一体6の四部6aの裏面である凸部6
bに、たとえば常温硬化性の接着剤10を用いて接着さ
れる。この状態で、封止用カバ一体6に接合された半導
体装置1の接続用電極3の高さ114を、封止用カバ一
体6の高さh2よりも大きくなるように設定する。The semiconductor device 1 in which the connection electrode 3 is formed with the intervening body 4 interposed in advance has a convex surface whose opposite surface to the surface on which the connection electrode 3 is formed is the back surface of the four parts 6a of the sealing cover integral 6. Part 6
b using, for example, an adhesive 10 that hardens at room temperature. In this state, the height 114 of the connection electrode 3 of the semiconductor device 1 joined to the sealing cover unit 6 is set to be greater than the height h2 of the sealing cover unit 6.
半導体装置1および封止用カバ一体6は、半導体装置1
の接続用電極3が接続される回路基板5の接続用電極7
と対向され、相互に位置合わぜされた状態で矢符P方向
に圧接される。この圧接状態で、封止用カバ一体6と回
路基板5との間には接ぎ用の光硬化性接着剤11が注入
され、紫外線照射などを行って硬化さゼて半導体装置1
および封止用カバ一体6を回路基板5上に実装する。こ
の状態で、半導体装置1は、その接続用電極3が回路基
板5の接続用電極7に封止用カバ一体6によって圧接さ
れて電気的に接続される。したがって封止後の封止用カ
バ一体6の回路基板5に対する高さh 3は、第5図に
示した高さh2より大きく、また高さh 4よりも小さ
い次式の範囲に設定される。The semiconductor device 1 and the sealing cover integrated 6 are
The connection electrode 7 of the circuit board 5 to which the connection electrode 3 of the circuit board 5 is connected.
and are pressed together in the direction of arrow P in a mutually aligned state. In this pressurized state, a photocurable adhesive 11 for bonding is injected between the sealing cover unit 6 and the circuit board 5, and is cured by irradiation with ultraviolet rays, etc., and then the semiconductor device 1
Then, the sealing cover unit 6 is mounted on the circuit board 5. In this state, the connection electrode 3 of the semiconductor device 1 is pressed against the connection electrode 7 of the circuit board 5 by the sealing cover unit 6, and is electrically connected. Therefore, the height h3 of the sealing cover unit 6 relative to the circuit board 5 after sealing is set within the range of the following formula, which is larger than the height h2 shown in FIG. 5 and smaller than the height h4. .
h 2 こh 3 < h 4 ・・
・(1)第1式の状態で、半導体装置1の介在体4は弾
性変形した状態にある。これによって半導体装置1や回
路基板5の接続用電極3,7の高さの不揃い、あるいは
回路基板5が有する「うねり」などといった不均一さを
吸収することができ、半導体装置1と回路基板5の各接
続用電極3.7の電気的接続を安定した均一な状態とす
ることができる。h 2 h 3 < h 4 ・・
- (1) In the state of the first equation, the intervening body 4 of the semiconductor device 1 is in an elastically deformed state. As a result, it is possible to absorb unevenness such as unevenness in the heights of the connection electrodes 3 and 7 of the semiconductor device 1 and the circuit board 5, or "undulations" of the circuit board 5, and The electrical connection of each connection electrode 3.7 can be made stable and uniform.
また半導体装置1に不良が発生した場合には、半導体装
置1は回路基板5上に単に圧接されているだけであるか
ら、容易に回路基板5から不良となった半導体装置1を
取去って、不良のない新たな半導体装置1と交換するこ
とができる。Furthermore, if a defect occurs in the semiconductor device 1, since the semiconductor device 1 is simply pressed onto the circuit board 5, the defective semiconductor device 1 can be easily removed from the circuit board 5. The semiconductor device 1 can be replaced with a new semiconductor device 1 without any defects.
第7図は本発明の他の実施例である半導体装置12の斜
視図てあり、第8図は第7図の切断面線■−■から見た
断面図であり、第9図は第8図の一部を詳細に示すため
の拡大断面図である。なお第1図〜第6図に示した実施
例と対応する部分については同一の参照符号を用いる。FIG. 7 is a perspective view of a semiconductor device 12 which is another embodiment of the present invention, FIG. 8 is a sectional view taken along the section line ■-■ in FIG. FIG. 3 is an enlarged sectional view for showing a part of the figure in detail. Note that the same reference numerals are used for parts corresponding to the embodiments shown in FIGS. 1 to 6.
半導体装置12の基板2上には予め電極8が形成されて
おり、この電極8の接続領域以外の部分には表面保護層
9が形成されている。さらに表面保護層9上には、第7
図および第8図に示される形状で基板2上の周縁部に介
在体4が形成されている。介在体4は、層厚11=10
〜20μrl’lに設定される。この介在体4を介在し
て、第9図に示される形状で、その断面が略し字状に接
続用電極13が形成されている。この接続用電極13は
、第4図に示した接続用電極3と同様に、たとえばAI
、Ti、Cu−Ni合金、Auなどからなる多層構造を
有する金属薄膜によって形成される。An electrode 8 is formed in advance on the substrate 2 of the semiconductor device 12, and a surface protection layer 9 is formed on a portion other than the connection area of the electrode 8. Further, on the surface protection layer 9, a seventh
An intervening body 4 is formed at the peripheral edge of the substrate 2 in the shape shown in FIG. 8 and FIG. The intervening body 4 has a layer thickness 11=10
~20μrl'l. A connecting electrode 13 is formed with the intervening body 4 interposed in the shape shown in FIG. 9 and having an abbreviated cross section. This connection electrode 13 is similar to the connection electrode 3 shown in FIG.
It is formed of a metal thin film having a multilayer structure made of , Ti, Cu-Ni alloy, Au, or the like.
第7図に示されるような形状で接続用電極13を半導体
装置12の基板2上に形成することによって、第1図に
示した半導体装置1と比較して、その接続用電極13の
面積を縮小化することが可能である。したがって半導体
装置12の実装面積もまた縮小化される。By forming the connection electrode 13 in the shape shown in FIG. 7 on the substrate 2 of the semiconductor device 12, the area of the connection electrode 13 can be reduced compared to the semiconductor device 1 shown in FIG. It is possible to downsize. Therefore, the mounting area of the semiconductor device 12 is also reduced.
第10図は、第7図に示した半導体装置12が封止用カ
バ一体14を用いて回路基板5上に実装された構造を示
す断面図である。封止用カバ一体14の凹所には、予め
常温硬化性の接着剤16を用いてたとえばシリコーンゴ
ムなどの弾性部材15が接着されている。この弾性部材
15に対して、半導体装置12の接続用電極13が形成
された面とは反対面を接着剤17を介して貼り合わせる
。FIG. 10 is a sectional view showing a structure in which the semiconductor device 12 shown in FIG. 7 is mounted on the circuit board 5 using the sealing cover unit 14. An elastic member 15, such as silicone rubber, is bonded in advance to the recess of the sealing cover unit 14 using an adhesive 16 that hardens at room temperature. The surface of the semiconductor device 12 opposite to the surface on which the connection electrode 13 is formed is bonded to the elastic member 15 via an adhesive 17.
このようにして封止用カバ一体14に接合された半導体
装置12は、その各接続用電極13が回路基板5の接続
用電極7と相互に位置6わせされた―
状態て圧接される。この圧接状態で、封止用カバ一体1
4と回路基板5との間に光硬化性接着剤11が注入され
、この光硬化性接着剤11の紫外線照射などによる硬化
によって半導体装置12は回路基板5上に実装される。The semiconductor device 12 bonded to the sealing cover unit 14 in this manner is pressed into contact with the connection electrodes 13 of the semiconductor device 12 in such a manner that they are aligned with the connection electrodes 7 of the circuit board 5 . In this pressure-welded state, the sealing cover 1
A photocurable adhesive 11 is injected between the photocurable adhesive 4 and the circuit board 5, and the semiconductor device 12 is mounted on the circuit board 5 by curing the photocurable adhesive 11 by irradiating ultraviolet rays or the like.
本実施例ては、半導体装置12の接続用電極13が有す
る高さの不揃いや回路基板5が有する[うねり」などを
、半導体装置12が回路基板5に圧接されることによっ
て、介在体4および弾性部材15の弾性変形によって吸
収させることができる。したがって半導体装置12の接
続用電極13と回路基板5の接続用電極7とは、さらに
安定した均一な状態で電気的に接続されることになる。In this embodiment, uneven heights of the connection electrodes 13 of the semiconductor device 12 and undulations of the circuit board 5 are eliminated by the semiconductor device 12 being pressed against the circuit board 5, and thereby the intervening body 4 and This can be absorbed by elastic deformation of the elastic member 15. Therefore, the connection electrode 13 of the semiconductor device 12 and the connection electrode 7 of the circuit board 5 are electrically connected in a more stable and uniform state.
上述した半導体装置1.12に関する2つの実施例にお
いては、形成される接続用電極3.13や圧接時に用い
る封止用カバ一体6,14の形状などが相互に異なるも
のを例示した。しかし本発明は、そのような各部材のい
かなる組合せも含むものであり、かつ、そのような各部
材の組合ぜや形状に限定されるものでもない。In the two embodiments related to the semiconductor device 1.12 described above, the shapes of the connecting electrodes 3.13 formed and the integral sealing covers 6, 14 used during pressure bonding are different from each other. However, the present invention includes any combination of such members, and is not limited to such combinations or shapes of each member.
発明の詳細
な説明したように本発明に従えば、第1回路基板上に介
在体を介在して接続用電極を微細ピッチ幅で形成するこ
とが可能となる。この第1回路基板が、予め接続用電極
が形成された第2回路基板に対して圧接した状態で固定
されることによって、第1および第2回路基板に形成さ
れた接続用電極が有する高さの不揃いや回路基板が有す
る「うねり」などを介在体の弾性変形によって吸収させ
ることができ、第1および第2回路基板は相互に安定し
た均一な状態で各接続用電極が接続される。また第1お
よび第2回路基板は、相互に圧接した状態て固定されて
いるだけであるから、たとえば第1回路基板に実装され
た電子部品に不良が発生した場合には、容易に第1回路
基板を第2回路基板から取去って、不良のない新たな第
1回路基板と交換することができる。As described in detail, according to the present invention, connection electrodes can be formed on the first circuit board with an intervening body at a fine pitch width. By fixing the first circuit board in pressure contact with the second circuit board on which connection electrodes are formed in advance, the height of the connection electrodes formed on the first and second circuit boards increases. It is possible to absorb irregularities in the circuit board and "waviness" of the circuit board by elastic deformation of the intervening body, and the connection electrodes of the first and second circuit boards are connected to each other in a stable and uniform state. Furthermore, since the first and second circuit boards are only fixed in pressure contact with each other, for example, if a defect occurs in an electronic component mounted on the first circuit board, it is easy to damage the first circuit board. The board can be removed from the second circuit board and replaced with a new, non-defective first circuit board.
第1図は本発明の一実施例である半導体装置1の斜視図
、第2図は半導体装置1の回路基板5への実装状態を示
す斜視図、第3図は第1図の切断面線■−■から見た断
面図、第4図は第3図の一部拡大断面図、第5図は半導
体装置1の回路基板5/\の実装工程を説明する断面図
、第6図は半導体装置1の実装状態を示す断面図、第7
図は本発明の他の実施例である半導体装置12の斜視図
、第8図は第7図の切断面線■−■がら見た断面図、第
9図は第8図の一部拡大断面図、第10図は半導体装置
12の回路基板5への実装状態を示す断面図である。
1.12・・半導体装置、2・・基板、3.7.13・
・・接続用電極、4・・・介在体、5・・回路基板、6
14・・・封止用カバ一体、8・・・電極、9・・・表
面保護層、10.11,16.17・・・接着剤、15
・・・弾性部材、P・・・圧接方向
代理人 弁理士 西教 圭一部FIG. 1 is a perspective view of a semiconductor device 1 which is an embodiment of the present invention, FIG. 2 is a perspective view showing a state in which the semiconductor device 1 is mounted on a circuit board 5, and FIG. 3 is a cross-section line of FIG. 1. 4 is a partially enlarged sectional view of FIG. 3, FIG. 5 is a sectional view explaining the mounting process of the circuit board 5/\ of the semiconductor device 1, and FIG. 6 is a semiconductor 7th cross-sectional view showing the mounting state of the device 1
The figure is a perspective view of a semiconductor device 12 which is another embodiment of the present invention, FIG. 8 is a cross-sectional view taken along the cutting plane line ■--■ in FIG. 7, and FIG. 9 is a partially enlarged cross-section of FIG. 10 are cross-sectional views showing how the semiconductor device 12 is mounted on the circuit board 5. As shown in FIG. 1.12...Semiconductor device, 2...Substrate, 3.7.13...
...Connection electrode, 4...Intermediate body, 5...Circuit board, 6
14... Sealing cover integrated, 8... Electrode, 9... Surface protective layer, 10.11, 16.17... Adhesive, 15
...Elastic member, P...Press contact direction agent Patent attorney Keiichi Nishikyo
Claims (1)
記回路配線に接続領域で電気的に接続され、残余の領域
で上記基材から弾性および電気絶縁性を有する介在体を
介在して離間した接続用電極とを含む第1回路基板と、 第1回路基板上の接続用電極の前記残余の領域と対応す
る位置に接続用電極が形成された第2回路基板とを含み
、 第2回路基板の接続用電極に第1回路基板の接続用電極
の上記残余の領域を対向させて、これらを圧接した状態
で固定するようにしたことを特徴とする複数の回路基板
の接続構造。[Scope of Claims] A base material having circuit wiring formed on at least one surface thereof, and an intervening body electrically connected to the circuit wiring in a connection region and having elasticity and electrical insulation properties from the base material in the remaining region. a first circuit board including connection electrodes spaced apart from each other; and a second circuit board on which the connection electrodes are formed at positions corresponding to the remaining areas of the connection electrodes on the first circuit board. The remaining areas of the connection electrodes of the first circuit board face the connection electrodes of the second circuit board, and are fixed in a press-contact state. Connection structure.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1011023A JPH02192195A (en) | 1989-01-19 | 1989-01-19 | Connection structure of plural circuit boards |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1011023A JPH02192195A (en) | 1989-01-19 | 1989-01-19 | Connection structure of plural circuit boards |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02192195A true JPH02192195A (en) | 1990-07-27 |
Family
ID=11766508
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1011023A Pending JPH02192195A (en) | 1989-01-19 | 1989-01-19 | Connection structure of plural circuit boards |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02192195A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100762208B1 (en) * | 2000-10-20 | 2007-10-01 | 마쯔시다덴기산교 가부시키가이샤 | Semiconductor device and its manufacturing method and mounting method of semiconductor device |
US7446423B2 (en) | 2002-04-17 | 2008-11-04 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for assembling the same |
-
1989
- 1989-01-19 JP JP1011023A patent/JPH02192195A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100762208B1 (en) * | 2000-10-20 | 2007-10-01 | 마쯔시다덴기산교 가부시키가이샤 | Semiconductor device and its manufacturing method and mounting method of semiconductor device |
US7446423B2 (en) | 2002-04-17 | 2008-11-04 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for assembling the same |
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