JPH02187875A - Picture processor - Google Patents

Abstract

PURPOSE:To eliminate the need for a software processing and to shorten processing time by simultaneously obtaining either vertical directional moment or horizontal directional moment by performing a pipeline operation once at every object picture existing in a picture memory and having different density. CONSTITUTION:When picture data is transferred from a computing element 3 synchronously with a clock 24, the data is delayed by a 1.5 clock in a delay circuit 4, and a data switching circuit 7 outputs the data before the delay to a result memory 8 as an address while the clock 24 is L, and the circuit 7 outputs the data after the delay to the memory 8 as the address while the clock 24 is H. When the consecutively inputted data are different from each other, since a memory control circuit 6 reads out the content of the result memory 8 and inputs the read out content to an addition switching circuit 10 when the clock 24 is L, the output of a coincidence detecting circuit 5 is inputted to an adding circuit 11 and added with the output of a counter 9. When the clock 24 is H, the output of the adding circuit 11 is rewritten.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device applied to a moment calculation circuit, etc. in a vehicle number recognition device of a road toll machine.

[Conventional technology]

In image processing ζ such as number recognition, the area, perimeter, center of gravity, circumscribed rectangle, etc. are used as feature quantities representing the target image 25 whose density is D in the image memory 2 as shown in FIG. There is.

To find the center of gravity, you must find the moments in the vertical and lateral directions and divide them by the area.

Here, the moment in the vertical (horizontal) direction is the sum of the products of the coordinate y (x) in the vertical (horizontal) direction and the number N (M) of density particles existing on that coordinate Σ(Y-N) ( Σ(x-M))
It is calculated as

FIG. 4 is a diagram showing an example of a pipeline calculation type image processing device in the prior art.

In FIG. 4, the image captured by camera I2 is
It is converted into a digital signal by the A/D converter I3 and written into the image memory 2.

The image data written in the image memory 2 is sequentially read out according to instructions from the computer 1, subjected to various image processing by the arithmetic unit 3, and then written to the image memory 2 again.

The processed image is converted into an analog video signal by the D/A converter 15 and displayed on the monitor television 14.

Here, the computer 1 controls the device and performs processing that cannot be performed by the arithmetic unit 3.

When calculating the above-mentioned moment with the above-mentioned pipeline calculation type image processing device, conventionally, as shown in Fig. 5,
Run length conversion of the image was performed using a run length conversion circuit.

Here, run length conversion means reading out the data in the image memory 2 in the horizontal direction and converting the target image 2 for each row as shown in FIG.
This means converting the coordinates of the starting point of the area of 5 (density D) and its length l. In Figure 6, the first run is ('+,
J+, Nt) The second run is (j,.

JlyNri The nth run is ('1. jn *Nn)
(!: f(7,.

In the circuit shown in FIG. 5, the data flowing through the pipeline, that is, the output of the arithmetic unit 3, is input to the comparison circuit 161, where it is compared with the value of the density designation register 17, and the data is converted into the data of the target image. It is determined whether

When it is determined that the input data is the data of the target image, the output of the comparison circuit 16 changes from 1L" to .H", and the first counter 19 starts counting the number of clock pulses. Here, the clock is synchronized so that one pulse is output every time image data is input.

By this time, the second counter 20 is reset at the start of image data transfer, and then remains "L" during the II HI11 line feed period while transferring one line of image data.
” is counted, and indicates one vertical coordinate of input image data.

Also, in the third counter 21, @L of the image valid signal 23
'', the number of pulses of the clock 24 is counted and indicates the horizontal coordinate in of input image data.

When the output of the comparison circuit I6 changes by one from "L" to "H", the memory control circuit 18 runs the data of the second counter 20 and the data of the third counter 2I, that is, the coordinates of the start point of the run. Write to result memory 22.

Next, when the input image data deviates from the target image area, the first counter 19 stops counting, and at the same time, the memory control circuit I8 stores the data, that is, the length of the run, in the run result memory 22. Write. Thereafter, the first counter 19 is reset.

By performing the above operations on all image data,
A run length transformation of the image is performed.

In order to calculate the moment, the calculator I then refers to the contents of the run result memory 22 and performs the calculation using software.

[Problems to be Solved by the Invention] In the above-mentioned conventional technology, the process up to run length conversion of image data is performed using dedicated hardware, so it is fast, but after that, moment calculation is performed using software. This requires a large amount of processing time.

In addition, the run length conversion circuit performs the following in one pipeline process:
Since run length conversion can only be performed for one density, if there are multiple target images with different densities, pipeline processing must be performed for the number of target images, which also causes an increase in processing time.

An object of the present invention is to provide an image processing device that can solve the above conventional problems.

[Means to solve the problem]

An image processing device according to the present invention is a pipeline operation type image processing device, and includes a delay circuit that delays read data by a multiplication of a read clock and a half thereof, and a match detection that detects a match between data that is read in succession. a data switching circuit that switches between data before delay and data after delay and inputs the data as an address to a memory that stores the calculation result; and a counter for knowing the position of the read data on the image memory; It is equipped with an addition circuit for calculating the moment and an addition switching circuit for switching the input of the addition circuit, and during one pipeline calculation period, all the densities J in the image memory are It is characterized by simultaneously determining the moment in the vertical or horizontal direction.

[Effect]

In the delay circuit, after reading the contents of the result memory and adding the coordinates in the vertical or horizontal direction, the input data is delayed by a time corresponding to the number of locks and half the clock required until the result memory IC can be written again. .

When image data starts to be input, the data switching circuit first outputs the data before being delayed as an address, and the memory control circuit reads the contents of the result memory.

At this time, when calculating the longitudinal moment, the counter is reset at the start of image data transfer and counts the number of image valid signals. That is, the vertical coordinates are output. Furthermore, when calculating the lateral moment, it is reset at the time of line feed in image data transfer, and the number of read clocks is counted. That is, the horizontal coordinates are output.

The contents of the read result memory are added to the output of the counter in an adder circuit.

At this point, the same data as when read, delayed by the delay circuit, appears at the address of the result memory, so
The output of the adder circuit is written there again.

Moment calculation can be performed by performing the above operations on all image data.

However, at this time, if two or more pieces of input image data have the same value, the next data will overwrite the contents of the result memory before the addition result for the first data is written to the result memory. Because it is read out, moment calculation may not be performed correctly.

For this reason, a coincidence detection circuit detects whether consecutively input image data have the same value, and if they are the same value, the contents of the result memory and the counter are used for the second and subsequent image data. By switching the addition switching circuit so that the output 1ζ of the addition circuit is added again to the value of the counter instead of adding up the outputs, the moment can always be calculated normally.

〔Example〕

Next, one embodiment of the present invention will be described based on FIG.

FIG. 2 is a diagram showing a timing chart of one embodiment of the present invention.

In FIG. 1, a computer 11, an image memory 2, and an arithmetic unit 3
This is the minimum configuration of the pipeline calculation type image processing device, and the other circuits are the circuits provided according to the present invention.

In the explanation, the delay circuit 4 inputted image data
．． It shall be delayed by 5 clocks, and the counter 9
shall count the clock 24, ie calculate the transverse moment. When calculating the moment in the vertical direction, the counter 9 is reset at the start of image data transfer, and the only change is to count the image valid signal 23, but there is no change in the main operation.

First, image data A is sent from the arithmetic unit 3 in synchronization with the clock 24. , AH, AH, Aa, etc. are transferred.

In delay circuit 4, this is delayed by 1.5 clocks.

The data switching circuit 7 outputs the data before the delay while the clock 24 is @Lm, and outputs the data after the delay while the clock 24 is @Lm as an address to the result memory 81.

When the output of the coincidence detection circuit 5 is "L", that is, when the consecutively inputted data are different, the memory control circuit 6 reads the contents of the result memory 8 when the clock 24 is "L".

The read contents of the result memory 8 are input to the addition switching circuit 10, but since the output of the coincidence detection circuit 5 is 1L'', the contents are input to the addition circuit 11 as they are.

The adder circuit 11 adds the output of the counter 9, that is, the horizontal coordinates of the input image data. The above operations are performed within 1.5 clocks.

When the clock 24 is 1H" 1.5 clocks after reading the result memory 8, the same address as at the time of reading appears in the address of the result memory 8, so the output of the -scattering product output circuit 5 becomes II. If L11, write the output of adder II again.

Next, assuming that the image data A and A are equal, the -scattering product output circuit 5 sets its output to °H'' for one clock.

Assuming that the output of the coincidence detection circuit 5 is 1H'', reading of the result memory 8 for the second data A is stopped, and instead, the addition switching circuit 10 is switched to change the output of the addition circuit II. , is again input to the adder circuit 11. Writing of the first data A to the result memory 8 is also suspended.

As a result, the contents of the result memory 8, which were output one after another when the first data A!, are now the two data A! .

The coordinates of A and A are continuously added and written to the result memory 8 by writing at AB.

This operation is performed in the same way no matter how many consecutive pieces of image data are the same.

Here, if the image data coincides with the undefined data during a line break and the first or last data of each line of the image data, a reading or writing failure of the memory 8 will occur as a result, so the memory control The circuit 6 always reads the result memory 8 at the beginning of each row, and always reads the result memory 8 at the end.
It must be written to the result memory 8.

By performing the above operations for all image data,
For each target image with a different density, the lateral moment is determined at the same address position as the density in one pipeline calculation.

〔Effect of the invention〕

As explained above, according to the present invention, the moment in the vertical direction or the horizontal direction can be calculated by one pipeline calculation for each target image of different density existing in the image memory.
This can be done simultaneously, eliminates the need for software processing, and enables a significant reduction in processing time.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an image processing device according to an embodiment of the present invention, FIG. 2 is a timing chart diagram of an embodiment of the present invention, FIG. 3 is an explanatory diagram of moment calculation, and FIG. 4 is a conventional Block diagram of the pipeline calculation type image processing device, No. 5
The figure is a block diagram of a run length conversion circuit for moment calculation according to the prior art, and FIG. 6 is an explanatory diagram of run length conversion. 4...Delay circuit, 5...-scattering output circuit, 7...Data switching circuit, 9...Counter, IO...Addition switching circuit, 11...Addition circuit.

Claims (1)

[Claims] In a pipeline arithmetic image processing device, a delay circuit delays read data by multiplying the read clock and half of the read clock, a match detection circuit detects a match between successively read data, and a match between data before being delayed. A data switching circuit that switches the delayed data and inputs it as an address to the memory that stores the calculation result, a counter that knows the position of the read data on the image memory, and an addition circuit that calculates the moment. and an addition switching circuit that switches the input of the addition circuit.