JP2659783B2 - Image processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an image processing device applied to a moment calculation circuit or the like in a vehicle number recognition device of a road toll machine.

[Conventional technology]

In the image processing such as the number recognition, as the characteristic amount representing the target image 25 having the density D in the image memory 2 as shown in FIG. 3, there are an area, a perimeter, a center of gravity, a circumscribed rectangle and the like.

Of these, to determine the center of gravity, the moments in the vertical and horizontal directions must be determined, and the moments must be divided by the area.

Here, the moment in the vertical (horizontal) direction is the sum of the product of the coordinate Y (X) in the vertical (horizontal) direction and the number N (M) of the densities D existing on the coordinates Σ (Y · N) ( Σ (X · M)).

FIG. 4 is a diagram showing an example of a pipeline operation type image processing apparatus according to the prior art.

In FIG. 4, the image captured by the camera 12 is
The signal is converted into a digital signal by the A / D converter 13 and written into the image memory 2.

The image data written in the image memory 2 is sequentially read out according to a command from the computer 1, subjected to various image processes by the arithmetic unit 3, and then written into the image memory 2 again.

The processed image is converted to an analog video signal by the D / A converter 15 and displayed on the monitor television 14.

Here, the computer 1 controls the apparatus and performs processing that cannot be performed by the arithmetic unit 3.

When the above-described moment is calculated by the above-described pipeline operation type image processing apparatus, a run length conversion of an image is conventionally performed by using a run length conversion circuit as shown in FIG.

Here, the run length conversion means that data in the image memory 2 is read out in the horizontal direction as shown in FIG.
This means that the coordinates are converted into the coordinates of the start point of the area of 25 (density D) and its length. In FIG. 6, the first run is (i ₁ , j ₁ , N ₁ )
The second run is (j ₂ , j ₁ , N ₂ ) and the nth run is (i ₁ , j _n ,
N _n ).

In the circuit of FIG. 5, the data flowing through the pipeline, that is, the output of the arithmetic unit 3, is input to the comparison circuit 16, where
It is compared with the value of the density designation register 17 and the data is
It is determined whether the data is data of the target image.

When it is determined that the input data is data of the target image, the output of the comparison circuit 16 changes from “L” to “H”, and the first
Counter 19 starts counting the number of clock pulses. Here, the clock is synchronized so that one pulse is output each time one image data is input.

By this time, the second counter 20 is reset when the transfer of the image data is started, and then becomes "H" during the transfer of one line of image data and "L" during the line feed period. The number of image valid signals 23 is counted, and indicates the vertical coordinate j _n of the input image data.

Also, shown in the third counter 21, after being reset by the "L" of the image effective signal 23, and counts the number of pulses of the clock 24, the coordinates i _n the transverse direction of the image data to be input.

When the output of the comparison circuit 16 changes from "L" to "H", the memory control circuit 18 compares the data of the second counter 20 and the data of the third counter 21, that is, the coordinates of the start point of the run with the run result. Write to memory 22.

Next, when the input image data deviates from the target image area, the second counter 19 stops counting, and at the same time, the memory control circuit 18 stores the data, that is, the length of the run in the run result memory 22. Write. Thereafter, the first counter 19 is reset.

By performing the above operation on all image data, the run length of the image is converted.

In order to calculate the moment, the computer 1 thereafter calculates the moment by software with reference to the contents of the run result memory 22.

[Problems to be solved by the invention]

In the above-described prior art, the run length conversion of image data is performed at high speed because it is performed by dedicated hardware. However, since the calculation of the moment must be performed by software, a large amount of processing time is required.

In addition, since the run length conversion circuit can perform run length conversion only for one density in one pipeline process, if there are a plurality of target images having different densities, the pipeline process must be performed by the number thereof. However, this also leads to an increase in processing time.

An object of the present invention is to provide an image processing apparatus that can solve the above-mentioned conventional problems.

[Means for solving the problem]

An image processing apparatus according to the present invention is a pipeline operation type image processing apparatus that reads labeling image data read into an image memory into an arithmetic unit in synchronization with a clock, processes the labeling image data, and writes a processing result into the image memory. A delay circuit for delaying image data read from an image memory by 1.5 clocks of the clock, a coincidence detection circuit for detecting coincidence of image data continuously output from the arithmetic unit in synchronization with the clock, and By switching between the image data before the delay in the circuit and the image data after the delay between the high level and the low level of the read clock, and inputting them as addresses to the operation result storage memory,
A data switching circuit for switching the operation result for each target image having a different density, counting the clock or the image valid signal, and coordinate values of the image data read into the result memory in the vertical or horizontal direction on the image memory And an addition circuit that adds the image data stored in the result memory to the count value of the counter, calculates the moment of the image data by accumulating the coordinate values for each label, and stores the moment in the result memory. And the addition circuit
An addition switching circuit for switching and inputting the output of the addition circuit and the read data from the result memory, and controlling the reading and writing of image data to and from the result memory in accordance with the detection signal of the coincidence detection circuit and the addition switching And a memory control circuit for switching circuits.

[Action]

In the delay circuit, the contents of the result memory are read out,
After the addition of the coordinates in the horizontal direction, the input data is delayed by a time corresponding to the number of clocks necessary for writing data to the result memory again and a time corresponding to half of the clocks.

When image data starts to be input, the data switching circuit first outputs data before delay as an address, and the memory control circuit reads the contents of the result memory.

At this time, when calculating the vertical moment, the counter is reset at the start of the image data transfer, and counts the number of image valid signals. That is, the vertical coordinate is output.
When the calculation of the lateral moment is performed, it is reset at the line feed of the image data transfer, and the number of read clocks is counted. That is, the coordinates in the horizontal direction are output.

The content of the read result memory is added to the output of the counter by the adding circuit.

At this time, since the same data as that at the time of reading, which has been delayed by the delay circuit, appears at the address of the result memory, the output of the adder circuit is rewritten there.

By performing the above operation on all image data,
Calculation of moment can be performed.

However, at this time, when two or more input image data have the same value successively, the next data stores the contents of the result memory before the result of addition to the first data is written to the result memory. Since the reading is performed, the calculation of the moment may not be performed normally.

For this reason, the coincidence detection circuit detects whether or not the successively input image data has the same value. If the value is the same, the contents of the result memory and the counter of the counter are read for the second and subsequent image data. By performing the switching of the addition switching circuit so as to add the value of the counter to the output of the adding circuit again instead of adding the output, the moment can always be normally calculated.

〔Example〕

 Next, an embodiment of the present invention will be described with reference to FIG.

FIG. 2 is a diagram showing a timing chart of one embodiment of the present invention.

In FIG. 1, a computer 1, an image memory 2, and a computing unit 3 are the minimum ones constituting a pipeline operation type image processing apparatus, and other circuits are circuits provided according to the present invention.

In the description, the delay circuit 4 converts input image data
Delay by 1.5 clocks and counter 9
Counts clock 24. That is, the moment in the lateral direction is calculated. When calculating the moment in the vertical direction, the counter 9 is reset at the start of the image data transfer and changes to count the image valid signal 23, but there is no change in the main operation.

First, the image data is transferred from the computing unit 3 as A ₀ , A ₁ , A ₂ , A ₃ ... In synchronization with the clock 24.

In the delay circuit 4, this is delayed by 1.5 clocks.

The data switching circuit 7 outputs data before delay to the result memory 8 as an address while the clock 24 is “L” and data after delay while the clock 24 is “H”.

When the output of the coincidence detecting circuit 5 is "L", that is, when successively input data is different, the memory control circuit 6 reads the contents of the result memory 8 when the clock 24 is "L".

The content of the read result memory 8 is input to the addition switching circuit 10, but is input to the addition circuit 11 as it is because the output of the coincidence detection circuit 5 is "L".

The adding circuit 11 adds the output of the counter 9, that is, the horizontal coordinate of the input image data. The above operation is performed within 1.5 clocks.

When the clock 24 after 1.5 clocks from the reading of the result memory 8 is "H", the same address as that at the time of reading appears in the address of the result memory 8, so that the output of the match detection circuit 5 is "L". If there is, the output of the adder circuit 11 is written again.

Then, the image data A ₂ and A ₃ are equal, the coincidence detection circuit 5, by one clock, and "H" the output.

When a match output of the detection circuit 5 is assumed to be "H", the result when the second data A ₃ suspended the reading of memory 8, instead, switches the addition switching circuit 10, the output of the adder circuit 11 To
The signal is input to the adder circuit 11 again. Also pauses result writing to the memory 8 when the first data A _2.

As a result, read out at the time of the first data A _2, the contents when the result memory 8, two data A _2, A ₃ of the coordinates are added continuously, in writing at the time of A _3, the results It will be written to the memory 8.

This operation is performed in the same manner, regardless of the number of consecutive image data.

Here, if the indefinite data in which the image data is line feed and the first or last data of each line of the image data happen to coincide with each other, reading or writing failure of the result memory 8 occurs. The circuit 6 must always read the result memory 8 at the beginning of each row and always write to the result memory 8 at the end.

By performing the above operation on all the image data, the moment in the horizontal direction is obtained by one pipeline operation at the position of the same address as the density for each target image having a different density.

〔The invention's effect〕

As described above, according to the present invention, for each of the target images having different densities existing in the image memory, the moment in the vertical direction or in the horizontal direction is calculated by one pipeline operation.
Simultaneously, the processing is not required by software, and the processing time can be greatly reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of an image processing apparatus according to one embodiment of the present invention, FIG. 2 is a timing chart of one embodiment of the present invention, FIG. 3 is an explanatory diagram of moment calculation, and FIG. Block diagram of the pipeline operation type image processing apparatus of FIG.
FIG. 1 is a block diagram of a run length conversion circuit for calculating a moment according to a conventional technique, and FIG. 6 is an explanatory diagram of run length conversion. 4 delay circuit 5 coincidence detection circuit 7 data switching circuit 9 counter 10 addition switching circuit 11
Addition circuit.

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Hideo Urata 1-1-1, Wadazaki-cho, Hyogo-ku, Kobe City, Hyogo Prefecture Inside the Kobe Shipyard of Mitsubishi Heavy Industries, Ltd. (56) References JP 62-3309 (JP, A) JP-A-60-157672 (JP, A)

Claims (1)

(57) [Claims] 1. A pipeline operation type image processing apparatus for reading out and processing a labeling image data read into an image memory in synchronization with a clock to an arithmetic unit and writing a processing result into the image memory. A delay circuit for delaying read image data by 1.5 clocks of the clock, a coincidence detection circuit for detecting coincidence of image data continuously output from the arithmetic unit in synchronization with the clock, and the delay circuit. By switching between the image data before the delay and the image data after the delay between the high level and the low level of the read clock and inputting them as addresses to the result memory for storing the calculation results, calculation is performed for each target image having a different density. A data switching circuit for switching the result; counting the clock or image valid signal; and an image read into the result memory. A counter indicating the vertical or horizontal coordinate value of the image data on the image memory, and adding the image data stored in the result memory and the count value of the counter, and accumulating the coordinate value for each label. An addition circuit for calculating a moment of image data and storing the result in the result memory; an addition switching circuit for switching and inputting an output of the addition circuit and data read from the result memory to the addition circuit; An image processing apparatus comprising: a memory control circuit that controls reading and writing of image data from and to the result memory in accordance with a detection signal of a detection circuit and performs switching of the addition switching circuit.