JPH02187074A - Optical semiconductor device - Google Patents
Optical semiconductor deviceInfo
- Publication number
- JPH02187074A JPH02187074A JP1006780A JP678089A JPH02187074A JP H02187074 A JPH02187074 A JP H02187074A JP 1006780 A JP1006780 A JP 1006780A JP 678089 A JP678089 A JP 678089A JP H02187074 A JPH02187074 A JP H02187074A
- Authority
- JP
- Japan
- Prior art keywords
- optical semiconductor
- peripheral circuit
- semiconductor device
- semiconductor element
- circuit components
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003287 optical effect Effects 0.000 title claims abstract description 83
- 239000004065 semiconductor Substances 0.000 title claims abstract description 80
- 230000002093 peripheral effect Effects 0.000 claims abstract description 35
- 239000013307 optical fiber Substances 0.000 claims abstract description 15
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 claims abstract description 13
- 239000005357 flat glass Substances 0.000 abstract description 18
- 230000008878 coupling Effects 0.000 abstract description 10
- 238000010168 coupling process Methods 0.000 abstract description 10
- 238000005859 coupling reaction Methods 0.000 abstract description 10
- 230000000593 degrading effect Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 20
- 230000007423 decrease Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 210000000988 bone and bone Anatomy 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Optical Couplings Of Light Guides (AREA)
- Led Device Packages (AREA)
- Light Receiving Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、光ファイバと光結合される発光素子若しくは
受光素子といった光半導体素子と、これに電気接続され
るトランジスタ、チップコンデンサー、チップ抵抗等の
周辺回路部品とを有する光半導体装置に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to optical semiconductor devices such as light emitting devices or light receiving devices that are optically coupled to optical fibers, and transistors, chip capacitors, chip resistors, etc. that are electrically connected thereto. The present invention relates to an optical semiconductor device having peripheral circuit components.
第3図に、従来から知られている光半導体装置を示す。 FIG. 3 shows a conventionally known optical semiconductor device.
従来の光半導体装置は、図示したように、チップ状の光
半導体素子(発光素子又は受光素子)1を単体で絶縁基
板2上に実装し、この絶縁基板2を金属製のボトムケー
ス3上に固定した後、窓ガラス4が嵌め込まれた金属製
の窓付きキャップうで覆って構成されている。As shown in the figure, in a conventional optical semiconductor device, a chip-shaped optical semiconductor element (light emitting element or light receiving element) 1 is mounted singly on an insulating substrate 2, and this insulating substrate 2 is mounted on a metal bottom case 3. After it is fixed, it is covered with a metal window cap into which the window glass 4 is fitted.
このように構成された光半導体装置は、光ファイバと光
結合され、光通信に用いられる。The optical semiconductor device configured in this manner is optically coupled with an optical fiber and used for optical communication.
第4図に、上述した光半導体装置と光ファイバとを光結
合する際に用いるレセプタクル6を示す。FIG. 4 shows a receptacle 6 used for optically coupling the above-described optical semiconductor device and an optical fiber.
レセプタクル6は、略円筒形に形成され、その−端にて
、光ファイバ7の一端を担持し、その他端には、上述し
た光半導体装置に嵌脱自在に外嵌する嵌合凹部が形成さ
れている。レセプタクル6内には、光半導体装置の光半
導体素子(発光素子または受光素子)1と光ファイバ7
とを光結合するレンズ8が設けられている。そして、こ
のレンズ8の焦点距離に合わせて、光ファイバ7と光半
導体装置との間における光の結合効率が最高となるよう
に、レンズ8と光半導体装置の窓ガラス4との間隔S、
及び光ファイバ7の一端とレンズ8との間隔S2が定め
られている。The receptacle 6 is formed into a substantially cylindrical shape, supports one end of the optical fiber 7 at its lower end, and has a fitting recess formed at the other end into which the above-mentioned optical semiconductor device is removably fitted. ing. Inside the receptacle 6 are an optical semiconductor element (light emitting element or light receiving element) 1 of an optical semiconductor device and an optical fiber 7.
A lens 8 is provided for optically coupling the two. Then, in accordance with the focal length of this lens 8, the distance S between the lens 8 and the window glass 4 of the optical semiconductor device is adjusted such that the coupling efficiency of light between the optical fiber 7 and the optical semiconductor device is maximized.
And a distance S2 between one end of the optical fiber 7 and the lens 8 is determined.
ところで、最近、上述した光半導体装置に、その周辺回
路部品を内蔵させることが要望されている。周辺回路部
品は、例えば、光半導体素子1としてフォトダイオード
等の受光素子を有した光半導体装置の場合には、受光素
子から取り出される信号を増幅するための増幅回路を構
成するアンプIC,チップコンデンサー、電界効果トラ
ンジスタ(FET)、チップ抵抗等の部品であり、光半
導体素子1としてレーザダイオード等の発光素子を有し
た光半導体装置の場合には、発光素子を駆動するための
駆動回路を構成する部品である。Incidentally, recently there has been a demand for the above-mentioned optical semiconductor device to have peripheral circuit components built therein. For example, in the case of an optical semiconductor device having a light-receiving element such as a photodiode as the optical semiconductor element 1, the peripheral circuit components include an amplifier IC and a chip capacitor that constitute an amplifier circuit for amplifying a signal extracted from the light-receiving element. , a field effect transistor (FET), a chip resistor, etc., and in the case of an optical semiconductor device having a light emitting element such as a laser diode as the optical semiconductor element 1, it constitutes a drive circuit for driving the light emitting element. It is a part.
しかし、第5図に示したように、これら周辺回路部品1
0a、10bを、単に、光半導体素子1が実装されてい
る絶縁基板2上に実装したのでは、周辺回路部品の高さ
寸法(例えば、アンプICで200〜600μm1チツ
プコンデンサーで0.6〜1.2mm)が、光半導体素
子1の高さ寸法(フォトダイオードで140μm)より
も大きいため、窓付きキャップ5と周辺回路部品10a
若しくは10bとの干渉を避けるのに、窓付きキャップ
5の高さ寸法を大きくする必要が生ずる。However, as shown in FIG.
If 0a and 10b are simply mounted on the insulating substrate 2 on which the optical semiconductor element 1 is mounted, the height dimensions of the peripheral circuit components (for example, 200 to 600 μm for an amplifier IC and 0.6 to 1 μm for one chip capacitor) .2 mm) is larger than the height dimension of the optical semiconductor element 1 (140 μm for a photodiode), the window cap 5 and the peripheral circuit component 10a
Alternatively, in order to avoid interference with 10b, it becomes necessary to increase the height dimension of the window cap 5.
この為、窓付きキャップ5に嵌め込まれた窓ガラス4と
光半導体素子1との間隔Lo (第3図に示す)がり
、に拡張されることとなる。この結果、第5図に示した
光半導体装置を、第4図に示したレセプタクル6の嵌合
凹部に嵌め合わせた場合、レンズ8と光半導体装置の窓
ガラス4との間隔S、は変わらないが、窓ガラス4と光
半導体素子1との間隔がり。からLlに拡張された分、
1ノンズ8と光半導体素子1の相互間の光路長が長くな
って、光の結合効率が低下する不都合があり、この結合
効率の低下を防止するためには、それ専用に、レンズ8
と光半導体装置の窓ガラス4との間隔S1を短縮化した
レセプタクル6を用意しなければならなかった。Therefore, the distance Lo (shown in FIG. 3) between the window glass 4 fitted into the window cap 5 and the optical semiconductor element 1 is increased. As a result, when the optical semiconductor device shown in FIG. 5 is fitted into the fitting recess of the receptacle 6 shown in FIG. 4, the distance S between the lens 8 and the window glass 4 of the optical semiconductor device does not change. However, the distance between the window glass 4 and the optical semiconductor element 1 is large. As it was expanded from Ll,
There is an inconvenience that the optical path length between the lens 8 and the optical semiconductor element 1 becomes long, and the coupling efficiency of light decreases.In order to prevent this decrease in coupling efficiency, the lens 8 is
It was necessary to prepare a receptacle 6 in which the distance S1 between the optical semiconductor device and the window glass 4 of the optical semiconductor device was shortened.
そこで、本発明は、上述の事情に鑑み、周辺回路部品を
内蔵させても、それ専用のレセプタクルを必要とせず、
周辺回路部品が内蔵されていない従来の光半導体装置と
の互換性を有し、周辺回路部品が内蔵されていない光半
導体装置用のレセプタクルを用いても、光ファイバとの
光の結合効率が低下することのない光半導体装置を提供
することを目的としている。Therefore, in view of the above-mentioned circumstances, the present invention does not require a dedicated receptacle even if peripheral circuit components are built-in.
It is compatible with conventional optical semiconductor devices that do not have built-in peripheral circuit components, and even when using a receptacle for optical semiconductor devices that do not have built-in peripheral circuit components, the coupling efficiency of light with optical fibers decreases. The purpose of the present invention is to provide an optical semiconductor device that does not require any damage.
上述の目的を達成するため、本発明による光半導体装置
においては、周辺回路部品が実装される基板の中央部上
方までリード線を延在させ、該基板の中央部上方に位置
したリード線の上面に光半導体素子を実装した構成とな
っている。In order to achieve the above-mentioned object, in the optical semiconductor device according to the present invention, the lead wires are extended to above the center of the board on which peripheral circuit components are mounted, and the upper surface of the lead wires located above the center of the board is It has a configuration in which an optical semiconductor element is mounted on the board.
この様な構成とすることによって、周辺回路部品よりも
高い位置に光半導体素子を配置することが可能となり、
光半導体素子を窓ガラスに近付けることが出来るように
なる。With this configuration, it is possible to place the optical semiconductor element at a higher position than the peripheral circuit components,
It becomes possible to bring the optical semiconductor element closer to the window glass.
以下、本発明の実施例について第1図及び第2図を参照
しつつ、説明する。Embodiments of the present invention will be described below with reference to FIGS. 1 and 2.
第1図は、受光素子を有する光半導体装置に、本発明を
適用した実施例の縦断面図であり、第2図は、第1図に
示した光半導体装置の骨部斜視図である。FIG. 1 is a longitudinal sectional view of an embodiment in which the present invention is applied to an optical semiconductor device having a light receiving element, and FIG. 2 is a perspective view of a bone portion of the optical semiconductor device shown in FIG. 1.
図示した光半導体装置は、ボトムケース11と、これに
担持される絶縁基板12と、絶縁基板12上に実装され
る周辺回路部品13a及び13b等と、ボトムケース1
1を下方から上方に貫通して絶縁基板12の中央部上方
まで延在したリード線15aと、絶縁基板12の中央部
上方に位置したリード線15aの上面に実装れれる光半
導体素子16と、これらを光半導体素子16の上方から
覆ってボトムケース11に固定される窓付きキャップ1
7とを備えている。The illustrated optical semiconductor device includes a bottom case 11, an insulating substrate 12 supported by the bottom case 11, peripheral circuit components 13a and 13b mounted on the insulating substrate 12, and the bottom case 11.
1 from below to above and extending to above the center of the insulating substrate 12; an optical semiconductor element 16 mounted on the upper surface of the lead wire 15a located above the center of the insulating substrate 12; A cap 1 with a window is fixed to the bottom case 11 while covering the optical semiconductor element 16 from above.
7.
ボトムケース11は、金属製であり、これには、これを
下方から上方に貫通した4本のリード線15a〜15d
が、ケースの接地用のリード線を除いて、樹脂等によっ
て絶縁されつつ、固定されている。ボトムケース11の
上面には、絶縁基板12が固定されている。また、絶縁
基板12の上面には、周辺回路部品13a及び13b等
が実装されている。なお、図示は省略したが、絶縁基板
12の上面には、メタライズパターンが、スクリーンを
用いた厚膜印刷、或いは、蒸着、スパッタによる薄膜形
成等の方法によって形成されている。The bottom case 11 is made of metal, and includes four lead wires 15a to 15d passing through it from below to above.
However, except for the grounding lead wire of the case, it is fixed and insulated with resin or the like. An insulating substrate 12 is fixed to the upper surface of the bottom case 11. Further, on the upper surface of the insulating substrate 12, peripheral circuit components 13a and 13b, etc. are mounted. Although not shown, a metallized pattern is formed on the upper surface of the insulating substrate 12 by thick film printing using a screen, thin film formation by vapor deposition, sputtering, or the like.
ボトムケース11に固定されているリード線15a〜1
5dの内の一本15aは、絶縁基板12の側方上部にて
屈曲し、絶縁基板12の中央部上方まで延在している。Lead wires 15a to 1 fixed to the bottom case 11
One of the wires 15a is bent at the upper side of the insulating substrate 12, and extends to above the center of the insulating substrate 12.
このリード線15aの絶縁基板12の中央部上方に位置
した部分の上面には、フォトダイオード等のチップ状の
光半導体索子16がダイボンディングされている。なお
、リード線15aの絶縁基板12の中央部上方に位置し
た部分の上面は、光半導体素子16のダイボンディング
を容易にするため平坦になっている。A chip-shaped optical semiconductor cable 16 such as a photodiode is die-bonded to the upper surface of a portion of the lead wire 15a located above the center of the insulating substrate 12. Note that the upper surface of the portion of the lead wire 15a located above the center of the insulating substrate 12 is flat in order to facilitate die bonding of the optical semiconductor element 16.
リード線の太さは、例えば、0.511I11程度であ
り、絶縁基板12の中央部上方に位置した部分は、これ
を屈曲させ、その上面を平坦に加工して形成されるので
、その厚みも、はぼ0.5mm程度となる。The thickness of the lead wire is, for example, about 0.511I11, and the part located above the center of the insulating substrate 12 is formed by bending it and processing the top surface to be flat, so the thickness is also small. , is approximately 0.5 mm.
光半導体索子16は、ワイヤボンディングによって周辺
回路部品13a、13b若しくは絶縁基板12上のメタ
ライズパターンと接続されており、また、周辺回路部品
13a、13b若しくは絶縁基板12上のメタライズパ
ターンは、ワイヤボンディングによってリード線15a
〜15bに接続されている。周辺回路部品13a及び1
3bは、例えば、電界効果トランジスタ及びチップ抵抗
であり、メタライズパターンによって相互に接続され、
図示しない他の周辺回路部品と共に、光半導体索子16
から取り出される信号を増幅するための増幅回路を構成
する。The optical semiconductor cable 16 is connected to the peripheral circuit components 13a, 13b or the metallized pattern on the insulating substrate 12 by wire bonding. Lead wire 15a by
~15b. Peripheral circuit components 13a and 1
3b is, for example, a field effect transistor and a chip resistor, which are interconnected by a metallized pattern,
Along with other peripheral circuit components not shown, the optical semiconductor cable 16
An amplifier circuit is configured to amplify the signal extracted from the.
絶縁基板12、周辺回路部品13a、、13bs光半導
体素子16等は、第1図に示したように、窓付きキャッ
プ17によって覆われている。窓付きキャップ17は、
略円筒状の金属製の部材で、その底部にてボトムケース
11の外周部に外嵌して固定される。窓付きキャップ1
7の頂部には、光半導体素子16の上面と対向して窓ガ
ラス18が嵌め込まれている。The insulating substrate 12, peripheral circuit components 13a, 13bs, optical semiconductor element 16, etc. are covered with a window cap 17, as shown in FIG. The window cap 17 is
It is a substantially cylindrical metal member, and its bottom part is fitted onto and fixed to the outer peripheral part of the bottom case 11. Cap with window 1
A window glass 18 is fitted into the top of 7 so as to face the top surface of the optical semiconductor element 16 .
上述したように構成された本発明による光半導体装置に
おいては、リード線15aを絶縁基板12の中央部上方
に延在させ、その上面に光半導体素子16を実装してい
るので、光半導体素子16を最も窓ガラス18に近接さ
せて配置でき、窓ガラス18と周辺回路部品13a、1
3bとの干渉を避けるために、光半導体素子16と窓ガ
ラス18との相互間隔L2を拡張する必要はなく、該相
互間隔L2を自由に決定することができる。In the optical semiconductor device according to the present invention configured as described above, the lead wire 15a extends above the central portion of the insulating substrate 12, and the optical semiconductor element 16 is mounted on the upper surface of the lead wire 15a. can be placed closest to the window glass 18, and the window glass 18 and peripheral circuit components 13a, 1
3b, it is not necessary to extend the mutual distance L2 between the optical semiconductor element 16 and the window glass 18, and the mutual distance L2 can be determined freely.
従って、L2を第3図に示したし。に一致させることが
容易にでき、従来の周辺回路部品が内蔵されていない光
半導体装置用のレセプタクルを用いて、光の結合効率を
低下させることなく、光ファイバと光結合させることが
できる。Therefore, L2 is shown in FIG. The optical fiber can be optically coupled to the optical fiber without reducing the optical coupling efficiency using a receptacle for an optical semiconductor device that does not have conventional peripheral circuit components built-in.
なお、上述した実施例においては、光半導体素子15と
して、フォトダイオード等の受光素子を用いているが、
光半導体素子15は、レーザダイオード等の発光素子で
あってもよい。この場合には、周辺回路部品は、発光素
子を駆動する駆動回路を構成する部品となる。Note that in the above embodiment, a light receiving element such as a photodiode is used as the optical semiconductor element 15;
The optical semiconductor element 15 may be a light emitting element such as a laser diode. In this case, the peripheral circuit components are components that constitute a drive circuit that drives the light emitting element.
また、上述した実施例は、4本のリード線を有する光半
導体装置に本発明を適用したものであるが、リード線の
本数はこれに限定されるものではない。Further, in the embodiment described above, the present invention is applied to an optical semiconductor device having four lead wires, but the number of lead wires is not limited to this.
以上説明したように、本発明による光半導体装置におい
ては、周辺回路部品が実装される基板の中央部上方まで
リード線を延在させ、該基板の中央部上方に位置したリ
ード線の上面に光半導体素子を実装した構成となってい
るので、周辺回路部品よりも高い位置に光半導体素子を
配置することが可能となり、光半導体素子を窓ガラスに
近接させることができる。それゆえ、光半導体素子より
も高さ寸法が大きい周辺回路部品を内蔵させることによ
って光半導体素子と窓ガラスとの相互間隔が拡張するこ
とを防止でき、光半導体素子と窓ガラスとの間隔を、周
辺回路部品が内蔵されていない従来の光半導体装置のそ
れに一致させることが可能となる。よって、周辺回路部
品が内蔵されていない従来の光半導体装置との互換性を
有するようになり、周辺回路部品が内蔵されていない光
半導体装置用に作製されたレセプタクルを用いても、光
ファイバとの光の結合効率が低下することがない。As explained above, in the optical semiconductor device according to the present invention, the lead wires are extended to above the center of the board on which peripheral circuit components are mounted, and light is emitted onto the upper surface of the lead wires located above the center of the board. Since the semiconductor element is mounted, the optical semiconductor element can be placed at a higher position than peripheral circuit components, and the optical semiconductor element can be placed close to the window glass. Therefore, by incorporating peripheral circuit components whose height dimension is larger than that of the optical semiconductor element, it is possible to prevent the mutual distance between the optical semiconductor element and the window glass from increasing, and to reduce the distance between the optical semiconductor element and the window glass. It becomes possible to match that of a conventional optical semiconductor device in which peripheral circuit components are not built-in. Therefore, it is now compatible with conventional optical semiconductor devices that do not have built-in peripheral circuit components, and even if a receptacle manufactured for an optical semiconductor device that does not have built-in peripheral circuit components is used, it will not work with optical fibers. The coupling efficiency of light does not decrease.
3.11・・・ボトムケース、4.18・・・窓ガラス
、5.17・・・窓付きキャップ、6・・・レセプタク
ル、7・・・光ファイバ、8・・・レンズ、l Q a
110 b+13a、13b−・・周辺回路部品、1
5a 〜15d・・・リード線。3.11...Bottom case, 4.18...Window glass, 5.17...Cap with window, 6...Receptacle, 7...Optical fiber, 8...Lens, l Q a
110 b+13a, 13b-...peripheral circuit parts, 1
5a to 15d...Lead wires.
第1図は本発明による光半導体装置の縦断面図、第2図
は第1図に示した本発明による光半導体装置の部分斜視
図、第3図は従来の光半導体素子を示した縦断面図、第
4図は光半導体装置と光ファイバをレセプタクルを用い
て光結合したところを示した部分断面斜視図、第5図は
第3図に示した光半導体装置の絶縁基板上に周辺回路部
品を実装した場合の縦断面図である。
1゜16・・・光半導体素子、2.12・・・絶縁基板
、特許出願人 住友電気工業株式会社
代理人弁理士 長谷用 芳 樹炙 p?i
啓1Δ
爽 犬 炉J
第1図
第2図
3足
釆
づ3フ1J
第
図
た¥−講4本仮lとし℃アタフル
篇巨7ykご児べ粗過回アトい品】りuくし孜七中11
)条灸1第
図FIG. 1 is a vertical cross-sectional view of an optical semiconductor device according to the present invention, FIG. 2 is a partial perspective view of the optical semiconductor device according to the present invention shown in FIG. 1, and FIG. 3 is a vertical cross-sectional view of a conventional optical semiconductor element. Figure 4 is a partial cross-sectional perspective view showing optical coupling between an optical semiconductor device and an optical fiber using a receptacle, and Figure 5 shows peripheral circuit components on the insulating substrate of the optical semiconductor device shown in Figure 3. FIG. 1゜16...Optical semiconductor device, 2.12...Insulating substrate, Patent applicant: Sumitomo Electric Industries Co., Ltd. Representative Patent Attorney Yoshiki Hase p? i
Kei 1Δ Sou Inu Furnace J Figure 1 Figure 2 Figure 3 Foothold 3F 1J Figure ¥-Ko 4 temporary l and ℃ Atafuru version huge 7yk child's gross overtime product] Riu Kushi Keishichi Junior high school 11
) Moxibustion 1st figure
Claims (1)
光ファイバと前記光半導体素子とが光結合される光半導
体装置であって、 前記光半導体素子に電気接続される周辺回路部品と、前
記周辺回路部品が実装される基板と、前記ケースの外部
から内部に貫入し、前記基板の中央部上方にその少なく
とも一部が延在するリード線とを備え、前記基板の中央
部上方に位置した前記リード線の上面に前記光半導体素
子を実装したことを特徴とする光半導体装置。[Scope of Claims] An optical semiconductor device in which an optical fiber and the optical semiconductor element are optically coupled through a window provided in a case housing the optical semiconductor element, comprising a peripheral circuit electrically connected to the optical semiconductor element. a component, a board on which the peripheral circuit component is mounted, and a lead wire that penetrates into the case from the outside and extends at least partially above the center of the board, the lead wire extending above the center of the board. An optical semiconductor device characterized in that the optical semiconductor element is mounted on the upper surface of the lead wire located above.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1006780A JPH02187074A (en) | 1989-01-13 | 1989-01-13 | Optical semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1006780A JPH02187074A (en) | 1989-01-13 | 1989-01-13 | Optical semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02187074A true JPH02187074A (en) | 1990-07-23 |
Family
ID=11647690
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1006780A Pending JPH02187074A (en) | 1989-01-13 | 1989-01-13 | Optical semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02187074A (en) |
-
1989
- 1989-01-13 JP JP1006780A patent/JPH02187074A/en active Pending
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