JPH02184049A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a wiring pattern having an air bridge structure characterized by the small capacitance of foil wires and large mechanical strength highly reliably by transforming a resin layer incorporating silicon beneath a wiring pattern part into an inorganic layer 61. CONSTITUTION:A PMSS resin as a resin incorporating silicon is rotatably applied on the entire surfaces of electrodes 21-23 and 31 and an insulating layer on a semiconductor substrate on which elements 2-4 are formed. Thus a resin layer 6 is formed. Then the device is heated in atmosphere and also in nitrogen atmosphere, and the resin is hardened by heating. Then, a parallel plate type oxygen plasma apparatus is used, and the PMSS resin layer 6 is transformed into the inorganic layer from the surface. Then, holes are provided from the upper surface of the inorganic layer 61. Contact holes 71 and 72 are formed on the electrode 21 of the first element 2 and on the electrode 31 on the second element 3. The contact holes 71 and 72 are filled with metal, and embedded conductor parts 81 and 82 are formed. Thereafter, a wiring pattern part 83 which is connected to the embedded conductor parts 81 and 82 is formed on the upper surface of the inorganic layer 61. Then, the inorganic layer 61 is removed by isotropic etching.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for wiring a semiconductor device.

The aim is to create a wiring method that reduces wiring capacitance and achieves smaller and faster devices.

a step of forming a silicon-containing resin layer on a semiconductor substrate on which an element is formed; a step of mineralizing the silicon-containing resin layer from the surface to form a mineralized layer on the surface of the silicon-containing resin layer; a step of forming a plurality of contact holes in the mineralized layer and the silicon-containing resin layer, a buried conductor portion for burying the plurality of contact holes, and a wiring pattern connected to the buried conductor portion and disposed on the mineralized layer. A semiconductor device manufacturing method includes a step of forming a portion, and a step of selectively etching and removing the inorganic layer to form an air bridge structure in the wiring pattern portion.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for wiring a semiconductor device.

Currently, the competition for miniaturization of semiconductor integrated circuit elements is becoming more and more intense, and as a result, the development of wiring technology is in a fierce competition to form miniaturized patterns.

Wire spacing has become smaller as processing technology improves.

Research and development efforts are underway to realize large-capacity integrated circuits.

Furthermore, there is a strong demand for higher speed as well as higher capacity, and in order to increase the speed of devices with increased capacity, there is a need for a method of reducing wiring capacitance.

[Conventional technology]

2. Description of the Related Art Conventionally, there has been an element having a wiring pattern of an air bridge structure, which is manufactured for the purpose of reducing wiring capacitance.

In forming the air bridge structure, the resin layer in contact with the wiring pattern is removed by etching.

However, in the conventional process, it was difficult to remove the resin layer, making it difficult to remove it to a uniform thickness, and when the etching solution was shaken, the wiring pattern warped and came into contact with the electrodes and wiring underneath, among other problems.

[Problems to be Solved by the Invention] Therefore, it has not been possible to realize a wiring pattern with a highly reliable air bridge structure, and it has not been possible to say that a technology for reducing wiring capacitance by the air bridge method has been established.

SUMMARY OF THE INVENTION The present invention aims to provide a method for reliably forming a wiring pattern having an air bridge structure with low wiring capacity and high mechanical strength in order to meet the demands for larger capacitance and higher speed devices. .

[Means for Solving the Problems] FIG. 1 shows Embodiment I of the present invention realizing an air bridge structure.
FIG.

Means for solving the above problem will be explained with reference to FIG. 1 and the reference numerals in the figure.

The above problem is solved by the semiconductor substrate 1 on which the elements 2, 3.4 are formed.
a step of forming a silicon-containing resin layer 6 thereon; a step of mineralizing the silicon-containing resin layer 6 from the surface to form a mineralized layer 61 on the surface of the silicon-containing resin layer 6; and a step of forming a mineralized layer 61 on the surface of the silicon-containing resin layer 6. and a step of forming a plurality of contact holes 71.72 in the silicon-containing resin N6, and a buried conductor portion 81.8 for burying the plurality of contact holes 71.72.
2 and a step of forming a wiring pattern section 83 connected to the buried conductor sections 81 and 82 and disposed on the inorganic layer 61, selectively etching and removing the inorganic layer 61,
The problem is solved by a semiconductor device manufacturing method including a step of forming the wiring pattern portion 83 into an air bridge structure.

[Effect]

In the present invention, the silicon-containing resin 1 below the wiring pattern portion 83! Mineralized layer 6 to form an air bridge I6
I am changing it to 1. The silicon-containing resin layer 6 is.

For example, silylated polymethylsilsesoxane (PM
(referred to as SS), and by subjecting it to mineralization treatment, for example, by exposing it to oxygen plasma.

It can be replaced with a mineralized layer 61 of silicon dioxide.

This mineralization proceeds from the surface, and its thickness can be easily controlled.

Such an inorganic layer 61 of silicon dioxide is easily dissolved in an etching solution of, for example, hydrochloric acid.

The wiring pattern portion 83 having a highly accurate air bridge structure that maintains a desired space can be easily obtained.

In this way, the speed of the device can be increased.

〔Example〕

FIG. 1 is a diagram for explaining the process of forming a wiring pattern of an air bridge structure in Example 1 of the present invention.

Figure 1 (at) and Figure 1 (1) are top views;
Figure (a2), Figures 1 (b) to (e).

FIG. 1(f2) is a sectional view taken along line A-A.

The following description will be made with reference to these figures.

See FIGS. 1(a and 2). FIGS. 1(al) and (a2) are a top view and an A-A sectional view of a semiconductor substrate on which elements are formed, respectively, where 1 is a semiconductor substrate, 2 is the first element, 3 is the second element, 4 is the third element, 21.22.23.31°41 is the electrode, 5
represents an insulating layer.

The first element 2 is a field effect transistor, for example, a second
The element 3 and the third element 4 are, for example, Schottky diodes.

Referring to FIG. 1(b), PMSS resin as a silicon-containing resin is spin coated on the entire surface. Figure 2 shows the molecular structure of PMSS resin.

The viscosity of the PMSS resin used is about 40 cp (centipoise), and the PMSS resin layer 6 with a thickness of about 1.5 μm is formed by spin coating at 4000 rpm.

Next, the resin was heated in the atmosphere at 100° C. for 10 minutes, then at 250° C. for 110 minutes, and then heated at 350° C. for 40 minutes in a nitrogen atmosphere to thermoset the resin.

This achieves device planarization.

1 frequency 13.5 using a parallel plate type oxygen plasma device (see Fig. 1(C))
6 Ml, mineralization proceeds from the surface of the PMSS resin layer 6 under the following exposure conditions: high frequency power of 200 W, ion sheath voltage of 300 to 400 V-b (self-bias), and oxygen atmosphere pressure of 1.5 Pa.

Figure 3 shows the progress of mineralization by oxygen plasma.

These are the results of actual measurements on a 0.6 μm thick PMSS resin layer that has been subjected to the above thermosetting treatment.

Mineralization penetrates from the surface according to the following reaction rules.

T (t) = T, -, /r where L is time (minutes) and T(t) is P after t minutes.
The layer thickness of the MSS resin layer, To is the initial layer thickness.

K is a coefficient.

Referring to FIG. 3, by exposing to oxygen plasma for 5 minutes, a mineralized layer 61 having a thickness of approximately 3,500 layers is formed.

Contact holes 71 and 72 are formed on the electrode 21 of the first element 2 and on the electrode 31 of the second element 3 by drilling holes from the surface of the mineralized layer 61 (see FIG. 1(d)).

Refer to FIG. 1(e) After filling the contact holes 71 and 72 with metal and forming the buried conductor parts 81 and 82, a thickness of lam is determined to connect the buried conductor parts 81 and 82 to the upper surface of the inorganic layer 6I.

Aluminum (AI) wiring pattern part 8 with a width of 2 μm
form 3.

Using a barrel-type etching device as shown in Figures 1 (rl) and (2), carbon fluoride (CF4) and oxygen (02
The mineralized layer 61 is removed by isotropic dry etching with a mixed gas of ) or by isotropic wet etching with 5 to 10% hydrofluoric acid.

FIGS. 1(fl) and 1(f2) are a top view and a sectional view taken along line A-A in this state, respectively.

The inorganic layer 61 is removed below the wiring pattern section 83,
An air bridge structure is formed.

In this way, the wiring pattern portion 83 having an air bridge structure connecting the electrode 21 of the first element 2 and the electrode 31 of the second element 3 was manufactured.

The formation and removal of the mineralized layer 61 can be performed easily and with good controllability, and no undue force is applied to the wiring pattern portion 83. Furthermore, even if the Yoshiba wiring pattern portion 83 is bent and touches the underlying PMSS resin N6, this resin layer has extremely high electrical resistance, so there will be no problem in terms of characteristics.

Furthermore, the relative dielectric constant of PMSS resin is 3.

The dielectric constant of commonly used polyimide resin (3.5 to 3.
8) Being smaller is also advantageous in terms of wiring capacity.

Next, as Example H of the present invention, a wiring pattern is formed on the wiring pattern part 83 shown in Example I to connect it to the third element 4. An example of so-called multilayer wiring is shown.

FIG. 4 is a diagram for explaining the process of forming multilayer wiring in Example 2.

FIG. 4(rl) is a top view, and FIGS. 4(a) to (e), and FIG. 4(f2) are BB sectional views.

The following description will be made with reference to these figures.

See FIG. 4(a) FIG. 4(a) is a reproduction of FIG. 1(e) of Example 2, where I is a semiconductor substrate, 2 is a first element, 3 is a second element, 21, 22, 23, and 31 are electrodes, 5 is an 8i layer, 6 is a PMSS layer, 61 is an inorganic layer, 81.82 is a buried conductor portion, and 83 is a wiring pattern portion.

Thereafter, substantially the same steps as those shown in FIGS. 1(b) to 1(e) are performed.

Refer to FIG. 4(b), PMSS resin is spin-coated on the entire surface, and the wiring pattern portion 83 is
After forming a PMSS resin layer 9 with a thickness of 5000 mm overlying the substrate, a thermosetting treatment is performed.

See Figure 4 (C) Mineralization proceeds from the surface of the PMSS resin layer 9.

The entire PMSS resin layer 9 is mineralized to form a mineralized layer 91.

Refer to FIG. 4(d) A hole is made from the surface of the inorganic layer 91 to form a wiring pattern portion 8.
Contact holes 11 and 12 are formed on the third element 3 and the electrode 41 of the third element 4.

Refer to FIG. 4(e) After filling the contact holes 11.12 with metal and forming the buried conductor portions 13.14, the thickness is such that the buried conductor portions 13 and 14 are connected to the upper surface of the mineralized layer 91. 1
An upper layer wiring pattern portion 15 of aluminum (AI) having a width of 2 μm and 1 μm is formed.

Refer to FIGS. 4(rl) and (r2). The mineralized layer 91 and the mineralized layer 61 are removed by wet etching with butic acid (10% hydrofluoric acid).

FIGS. 4(fl) and (r2) are a top view and a BB sectional view in this state, respectively.

Thus, the wiring pattern part 83 of the air bridge structure connects the electrode 21 of the first element 2 and the electrode 31 of the second element 3, and the wiring pattern part 83 and the electrode 41 of the third element 4 are connected. A multilayer wiring pattern consisting of the upper layer wiring pattern portion 15 having an air bridge structure is formed.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to reduce wiring capacitance and form a highly reliable wiring pattern that is stable against distortion during chip processing and distortion during element operation.

Moreover, according to the method of the present invention, continuous processing is possible.
Suitable for mass production.

The present invention greatly contributes to increasing the capacity and speed of semiconductor devices.

21, 22.23.3L 41 is an electrode.

5 is an insulating layer.

6.9 is a silicon-containing resin layer, which is a PMS S resin layer.

6L 91 is mineralized layer 3 11, 12, 71, and 72 are contact holes.

13, 14, 81, and 82 are embedded conductor parts.

15 is an upper layer wiring pattern section.

83 is the wiring pattern part

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining the process of Example 2. Figure 2 shows the molecular structure of PMSS resin. Figure 3 shows the progress of mineralization by oxygen plasma. FIG. 4 is a diagram for explaining the process of Example H. In fig. 1 is a semiconductor substrate. 2 is the first element. 3 is the second element. 4 is the third element. (L: Lt, 1 (α2) Jitsukuri ° example diagram cape f) 1) (chi 1) Jitsukata self Itari diagram (〒 no (C) (d) Mitsu Teki Ida] Otokozu (壬) /+ 2.) H3 PH1,5 Kizuki 1's minute: 5-Hashigo Figure 2 <a>CC') Minoru Katsumi Itari 1 [

Claims (1)

[Claims] A step of forming a silicon-containing resin layer (6) on the semiconductor substrate (1) on which the elements (2, 3, 4) are formed; a step of forming a mineralized layer (61) on the surface of the silicon-containing resin layer (6) by chemical treatment, and forming a plurality of contact holes (71, 72), and a step of forming buried conductor portions (81, 82) for burying the plurality of contact holes (71, 72) and the buried conductor portions (81, 8).
2) forming a wiring pattern section (83) connected to the inorganic layer (61) and disposed on the inorganic layer (61);
1) selectively etching and removing the wiring pattern portion (83) to form an air bridge structure.