JPH02180456A - クロック切換回路 - Google Patents

クロック切換回路

Info

Publication number
JPH02180456A
JPH02180456A JP63334189A JP33418988A JPH02180456A JP H02180456 A JPH02180456 A JP H02180456A JP 63334189 A JP63334189 A JP 63334189A JP 33418988 A JP33418988 A JP 33418988A JP H02180456 A JPH02180456 A JP H02180456A
Authority
JP
Japan
Prior art keywords
clock
signal
phase
output
switching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63334189A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0554296B2 (enrdf_load_stackoverflow
Inventor
Akira Takayama
明 高山
Harumitsu Mizuno
水野 春光
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yamaha Corp
Original Assignee
Yamaha Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yamaha Corp filed Critical Yamaha Corp
Priority to JP63334189A priority Critical patent/JPH02180456A/ja
Publication of JPH02180456A publication Critical patent/JPH02180456A/ja
Publication of JPH0554296B2 publication Critical patent/JPH0554296B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Communication Control (AREA)
JP63334189A 1988-12-29 1988-12-29 クロック切換回路 Granted JPH02180456A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63334189A JPH02180456A (ja) 1988-12-29 1988-12-29 クロック切換回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63334189A JPH02180456A (ja) 1988-12-29 1988-12-29 クロック切換回路

Publications (2)

Publication Number Publication Date
JPH02180456A true JPH02180456A (ja) 1990-07-13
JPH0554296B2 JPH0554296B2 (enrdf_load_stackoverflow) 1993-08-12

Family

ID=18274535

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63334189A Granted JPH02180456A (ja) 1988-12-29 1988-12-29 クロック切換回路

Country Status (1)

Country Link
JP (1) JPH02180456A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009066383A1 (ja) * 2007-11-21 2009-05-28 Fujitsu Limited 記憶回路及び記憶回路の制御方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009066383A1 (ja) * 2007-11-21 2009-05-28 Fujitsu Limited 記憶回路及び記憶回路の制御方法
US8164973B2 (en) 2007-11-21 2012-04-24 Fujitsu Limited Storage apparatus and method of controlling storage apparatus
JP4968340B2 (ja) * 2007-11-21 2012-07-04 富士通株式会社 記憶回路及び記憶回路の制御方法

Also Published As

Publication number Publication date
JPH0554296B2 (enrdf_load_stackoverflow) 1993-08-12

Similar Documents

Publication Publication Date Title
EP0135879B1 (en) Interface circuit and method for connecting a memory controller with a synchronous or an asynchronous bus system
US5274678A (en) Clock switching apparatus and method for computer systems
US4970405A (en) Clock selection circuit for selecting one of a plurality of clock pulse signals
US5263172A (en) Multiple speed synchronous bus having single clock path for providing first or second clock speed based upon speed indication signals
KR100337052B1 (ko) 동기화된 독출 포인터 및 기록 포인터를 갖는 2 중 포트 fifo
KR100425472B1 (ko) 동기식 반도체 메모리 장치의 출력 제어 신호 발생 회로및 출력 제어 신호 발생 방법
US4835728A (en) Deterministic clock control apparatus for a data processing system
US5408641A (en) Programmable data transfer timing
KR100711131B1 (ko) 복수의 클록 도메인을 구비한 시스템을 위한 데이터 전송 장치
KR20040063283A (ko) 제어신호 발생회로 및 상기 제어신호 발생회로를 구비하는데이터 전송회로
US5148112A (en) Efficient arbiter
JP2000341093A (ja) 低消費電力ディジタル論理回路
US5692137A (en) Master oriented bus bridge
EP0319184B1 (en) Two stage synchronizer
US7027542B1 (en) Apparatus and method for providing data transfer between two digital circuits with different clock domains and for solving metastability problems
US20040135610A1 (en) Method and apparatus to delay signal latching
JPH02180456A (ja) クロック切換回路
JP2001159970A (ja) 装置間結合装置
US6075398A (en) Tunable digital oscillator circuit and method for producing clock signals of different frequencies
US7123674B2 (en) Reducing latency and power in asynchronous data transfers
JP3468977B2 (ja) 同期回路間データストリーム制御方法及びその制御装置
US6255869B1 (en) Method and apparatus for system resource negotiation
JP2756445B2 (ja) 非同期回路リセット方式
JPH08179926A (ja) データ転送制御用クロック同期c素子群
JPS63282820A (ja) クロック信号切換え方式

Legal Events

Date Code Title Description
S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313532

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20070812

Year of fee payment: 14

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080812

Year of fee payment: 15

LAPS Cancellation because of no payment of annual fees