JPH02180419A - Data rate converting circuit - Google Patents

Abstract

PURPOSE:To prevent the circuit from forming erroneous data by applying the competition detecting signal of competition detecting circuit to a selective circuit as a selection control signal, and outputting auxiliary data by means of a clock signal which does not compate at the time of competing. CONSTITUTION:A competition detecting circuit 30 divides a first clock signal CK1 into two through a 1/2-dividing circuit 31, and detects the competition of the CK1 with a second clock signal CK2. Output signals Q32 and Q33 from flip flop circuits 32 and 33 are applied to an exclusive OR circuit 36. A selection control signal S36 is outputted from the said circuit 36, and data Q22 latched in a 180 deg. different phase are selected and outputted at the time of competing. Consequently stable data rate converting data Q12 can be obtained. In addition, since a circuit 30 to detect the competition is composed of a D-type flip flop circuit and a buffer circuit, the constitution is simplified.

Description

Detailed Description of the Invention "Industrial Application Field" The present invention relates to a data rate conversion circuit that resamples a sampling signal sampled in synchronization with a certain clock signal with another asynchronous clock signal having a different frequency. Regarding.

[Prior Art] For example, in a video tape recorder, a chroma signal is processed using a clock signal synchronized with a color subcarrier signal, and then its data is processed in a luminance signal processing system in order to match the data rate of the luminance signal processed. Rates are converted. Furthermore, the data rate is appropriately converted during processing in the chroma signal processing system.

In devices that digitally process various signals in this way, the data layer I
・Converting.

Conventionally, such data rate conversion is performed by latching the original data with a clock signal having the frequency before conversion (pre-conversion clock signal), and then using the latched data as a clock signal having the frequency after conversion (post-conversion clock signal). This was done by re-latching the signal (signal).

[Problems to be Solved by the Invention] However, when the pre-conversion clock signal and the post-conversion clock signal are asynchronous and have different frequencies, it is difficult to determine whether or not to latch the original data using the pre-conversion clock signal. Furthermore, there may be cases where the latch signal is further latched using the converted clock signal. In this case, the latch operation using the converted clock signal is not performed properly, and data with a value that does not exist in the original data may be latched in the latch circuit at the subsequent stage.

This kind of conflict between clock signals before and after conversion occurs, and although it is not noticeable as long as either the original data is latched before or after the original data, a value that is not in the original data may be formed due to the conflict between the clock signals. What is happening is a big problem.

Conventionally, in order to solve this problem, firstly, the latch timing conflict based on the pre-conversion clock signal and the post-conversion clock signal is monitored, and if a conflict occurs, the latch timing of the pre-conversion clock signal is changed only at that time. A method has been proposed to avoid contention by delaying the process.

However, this method requires an analog delay circuit to variably delay the pre-conversion clock signal.
The signal processing circuit including this data rate conversion circuit becomes complicated, and realizing this analog delay circuit becomes a big problem when it is integrated into an integrated circuit.

In addition, in order to solve the problem caused by latch timing conflicts, secondly, the data latched by the pre-conversion clock signal is latched by a separate clock signal with a higher frequency than the post-conversion clock signal, and this latched data is transferred to the post-conversion clock signal. Some methods have attempted to solve problems caused by contention by forming output data by thinning out data according to the frequency of the signal.

However, in this case, there is the problem that it is necessary to form a separate clock signal that is originally unnecessary, and that a complicated structure is required to thin out the latch data according to the clock signal after conversion. .

The present invention has been made in consideration of the above points, and is capable of converting data rates without forming erroneous data even if the latch timings of two clock signals before and after data rate conversion conflict. The present invention is intended to provide a data rate conversion circuit with a simple configuration that can perform the following steps.

[Means for Solving the Problem] In order to solve the problem, the data rate conversion circuit of the present invention includes a first latch circuit that latches input data based on the first clock signal before rate conversion. and,
a second latch circuit that latches the output data of the first latch circuit based on the first clock signal or a second clock signal applied after rate conversion; and a clock signal for the second latch circuit that has a different phase. a third latch circuit that latches the output data of the first latch circuit based on clock signals of the same frequency having the same frequency, and detects conflict between the phase of the first clock signal and the phase of the second clock signal. a selection@circuit that selects the output data of the third latch circuit when there is a conflict and selects the output data of the second latch circuit when there is no conflict, based on the output signal of the conflict detection circuit; A fourth latch circuit latches data passed through this selection circuit based on a second clock signal.

[Operation] The input data is latched by the first latch circuit based on the first clock signal, and the latched data is further latched by the second latch circuit based on the first clock signal or the second clock signal. It is latched by the circuit, and is also latched by a third latch circuit based on a clock signal having the same frequency as the second clock signal but a different phase.

Each data thus latched by the second and third latch circuits is given to a selection circuit9.Furthermore, the first and second clock signals are given to a conflict detection circuit, and this conflict detection circuit controls these signals. It is detected whether or not the first and second clock signals conflict with each other, and a conflict detection signal is provided to the selection circuit as a selection control signal. The selection circuit selects the output data of the third latch circuit when there is a conflict, and selects the output data of the second latch circuit when there is no conflict and outputs it to the fourth latch circuit. The fourth latch circuit latches data from the selection circuit based on the second clock signal, and this latched data is output as output data of the data rate conversion circuit.

As a result, in the event of a conflict, spare data latched by a non-conflicting clock signal is output.
Data with unstable values will not be output during contention.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

In FIG. 1, this data rate conversion circuit 10 includes a D-type flip-flop circuit 11 that latches input data before conversion based on a first clock signal CKI, and a D-type flip-flop circuit 11 that latches input data based on a second clock signal CK2. In addition to the D-type flip-flop circuit 12 that outputs rate-converted output data, a sampling phase selection circuit 20 and a conflict detection circuit 30 are provided.

The sampling phase selection circuit 20 includes two D-type flip-flop circuits 21 and 22 used as latch circuits.
, a switch circuit 23 for two-manpower one-output cancellation, and an inverter circuit 24.

Data Qll latched by the flip-flop circuit 11 is input to the flip-flop circuits 21 and 22, respectively, and the flip-flop 91 circuit 21 latches the input data Qll based on the second clock signal CK2, and the flip-flop circuit 21 latches the input data Qll based on the second clock signal CK2. 22 is the second clock signal C
The input data Q1 is generated based on the third clock signal CK3, which is formed by inverting K2 via the inverter circuit 24.
Latch 1.

The latch data Q21 of the flip-flop 91 circuit 21 is applied to the switch circuit 23 as a first selection input, and the latch data Q22 of the other flip-flow 91 circuit 22 is applied to the switch circuit #123 as a second selection input. The switch circuit 23 is given an output signal S36 from a conflict detection diagram #130, which will be described later, as a selection control signal, and when the selection control signal S36 does not indicate a conflict state (logic 'LJ), the switch circuit 23 When the latch data Q21 from the flip-flop circuit 21 is selected and the selection control signal S36 indicates a conflict state (logic 'HJ), the latch data Q21 from the flip-flop circuit 22 is selected.
22 is selected and output to the flip-flop circuit 12.

That is, this sampling phase selection circuit 20
When there is no conflict between the clock CK1 and the second clock signal CK2, the latched data Q21 is output based on the second clock signal CK2, and when there is a conflict, the data Q21 is output based on the second clock signal CK2. Since the data Q21 latched based on the data Q21 may be erroneous data, the data Q22 latched based on the inverted clock signal CK3 is output.

The conflict detection circuit 30 operates as a 1/2 frequency divider circuit.
type flip-flop circuit 31, two D-type flip-flop circuits 32 and 33 that operate as a latch circuit, more specifically, as a phase comparison circuit, and two two-stage buffer circuits 34 that operate as a minute time delay circuit. and 35, and an exclusive OR circuit 36 which operates as a match/mismatch circuit.

This conflict detection circuit 30 detects a conflict between the first and second clock signals CKI and CK2. In this embodiment, the first clock signal CKi is higher than the second clock signal CK2. Since the frequency is within 1.5 times, and only the rising phase of the first clock signal CKI (latched at the rising edge) is a problem, conflict detection at pointless points is eliminated. Therefore, the frequency of the first clock signal CKI is divided by 1/2 via the 1/2 frequency dividing circuit 31 to detect a conflict with the second clock signal CK2.

This frequency-divided signal Q31 is delayed by a minute amount of time via the two-stage buffer circuit 34, and then sent to the D-type flip-flop circuit 32.
is applied to the data input terminal of

The second clock signal CK2 is directly applied to the clock input terminal of this flip-flop recess 832. Therefore, by this flip-flop circuit 32, the frequency-divided signal Q
31 delayed by a minute time, and the second
The phases of the clock signal CK2 and the clock signal CK2 are compared.

The second clock signal CK2 is applied to the clock input terminal of the D-type flip-flop circuit 33 via the two-stage buffer circuit 35 after being delayed by the same minute time as described above.

The data input terminal of this flip-flop circuit 33 is
A frequency-divided signal Q31 of the first clock signal CKI is directly applied. Therefore, the flip-flop circuit 33 compares the phases of the frequency-divided signal Q31 and the delayed signal S35 obtained by delaying the second clock signal CK2 by a minute amount of time.

Here, as for the delay time caused by the two-stage buffer circuits 34 and 35, data modification due to competition between latch operations in the latch circuits 11 and 12 is a problem, so the set-up time and hold time of the latch circuits 11 and 12 It is fine as long as it is a time that satisfies you. In this embodiment, the required time is obtained by passing through two stages of buffer circuits 34 and 35.

In this way, the flip-flop circuit 32 compares the phase of the original frequency-divided signal Q31 with a slightly delayed phase of the second clock signal CK2, and conversely, the phase of the original second clock signal CK2 is compared with the phase of the second clock signal CK2. Since the flip-flop circuit 33 compares the slightly delayed phase of the frequency-divided signal Q31 with the phase of the frequency-divided signal Q31, the frequency-divided signal Q31 (therefore, the first clock signal CK1) and the second clock signal CK2 conflict with each other. If there is a conflict, output signals Q32 and Q33 of different logic levels are output from each flip-flop circuit 32 and 33, whereas if there is no conflict, which signal Q31,
Even if CK2 is slightly delayed, each flip-flop circuit 32, 33 outputs the output signal Q3 of the same logic level.
2, Q33 is output.

Output signals Q32 and Q33 from these flip-flop circuits 32 and 33 are sent to an exclusive OR circuit 36.
given to. The exclusive OR circuit 36 outputs an output signal S36 that connects the above-mentioned switch circuit 23 to the flip-flop circuit 22 side when the logic levels of the two inputs Q32 and Q33 are different, that is, when they are in a competitive state.
On the other hand, when the logic levels of the two inputs Q32 and Q33 match, that is, when they are not in a competitive state, an output signal S36 is sent that connects the above-mentioned switch circuit 23 to the flip-flop circuit 21 side.

Note that when performing phase comparison between the flip-flop circuits 32 and 33, the phase signal related to the second clock signal CK2 (CK2 itself, 535) is applied to the clock input terminals of these flip-flop circuits 32 and 33. This is to ensure that the switching of the switch circuit 23 is performed using the period of the second clock signal CK2 as a unit time.

In the above configuration, the first clock CKI applied before data rate conversion changes as shown in FIG. 2(A), and the second clock signal CKI applied after data rate conversion changes.
Assume that K2 is changing as shown in FIG. 2(C).

In this case, the latched data Qll latched by the flip-flop circuit 11 in response to the first clock signal CKI becomes as shown in FIG. 2(B).

Therefore, the latch data Q21 and Q22 obtained by latching this latch data QLI by the flip-flop circuits 21 and 22 based on the second clock signal CK2 and its inverted clock signal CK3 are shown in FIGS. 2(E) and 2, respectively. The result is as shown in (D).

Here, it is assumed that the first clock signal CKI and the second clock signal CK2 compete at time t1.

In this case, it is not clear whether the latched data Q21 latched by the flip-flop circuit 21 at this time t1 will be the value "aJ or rb" before or after the data Qll given to the flip-flop circuit 21 before or after this time. ,
Further, the data may be a mixture of values [aj and rl)J. On the other hand, even at this time t1, the latch data Q22 of the flip-flop circuit 22 has a stable value "aJ
It is supposed to take.

Such latch data Q21 and Q22 are provided to the switch circuit 23.

Further, the first clock signal CKI is applied to a flip-flop circuit 31, frequency-divided by the flip-flop circuit 31, and a frequency-divided signal Q31 as shown in FIG. 2(F) is output.

Therefore, the flip-flop circuit 32, which compares the phase of the signal S34 obtained by delaying the frequency-divided signal Q31 and the second clock signal CK2, outputs a phase comparison signal Q32 as shown in FIG. 2(G). Ru. In this example, time t
1, the phase comparison signal Q32 rises to the logic "■(". Also, the frequency division signal Q31 and the second clock signal CK2
The flip-flop circuit 33 which compares the phase with the delayed signal S35 outputs a phase comparison signal Q33 as shown in FIG. 2(H). In this example, time L1
The phase comparison signal Q33 rises to logic r) (J) from a time point delayed by one period of the second clock signal CK2.

Therefore, as shown in FIG. 2(J), the exclusive OR circuit 36 outputs a selection control signal S36 that rises to logic rH only from time t1 to time t2, and the switch circuit 23 As shown in FIG. 2 (J), the latch data Q22 in a stable state is selected during this period tl-t2, and since competition is not a problem during other periods, the second clock signal CK2 applied after conversion is selected.
The latch data Q21 latched in is selected and given to the latch circuit 12 (S23>. In this way, the latch circuit 12 generates a stable data string as shown in FIG. Rate-converted output data Q12 is sent out.

Therefore, according to the embodiment described above, based on the second clock signal CK2 after conversion, the data Qll latched by the first clock signal CKI before conversion is latched, and the second clock signal CK2 Data Q22 is latched at a phase that differs by 180 degrees from that of Q12, and in the event of a conflict, the data Q22 latched at a phase different by 180 degrees is selected and output, resulting in stable data rate conversion data Q12.
can be obtained. Accordingly, since the circuit 30 for detecting competition is constructed from a D-type flip-flop circuit, a buffer circuit, and an exclusive OR circuit, the construction is simple and can be easily adapted to integrated circuits.

Note that in the above embodiment, the first clock signal C
We have shown a method that detects conflicts by dividing KI by 1/2, but
The conflict may be detected by doubling the frequency of the other clock signal CK2.

Moreover, the first and second clock signals CK1 and CK2
The layer division ratio may be determined according to the frequency ratio of , and is not limited to frequency division by two, and competition may be detected without frequency division.

Further, in the above embodiment, the two-stage buffer circuits 34 and 35 are used as delay circuits for conflict detection, but buffer circuits with other numbers of stages may be used. A delay element that can obtain a minute delay time other than the above may also be used.

Furthermore, in the above embodiment, the preliminary data Q22 selected only in the event of a conflict and the original data Q21 are latched using the phase information of the converted clock signal CK2, but the clock signal before conversion If the frequency of is lower than the frequency of the clock signal after conversion, the preliminary data and the original data corresponding thereto may be latched based on the clock signal before conversion. In this case, the signal relationship applied to the data input terminal and clock input terminal of the latch circuit provided for comparing the phases of the first and second clock signals CKI and CK2 is also reversed from that of the above embodiment. It is necessary to do so.

In the embodiment described above, the clock signal CK3 for the flip-flop circuit 22 which latches preliminary data in case of contention is formed by inverting the second clock signal CK2, but other methods may also be used. The phase may also be determined by the second clock signal CK2.
It is not necessary that the phase of the flip-flop circuit 22 is opposite to that of the first clock signal CKI and CK2. All you have to do is make sure the data can be latched.

[Effects of the Invention] As described above, according to the present invention, in preparation for a conflict, a clock signal having the same frequency and a different phase as the clock signal before conversion or after TFI is latched based on the clock signal before conversion. The data is latched to obtain preliminary data, and when a conflict is detected, the preliminary data is selected and output, so even if the clock signals before and after conversion conflict, erroneous data will not be generated. Therefore, it is possible to obtain a data rate conversion circuit with no problems.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a data rate conversion circuit according to the present invention, and FIG. 2 is a timing chart of each part thereof. 10...Data rate conversion circuit, 11.12.21.
22... Latch type flip-flop circuit, 20.
... Sampling phase selection circuit, 23... Switch circuit, 24... Inverter circuit, 30... Conflict detection circuit, 31... Frequency division type flip-flow 71 circuit, 32
．． 33...Flip-flop circuit for phase comparison, 3
4.35...Two-stage buffer circuit for delay, 36...Exclusive OR circuit for detecting coincidence and mismatch.

Claims (2)

[Claims] (1) A first latch circuit that latches input data based on a first clock signal applied before rate conversion; and a first latch circuit that latches input data based on the first clock signal applied before rate conversion; and a second latch circuit that latches based on a second clock signal; and a clock signal of the same frequency that has a different phase from the clock signal for the second latch circuit, and outputs data from the first latch circuit. a third latch circuit for latching; a conflict detection circuit for detecting a conflict between the phase of the first clock signal and the phase of the second clock signal; a selection circuit that selects the output data of the third latch circuit when there is no contention and selects the output data of the second latch circuit when there is no contention; and a selection circuit that selects the output data of the second latch circuit when there is no conflict; A data rate conversion circuit comprising: a fourth latch circuit for latching. (2) The conflict detection circuit delays the first pulse signal containing the phase information of the first (or second) clock signal by a minute amount of time until each of the latch circuits becomes stable when latched. a fifth latch circuit that latches the delayed signal at the timing of a second pulse signal that includes phase information of the second (or first) clock signal; A sixth latch circuit latches the signal at the timing of the delayed signal delayed by the minute amount of time, and detects a mismatch between the logical levels of the output signals from the fifth and sixth latch circuits, 2. The data rate conversion circuit according to claim 1, further comprising a match/mismatch circuit that indicates a conflict and outputs a conflict detection signal that indicates a conflict when there is a mismatch.