JPH02179124A - Digital/analog conversion circuit - Google Patents

Abstract

PURPOSE:To prevent production of an error in an analog conversion output with respect to a digital signal by constituting a switch circuit with a MOSFET. CONSTITUTION:NPN transistors(Tr) T17-T19 being components of a constant current circuit, resistors R11-R13 and inverters X11-X13 being components of a switch circuit are provided to the title circuit. In this case, MOSFETs are employed for TRs being the switch circuit. That is, MOS TRs T11 and T12, T13 and T14, T15 and T16 and the inverters X11-X13 constitute the switch circuit. Thus, an analog output signals with respect to digital input signals A, B, C are obtained at an output terminal IOUT as a current and the constant current generated by the T1-T7 being components of the constant current circuit is delivered by 100% to the output terminal IOUT. No error is caused to an analog conversion output with respect to the digital input.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital-to-analog conversion circuit that converts a digital signal into an analog signal.

[Conventional technology]

Conventionally, this type of digital-to-analog conversion circuit (hereinafter referred to as
A D/A converter (hereinafter referred to as a D/A converter) includes a switching circuit for a plurality of bits of digital input and a constant current circuit using bipolar transistors or the like.

FIG. 3 is a circuit diagram of a conventional D/A converter.

As shown in FIG. 3, this D/A converter includes inverters X31 to X33 whose input sides are connected to input terminals A to C, respectively, into which a 3-bit digital signal is input, and the outputs and inputs of these inverters X31 to X33. Terminal A~
Three pairs of NPN transistors T31.C are connected to their respective bases. Ta2, T33. T34; T35゜T
36, and the collectors are connected to the commonly connected emitters of each pair of transistors, and the emitters are connected to GND (low potential) via resistors R32 to R34, respectively, and the bases of each are connected to a reference power supply V R, . NPN transistors 737 to T39 supplying transistors T31 . T33. The collectors of T35 are both connected to the high power supply ■cc, while the transistors T32゜T34
．． Both collectors of T36 are connected to the output terminal v out, and a resistor R3 is connected between the high power supply ■cc and the output terminal V0LIT.
It is configured by connecting with 1. In this D/A converter, transistors T37 to T39 and resistors R32 to R
34 constitutes a constant current circuit on each diagonal, and a transistor pair T
31 and Ta2; T33 and T34; T35 and T36 and inverters X31 to X33 each constitute a switch circuit.

Here, the resistor R31 is set to 1Ω, and the transistor T39
The collector current (hereinafter referred to as rc) is 1mA, T38
So that the IC of T37 is 2mA and the Ic of T37 is 4mA.
A reference voltage VRεF and resistors R32 to R34 are respectively set. Input terminals A to C each have a logic value of “0”.
'', add VREF +0.5 V and set the logical value to ``1''.
'° when VRpp +1. OV shall be added.

First, input terminals A, B, and C are respectively '0'',
When "0"', transistors T31°T33. T35
is turned on, and transistors T32, T34. T36 is turned off and no current flows through resistor R31, so the high power supply V
The potential difference between CC and the output terminal VOUT becomes O■. Next, input terminal A.

When B and C are 1"', "o", "o", transistors T31, T33, and T36 are turned on, and transistor T32
．． T34. T35 is off and resistor R31 has 1mA
Current flows, high power ■. The voltage between 0 and the output terminals Vo and JT becomes IV. Next, input terminals A, B, and C are “O”
, "1", "O", the transistor T31. T34
．． T35 is turned on and transistors T32. T33. T3
6 is turned off, and a current of 2 mA flows through resistor R31.
■High power supply. The voltage between 0 and the output terminal VOUT becomes 2■. Hereinafter, in the same way, input terminals A, B, and C are each "
1", '1" When "0", 3■, °°0"゛, °"
4V when 0″″II l 1″, “1″II
Q11. 5V when “1”, “o”, “1”
′°.

°When “1”, 6■, 1”g, u 1 ++,
When I" is 1°, it becomes 7■. In this way, analog output signals for the digital input signals A, B, and C are obtained as voltages at the output terminal Voυ↑.

[Problem to be solved by the invention]

In the conventional D/A converter described above, a constant current circuit consisting of an NPN transistor and a resistor is switched by a switch circuit consisting of a pair of NPN transistors. The problem is that the signal flows to the base, causing an error in the analog conversion output for the digital input. Also,
Conventional D/A converters require a special level for the input signal for controlling the switch circuit, so they have the disadvantage of requiring an input level conversion circuit or the like.

SUMMARY OF THE INVENTION An object of the present invention is to provide a D/A converter that does not generate errors in the analog conversion output of such digital signals and does not require input level conversion.

[Means to solve the problem]

The D/A converter of the present invention includes a constant current circuit including n bipolar transistors whose bases are commonly connected to a reference power supply, and resistors respectively connected between the emitters of the bipolar transistors and a first power supply. ,
an inverter whose input side is connected to each of the n digital input terminals; and an n pair of inverters each having its input terminal and the output of the inverter inputted to its gate, and connected to the connector of the pair of bipolar transistors with the source or drain in common. N channel or P channel MO3
FET, the drain or source of each MOSFET whose gate is directly connected to the input terminal is connected in parallel to the output terminal, and the drain or source of the other MOSFET is connected in parallel to a second power supply. , or each MO3 whose gate is directly connected to the input terminal.
The drain or source of the FET is connected in parallel to the first output terminal, the drain or source of the other MOSFET is connected in parallel to the second output terminal, and the first and second output terminals are connected through resistors, respectively. and is configured to connect a second power source.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a D/A converter showing a first embodiment of the present invention.

As shown in FIG. 1, the D/A converter of this embodiment consists of a constant current circuit and a switch circuit, and the constant current circuit, that is, the NPN transistors T17 to T19 and resistors R11 to R13 that make up this circuit are different from those of the conventional example. The same applies to the inverters Xll to X13 that constitute the switch circuit. This embodiment differs from the conventional example in that the transistors constituting this switch circuit are realized by N-channel MO5FETs. That is, MOS transistors T17~
T19 and resistors R11 to R13 constitute a constant current circuit, and M
OS) Transistors Tll and Tl2; T13 and T, 14;
T15 and T16 and inverters Xll to X13 constitute a switch circuit. In addition, inverters Xll to X1
3 is a circuit that generates an inverted signal for digital input to input terminals A-C.

Here, the collector current IC of transistor T19 (MOS)
is 1mA, MOS transistor T18 IC is 2mA,
MOS) Set the reference voltage VREF and the resistors R11 to R13 so that Ic of the transistor T17 becomes 4 mA, and set the power supply voltage c.

is 5■. In addition, input terminals A to C have a logic value of +1.
When 0 II, add 0■, and when the logical value is “1'', 5V
shall be added.

First, input terminals A, B, and C are each at "'0°."

When the gate is 0° and 0°, the N-channel MOS transistor Tl 1. Tl 3. Tl5 is turned on and T12°T14. Since T16 is turned off, the output terminal ■. The current flowing through U-cho becomes OA. Next, input terminal A.

When B and C are '1', 'o', and 'o', N-channel MOS transistors Tl1.T13.T16 are turned on and T12.T14.T15 are turned off, so that the current flows to the output terminal I0LIT. The current will be 1mA. Below,
In the same way, input terminals A, B, and C are
, II I II, IIQ, II, the output terminal I0LIT is 2mA, "1", "1", "O"
3mA when ``1'', ``1'', 7mA when ``1°°''.

In this way, digital input signals A, B.

The analog output signal for C is obtained as a current at the output terminal IOUA, and the constant current generated by T17 to T19 forming the constant current circuit is 100% output terminal IOU.
It will be transmitted to ↑. In this example, high power supply ■. 0 and output terminal■. There is no need for a resistor connected between 07 and 07.

FIG. 2 is a circuit diagram of a D/A converter showing a second embodiment of the present invention.

As shown in FIG. 2, this embodiment is a circuit that takes out an analog output in response to a digital input as a voltage, and also takes out both positive and reverse polarity output voltages. N-channel MOS that constitutes the switch circuit and constant current circuit
) The transistor, inverter, and resistor are the same as in the first embodiment described above, and the difference is that a resistor is connected between the high power source and each output terminal. That is, N channel MOS) transistors T27 to T29 and resistor R
23 to R25 are constant current circuits, and MOS) transistors T21 and T22. T23 and T24; T25 and T26 constitute a switch circuit. Inverter X21-X23
is a circuit that generates an inverted signal of a digital input. Here, collector current Ic of N-channel MOS transistor T29 is 1 mA, Ic of T28 is 2 mA, and Ic of T27 is 1 mA.
Reference voltage VRF: F + resistor R2 so that C becomes 4 mA
Set 3 to R25, and resistors R21 and R22 are 100Ω.
VCC is set to 5V.

In addition, input terminals A to C have OV when the logical value is ``0''.
, and when the logical value 1# is 111, 5■ is added.

First, when input terminals A, B, and C are "0", "0", and "o", MoS transistors T21.T23.T25 are turned on and T22.T24.T26 are turned off, so resistor R2
1 current flows 7mA, power supply ■cc and one output terminal■
The potential difference between it and ouTl is 0.7■. Furthermore, since the current flowing through the resistor R22 is OA, the potential difference between the power supply Vcc and the other output terminal Vouvz becomes 0■.
Next, when inputs A, B, and C are "1", "o", and "o", Mo3) transistor T21. T23. T26 is turned on, and T22. T24. Since T25 is turned off, a current of 6 mA flows through resistor R21, and the voltage between VCC and Voutr becomes 0.6V. Also, the current of resistor R22 is 1mA
current, the potential difference between VCC and VOυD2 is 0. IV
become. In the same way, input terminals A, B, and C are set to 0°.
°, "1"', "0", the potential difference between VCa and Vout is 0.5 V, the potential difference between Vcc and VOU↑2 is 0.2■, and input terminals A, B, and C are " +1
++,"(l II, l"When Opa, VCCV
0.4■ between OLITI, 0 between Vcc and VOUT2
．． 3V, input terminals A, B, C are 1°', "1°'"
° When 1”, VCCVOUTI is OV, VCc-
The distance between VOυ↑2 becomes 0.7■. That is, in this embodiment, both positive polarity and reverse polarity of the analog output voltage for the digital input signal are obtained at the same time.

Further, since the switch circuit is composed of MOS transistors, 100% of the current from the constant current circuit can be transmitted.

In the above two embodiments, the digital input has been described as an example of 3 bits, but it goes without saying that the digital input can be expanded or reduced to n bits as desired.

Furthermore, although the above two embodiments have been described using NPN transistors as transistors constituting the constant current circuit, a D/A converter can be similarly realized even if the transistors are replaced with PNP transistors. However, in this case, the high power supply (Vcc) and the low power supply (GND) may be reversed. In addition, Mo3FE, which similarly constitutes the switch circuit,
T can also be replaced with a P-channel MOS FET.

〔Effect of the invention〕

As explained above, the D/A converter of the present invention can transmit 100% of the current from the constant current circuit to the output by configuring the switch circuit with Mo3FET. This has the effect that no errors occur. Also,
Since the D/A converter of the present invention requires only an input signal level of OV with respect to the power supply voltage, there is no need for extra circuits such as a level conversion circuit, and there is an effect that it can be easily interfaced with 0MO3 and TTL. .

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a D/A converter showing a first embodiment of the present invention, and FIG. 2 is a circuit diagram of a D/A converter showing a second embodiment of the present invention.
Converter circuit diagram, Figure 3 shows an example of a conventional D/A
FIG. 3 is a circuit diagram of a converter. A~C...Digital input terminal, T17~T19゜T
21~T26...N channel Mo3FET, T17~
T19. T27-T29...NPN transistor, X
11-X13. X21-X23...Inverter, R1
1~R13, R21~R25...Resistance, 1 oυ...
・Current output terminal, V REP...Reference power supply terminal, V
0UTI I V 0UT2...Voltage output terminal, GN
D...Ground potential. (Taburi Patent Attorney Shina Uchihara 3 Lu

Claims (1)

[Claims] a constant current circuit having n bipolar transistors whose bases are commonly connected to a reference power supply, and resistors respectively connected between the emitters of the bipolar transistors and a first power supply; and each of the n digital input terminals. an inverter whose input side is connected to the inverter, and n pairs of N-channel or P-channel MOSFETs, each of which has its input terminal and the output of the inverter inputted to its gate, and whose source or drain is connected to a pair of connectors of the bipolar transistors. each MOSFE including a switch circuit having a gate directly connected to the input terminal;
Either connect the drains or sources of T in parallel to the output terminal and connect the drains or sources of other MOSFETs in parallel to a second power supply, or connect the drains or sources of each MOSFET whose gate is directly connected to the input terminal in parallel. is connected to the first output terminal and the other MOSFE
1. A digital-to-analog conversion circuit characterized in that the drain or source of T is connected in parallel to a second output terminal, and a second power source is connected to the first and second output terminals through resistors, respectively.