JPS6253512A - Pulse output device - Google Patents

Abstract

PURPOSE:To vary the amplitude and offset voltage of an output pulse signal by providing a separating circuit separating an output pulse signal of a pulse output circuit into an AC signal and a DC signal and a bias control circuit. CONSTITUTION:A pulse signal outputted from a pulse output circuit 21 is separated into an AC signal and a DC signal by the separation circuit 22, the DC signal, an offset signal from a bias control circuit 24 and an inverting signal of an amplitude control signal are added to be a bias control signal, which is superimposed on the separated AC signal and the result is inputted to a differential logic circuit 25. In changing the amplitude control signal, current source control circuits 22, 26 for both the differential logic circuit and the pulse output circuit act in the same polarity and the bias control signal from the bias control circuit is operated reversely. Thus, the amplitude and DC bias voltage inputted to the differential logic circuit are changed simultaneously to vary continuously the amplitude of the output pulse signal thereby operating the differential logic circuit at the optimum condition.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a pulse output device, and more particularly to a pulse output device that can increase the range of change in output amplitude and offset voltage even in a high frequency region.

[Prior art] In recent years, the amount of data information in PCM (pulse code modulation) communication has been converted to G (giga) bits, logic integrated circuits using QaAS, and RAM (random
Research and development is progressing on technologies such as access memory). There is a need for a device that outputs a test signal in the form of a pulse wave in order to test the operation of semiconductor devices or devices that operate digitally at such high speeds.

This test signal can of course vary in frequency and data type, and can also be used to check the margin of input amplitude and threshold voltage of a semiconductor device under test or a device incorporating such a device. It is essential that the pulse amplitude and offset voltage of the test signal can be arbitrarily varied.

Conventionally, as shown in FIG. 2, as shown in FIG. 2, the emitters (sources in the case of FETs) of a pair of transistors 1a and 1b are connected to each other, and the pulse outputs for outputting such test pulse signals are connected to each other. A differential logic circuit 2 that performs a switching operation is widely used.

That is, the emitters of the pair of transistors 1a and ib constituting this differential logic circuit 2 are commonly connected to the constant current circuit 3, and the collectors of each transistor are connected to a load resistor 4a, respectively.
4b and is connected to the offset control circuit 5. The bases of the transistors 1a and 1b are connected to input terminals 6a and 6b to which pulse signals having different polarities are input, as shown in the figure, and the transistors 1b
The collector of is connected to the output terminal 7 from which the output pulse signal is taken out. The base of the current limiting transistor 3a constituting the constant current circuit 3 is connected to an input terminal 8 to which an amplitude control signal for controlling the amplitude of the output pulse signal is input.
It is connected to the. Further, an input terminal of a differential amplifier 5a constituting the offset control circuit 5 is connected via a resistor 5b to an input terminal 9 of an offset control signal that controls the offset voltage of the output pulse signal.

In the pulse output device configured in this manner, the amplitude of the output pulse signal output from the output terminal 7 is determined by the emitter current value IE determined by the constant current circuit 3 controlled by the amplitude control signal input from the input terminal 8. and the resistance 11iR of the load resistance 4b of the transistor 1b + which product (IER4
). Therefore, it is possible to obtain a desired amplitude value by changing the amplitude control signal.

Also, the offset control circuit 5 outputs an offset voltage corresponding to the offset control signal input from the input terminal 9 and applies it to the load resistors 4a and 4b, so the offset voltage of the output pulse signal output from the output terminal 7 is , a value proportional to the offset control signal. therefore,
A desired offset voltage can be obtained by changing the offset control signal.

However, the pulse output device composed of the differential logic circuit 2 shown in FIG. 2 has the following problems.

In other words, when increasing only the amplitude while keeping the offset voltage of the output pulse signal constant, it is necessary to increase the amplitude control signal and increase the emitter current value IE using the constant current circuit 3, but the emitter current 1i11E is large. Then, when the transistors 1a and Ib are conductive, the collector
The emitter voltage Vca (drain-source voltage VD4 in the case of FET) becomes low. In general, the transition frequency fT, which indicates the gain and phase characteristics in the high frequency region of a transistor, is the collector-emitter voltage V
The lower the ca, the smaller it becomes. As a result, when the amplitude of the output pulse signal is increased, the rise/fall time of the pulse waveform becomes longer, causing a problem that the waveform characteristics deteriorate.

In addition, when changing the offset voltage while keeping the amplitude of the output pulse signal constant, the change in the offset voltage means that the collectors of transistors 1a and 1b
The emitter voltage Vc@ will change. Therefore, when the offset voltage is high, the collector-emitter voltage Vch becomes high, so the above-mentioned transition frequency ft becomes high and the rise/fall time of the output pulse signal waveform becomes short, but on the other hand, ringing phenomenon is more likely to occur. and the entire pulse waveform is disturbed. Conversely, when the offset voltage is low, the collector-emitter voltage Vca decreases, so ringing does not decrease, but there is a problem that the rise/fall time becomes longer.

When the amplitude or offset voltage of the output pulse signal is changed in this way, the transition frequency fr of the transistors 1a and lb changes, so that the rise time/fall time and ringing phenomenon etc. are affected by the pulse period of the output pulse signal. It had the disadvantage that it could not be used in the problematic high frequency range.

Furthermore, transistors 1a and 1 constituting the differential logic circuit
When using a GaAsFET as b, the rated voltage between the drain and source of the FET is lower than the rated voltage between the collector and emitter of a general silicon transistor, so the variable range of the offset voltage in the output pulse signal is widened. There are some problems that cannot be solved.

In order to solve this problem, a pulse output device shown in FIG. 3 has been proposed. That is, the differential logic circuit 12
The collector of the transistor 11b is connected to the input terminal of the variable attenuator 14.

The output terminal of this variable attenuator 14 is connected via a capacitor 15 to an output terminal 161 which outputs an output pulse signal, and is also connected via an inductance 17a to a (-) side input terminal of a differential amplifier 18a of an offset control circuit 18. It is connected to the. Then, the (+) of this differential amplifier 18a is
) side input terminal is connected to one input terminal to which an offset control signal is input. Furthermore, the output terminal of this offset control circuit 18 is connected to the output terminal 16 via an inductance 17b.

Further, each transistor 11a of the differential logic circuit 12,
The emitters of the elements 11b are commonly connected to the constant current circuit 13.

In such a pulse output device, the output of the constant current circuit 13 is set to UA? First, the amplitude of the output pulse signal output from the differential logic circuit 12 is fixed at the maximum value. After the amplitude is attenuated by the variable attenuator 14, the AC component of the attenuated output pulse signal is guided to the output terminal 16 via the capacitor 15, and the DC component is transferred to the inductance 1.
It is input to the offset control circuit 18 via 7a. Then, the offset control circuit 18 outputs this DC component by superimposing it on a control signal to the offset controller 1 input from the input terminal 19, and sends it out to the output terminal 16 via the inductance 17b. Therefore, the final output pulse signal in which the AC component input via the capacitor 15 is superimposed on the DC offset voltage input from the offset control circuit 18 via the inductance 17b is output to the output terminal 16. Therefore, by adjusting the degree of attenuation of the variable attenuator 14, the amplitude of the output pulse signal output from the output terminal 16 can be varied, and by adjusting the offset control signal input to the input terminal 19, the offset voltage of the output pulse signal can be varied. It is possible to change the

Moreover, since the waveform, amplitude, and offset voltage of the pulse signal output from the differential logic circuit 12 are always constant, the amplitude of the circuit after the variable attenuator 14 is constant.

As long as the transmission characteristics such as phase maintain substantially flat frequency characteristics, the aforementioned characteristics such as rise/fall time are not affected by amplitude changes and offset voltage changes of the output pulse signal.

[Problems to be Solved by the Invention] However, even in the pulse output device configured as shown in FIG. 3, the following problems still need to be solved. In other words, the variable attenuator 14 for attenuating the output pulse output from the differential logic circuit 12 has a structure that changes the degree of attenuation in stages in consideration of frequency characteristics, etc., so that the degree of attenuation can be changed continuously. It was difficult to make changes. Although the above problem can be solved by setting a large number of attenuation degree change stages, this increases the equipment cost of the variable attenuator 14.

Further, the inductance 17a for separating the DC component of the pulse signal output from the variable attenuator 14 and the inductance 17b for combining the output signal of the offset control circuit 18 into the AC component have a limit on the low-pass frequency. Because signals containing frequency components cannot be transmitted completely,
There is a concern that a sag may occur in the output pulse signal waveform of the output terminal 16.

The present invention has been made based on the above circumstances, and its purpose is to reduce the amplitude and offset voltage of the output pulse signal over a wide frequency band from direct current to high frequency range so as to degrade the pulse waveform. The object of the present invention is to provide a pulse output device that can be varied to a large extent without any problems.

[Means for Solving the Problems] The present invention varies the offset voltage of a pulse signal output from a differential logic circuit using an externally inputted offset control signal, and also varies the offset voltage of a pulse signal output from a differential logic circuit using an externally inputted offset control signal. Accordingly, in the pulse output device configured to vary the amplitude of the pulse signal, the pulse signal is output in response to a pulse signal input from the outside, and the amplitude of the output pulse signal is controlled by the amplitude control signal. a pulse output circuit; a separation circuit that separates the output pulse signal of the pulse output circuit into an AC signal and a DC signal; and a separation circuit that adds the DC signal from the separation circuit, an inverted signal of the amplitude control signal, and the offset control signal. A bias control circuit is provided to output a bias control signal, and the bias control signal output from the bias control circuit and the AC signal from the separation circuit are superimposed and input to the differential logic circuit.

[Operation] With the pulse output device configured in this way, the pulse signal output from the pulse output circuit is separated into an alternating current signal and a direct current signal by the separation circuit. Then, the bias control circuit adds the offset control signal and the inverted amplitude control signal to the DC signal to obtain a bias control signal, which is superimposed on the separated AC signal and input to the differential logic circuit. .

Therefore, when the value of the amplitude control signal is changed, the current source control circuits of both the differential logic circuit and the pulse output circuit operate in the same direction, and the bias control signal of the bias control circuit operates in the opposite direction.

As a result, the amplitude of the pulse signal input to this differential logic circuit and the DC bias voltage change simultaneously, making it possible to continuously vary the amplitude of the output pulse signal and to always operate the differential logic circuit under optimal conditions. It is.

Also, since the offset control signal is input to the offset control circuit and also to the bias control circuit,
When the offset control signal changes, the bias control signal also changes in the same direction. However, even if the amplitude of the output pulse signal is kept constant and only the offset voltage is changed, the relative potential difference between the gate and drain of the FET in a differential logic circuit will not change. It is possible to operate with

Even if the amplitude and offset voltage of the output pulse signal are changed in this way, the pulse waveform is not adversely affected.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a circuit port showing the pulse output device of the embodiment.

This pulse output device is roughly divided into a pulse output circuit 21 that outputs a pulse signal in response to a pulse signal input from the outside, a current source control circuit 22 that controls the current source of this pulse output circuit 21, and a pulse output circuit 21 that outputs a pulse signal in response to a pulse signal input from the outside. A separation circuit 23 that separates a pair of pulse signals output from the output circuit 21 into a DC signal and an AC signal, respectively, and a bias control circuit 24 to which each DC signal separated by this separation circuit 23 is input.
A differential logic circuit 25 receives each bias control signal output from the bias control circuit 24 superimposed on each AC signal output from the separation circuit 23 and outputs an output pulse signal. The current source control circuit 26 controls the current source of the differential logic circuit 25, and the offset control circuit 27 applies an offset voltage to the differential logic circuit 25.

In the pulse output circuit 21, a pair of FETs 21a
, 21b are connected to each other and to the collector of a current control transistor 22a of the current source control circuit 22. Furthermore, the drains of each of the FETs 21a and 21b are grounded via load resistors 210 and 21d, respectively. Further, each gate of each FET 21a, 21b has substantially the same threshold voltage and amplitude, and input terminals 28a, 2 to which input pulses of different radial characteristics are input.
8b. And each FET21a, 21
The pulse signals output from each drain of b are sent to the separation circuit 2.
The signal is input to the respective capacitors 23a and 23b of No. 3, and is also inputted to the DC component detection circuits 29a and 29b each consisting of an integrating circuit via each resistor 23C923d. These DC component detection circuits 29a and 29b integrate the input pulse signal waveform at a constant period and extract the DC signal of this pulse signal waveform, and the mark rate of this pulse signal waveform,
The DC output signal level changes depending on the duty factor and signal level.

Each DC signal output from each DC component detection circuit 29a, 29b is input to a first input terminal of each analog adder 30a, 30b having four input terminals in bias control circuit 24. The fixed bias voltage output from the fixed bias voltage generation circuit 31 is input to the second input terminal of each adder 30a, 30b.
The amplitude-controlled 611 signal inputted from the input terminal 32 is inverted in polarity by an analog inverting circuit 33 and inputted as an inverted signal to the third input terminal. Furthermore, each adder 30
The offset control signal input from the input terminal 34 is input to the fourth input terminals a and 30b.

Signals inputted from the four input terminals of each adder 30a, 30b are added and output as each bias control signal, and each FET 25a, 24b constituting the differential logic circuit 25 is connected via resistors 24a, 24b. applied to each gate. Incidentally, each AC signal of each pulse signal outputted from the separation circuit 23 via each capacitor 23a, 23b is also superimposed and applied to each of these gates.

An offset voltage output from an offset control circuit 27 composed of a differential amplifier 27a, a current booster 27b, etc. is applied to each drain of the FETs 25a and 25M of the differential and dynamic logic circuit 25 via resistors 25c and 25d, respectively. has been done. Furthermore, the drain of the FET 25b is connected to an output terminal 35 that outputs an output pulse signal of this device.

Further, the sources of the FETs 25a and 25b are commonly connected to the collector of a current limiting transistor 26a in the current source control circuit 26. The emitter of this transistor 26a is connected to a DC power supply (-VE) via a resistor 26b. The base of the transistor 26a is connected to two Zener diodes 26C and 26C of polarity shown in the figure.
It is connected to the output terminal of the differential amplifier 26e via 26d. The (+) side input terminal of the differential amplifier 26e is connected to the amplitude control signal input terminal 32 via a resistor 26f, and to the (-VE) DC power supply via a resistor 26j. (-) side input terminal is transistor 2
Dividing resistor 26C1 inserted between the emitter of 6a and ground
, 26h.

Also, a pair of Zener diodes 26c connected in series
, 26d is connected to the base of a transistor 22a in the current source control circuit 22 of the pulse output circuit 21.

Further, the input terminal 34 to which the offset control signal is input is each adder 30a of the bias control circuit 24.

30b, and the (+
) side input terminal.

In the pulse output device configured in this way, the amplitude of the output pulse signal outputted from the differential logic circuit 25 via the output terminal 35 is controlled by the current source controlled by the amplitude control signal inputted from the input terminal 32. Since it is the product of the source current I8 determined by the control circuit 26 and the load resistance 25d,
By changing the amplitude control signal input to the input terminal 32, the amplitude of the output pulse signal can be changed. Furthermore, when the level of the offset control signal input from the input terminal 34 is changed, the offset voltage output from the offset control circuit 27 changes to each F of the differential logic circuit 25.
A resistor 25 connected to each drain of ET25a, 25b
c and 25d, the offset voltage of the output pulse signal changes.

Here, the amplitude control signal inputted from the input terminal 32 is inputted to the current source control circuit 26 of the differential logic circuit 25, and is inverted by the inverting circuit 33, and then sent to the bias control circuit 24.
is input to each adder 30a, 30b. therefore,
The gate voltage of each FET 25a, 25b changes in the opposite direction to the changing direction of the amplitude control signal. As a result, by changing the amplitude control signal at the input terminal 32 while keeping the offset voltage of the output pulse signal constant, only the amplitude can be changed, for example, from Vl to V.
2 (Vl<v2), FET25a, 2
The gate voltage of 5b operates to be a voltage lower by (V+-V2) than the voltage when the amplitude is vl.

That is, the gate voltage is changed so that the drain-gate voltage VD is increased for a large amplitude of the output pulse signal, and conversely, the drain-gate voltage VD4 is decreased for a small amplitude. Therefore, FET25
Drain-source voltage VDS when conduction of a and 25b
The changes in the gain and phase characteristics (transition frequency ft) in the high frequency region are also reduced. As a result, even if the amplitude of the output pulse signal changes significantly, there is little disturbance in the waveform of the output pulse signal.

On the other hand, the offset control signal input from the input terminal 34 is input to the offset control circuit 27 and to each adder 30a of the bias control circuit 24.

30b, so if you want to change the offset voltage while keeping the amplitude of the output pulse signal constant, each FET
The voltages 25a and 25b change in the circumferential direction in synchronization with the change in the set voltage.

Therefore, each FET 25a of the differential logic circuit 25.

The drain-to-gate voltage VD of 25b remains approximately constant regardless of changes in the offset voltage of the output pulse signal.

Therefore, the gain and phase characteristics (transition frequency fr) of the FETs 25a and 25b in the high frequency range do not change, so the rise/fall time of the output pulse signal waveform does not change. As a result, even if the amplitude is changed, the output pulse signal waveform will not be disturbed.

In this way, the bias control circuit 24 controls the pulse output circuit 2
The differential logic circuit 25 follows the level fluctuation of the DC signal of the pulse signal input from the differential logic circuit 25, and always maintains an optimal bias for changes in the offset voltage and amplitude of the output pulse signal output from the differential logic circuit 25. It has a function of supplying gate voltage to each FET 25a, 25b so as to maintain the conditions.

Further, the AC signal from the separation circuit 23 and the DC bias control signal from the bias control circuit 24, which are input to the differential logic circuit 25, are combined without using an inductance,
Moreover, each adder 30a, 30b of the bias control circuit 24
Since the output impedance of is set to a very high value,
Each gate circuit of each FET 25a, 25b of the differential logic circuit 25 operates in a wide range from direct current to a high frequency region.

Generally, in order to obtain a large amplitude output pulse signal from the differential logic circuit 25, the amplitude of the pulse signal input to each gate of each FET 25a, 25b must be set relative to the amplitude of the resulting output pulse signal. needs to become larger. The amplitude control signal input from the input terminal 32 is divided by the Zener diodes 26C and 26d in the current source control circuit 26 and applied to the base of the current control transistor 22a of the current source sub-circuit 22 of the pulse output circuit 21. Therefore, the amplitude of the pulse signal output from the pulse output circuit 21 can be controlled by i++ by the amplitude control signal, so that the above condition can be easily satisfied. Moreover, since the rate of change is lower than the rate of change of the output pulse signal of the differential logic circuit 25, the waveform of the pulse signal output from the pulse output circuit 21 is changed from the rise/rise caused by the change in the transition frequency fr. Changes in fall, duty factor, ringing, etc. can be minimized.

Note that although the present invention is provided with DC component detection circuits 29a and 2.9b consisting of an integrating circuit in order to detect the DC component of the pulse signal output from the pulse output circuit 21, the pulse signal input to the pulse output circuit 21 When the mark rate and duty factor of the signal are constant, the DC signal of the pulse signal output from the pulse output circuit 21 is a constant value, so by using the fixed bias voltage generation circuit 31, the DC component is It is also possible to eliminate the detection circuits 29a, 29b.

[Effects of the Invention] As explained above, according to the pulse output device of the present invention,
The amplitude and offset voltage of the output pulse signal can be varied significantly over a wide frequency band from direct current to high frequency regions without deteriorating the pulse waveform.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a pulse output device according to an embodiment of the present invention, and FIGS. 2 and 3 are circuit diagrams showing conventional pulse output devices, respectively. 21--Pulse output circuit, 21a, 21b. 25a, 25b-FET, 22.26-fii flow source control circuit, 23... Separation circuit, 23a, 23b... Capacitor, 24... Bias sub-part circuit, 25... Difference IjJ logic circuit, 27...Offset control (1 circuit,
29a. 29b...DC component detection circuit, 30a, 30b...
Adder, 31...Fixed bias voltage generation circuit, 33.
...Inversion circuit. Applicant's Representative Patent Attorney Takehiko Suzue Figure 2 VE 3rd Stage

Claims (1)

[Scope of Claims] A differential logic circuit (25); and an offset control circuit (27) that variably controls the offset voltage of a pulse signal output from the differential logic circuit in response to an offset control signal input from the outside. and; a current source control circuit that variably controls the amplitude of the pulse signal output from the differential logic circuit by controlling the current source of the differential logic circuit in response to an amplitude control signal input from the outside. 26) In a pulse output device that outputs a pulse signal input to the differential logic circuit with a desired offset voltage and amplitude: outputs a pulse signal in response to an externally input pulse signal, and a pulse output circuit (21) in which the amplitude of the output pulse signal is controlled by the amplitude control signal; a separation circuit (23) that separates the output pulse signal of the pulse output circuit into an AC signal and a DC signal; a bias control circuit (24) that adds and outputs the DC signal from the separation circuit, an inverted signal of the amplitude control signal, and the offset control signal; A pulse output device characterized in that the alternating current signal from the separation circuit is superimposed and input to the differential logic circuit.