JPH0217881A - Speed control device of motor - Google Patents

Abstract

PURPOSE:To obtain sufficient speed control even at a low speed by increasing the resolution of a pulse generator by n-times and at a low speed by setting the speed set value by n-times leaving the output from the pulse generator as it is. CONSTITUTION:The pulse number of a pulse generator 3 is converted into a speed signal with an F/V converter 4 and the output of a speed setter 5 is converted into a speed command signal with a D/A converter 6. The deviation signal between the speed command signal and the speed signal is supplied to a motor 2 through a speed regulator 7 and a thyristor converter 1. Here, let the resolution of the pulse generator 3 be n-times. At a high speed, contacts 82A and 82D are closed and the output of the speed setter is set by one(1) time. At the same time, the pulse signal is divided by 1/n. On the other hand, at a low speed, the contacts 82B and 82C are closed and the output of the speed setter 5 is increased by n-times, while the pulse signal is divided by 1/1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a speed control device for an electric motor, and particularly to an improvement thereof.

[Conventional technology]

Conventionally, this type of speed control device includes one in which a digitally adjustable speed setting value of an electric motor is converted into an analog value using a D/A converter, and a pulse generator (
The actual speed value from PLO) is converted into frequency/voltage (F/V)
There is a known system that performs control by using an analog speed regulator to detect the deviation from the analog value converted by a converter.

[Problem that the invention attempts to solve]

By the way, such a speed control device is used for applications that require extremely low speed setting and detection, such as winding (winding) of paper equipment.
(return) machine, the maximum speed should be set to 2400 (m/m
1nl, 15 (m/min) at low speed (one inching paper)
), and if the maximum diameter of the diameter is 3 m and the spool diameter (minimum diameter) is Q, 6 m, the motor rotation speed at low speed (maximum diameter) is 100% of the motor rotation speed at maximum speed (spool aging). As, it becomes.

Generally, the control range of an analog speed control device is 1:100, depending on the accuracy of the F/V converter that converts the pulse signal of the pulse generator (PLO) into analog voltage.
(1 to 100% of the maximum rotation speed), or -
Digital-analog CD used for boat fishing configuration circuits
/A) The error generated in the converter is about ±0.1%. Therefore, this error is too large to obtain sufficient accuracy at low speeds (0.1
/Q, 125 x 100%).

Therefore, an object of the present invention is to provide a speed control device that can maintain sufficient speed accuracy even at low speeds.

[Means to solve the problem]

a first conversion circuit for converting a digitally adjustable speed set value of the electric motor into an analog quantity; a second conversion circuit for converting a pulse signal from a pulse generator proportional to the actual speed value into an analog quantity; The resolution of the pulse generator is set to n (a natural number ) When doubled, the output pulse is divided by 1/1.

A first output means outputs the frequency divided by one of 1/n, and a second output means divides the set value by either 1 or n and outputs the set value. The output pulse from the pulse generator is frequency-divided by 1/1 by the first output means, and the speed setting value is multiplied by n by the second output means to perform speed control.

[Effect]

PLG at maximum rotational speed due to F/V converter specifications
Since the maximum number of pulses is determined, F
/V converter cannot obtain sufficient accuracy. Therefore, P.L.G.
By increasing the resolution of Sometimes the frequency is switched to 1/1 to obtain n times the normal number of pulses, allowing the F/V converter to be used within sufficient accuracy. Note that at this low speed, the speed detection value is n times as high, so the set value is switched to n times. In this way, the error occurring in the digital-to-analog converter can also be reduced by multiplying the setting 1[iA by n, A±[11
% to AXnfo to 1%, making it possible to obtain sufficient setting accuracy.

However, since the gain of the multi-speed regulator changes when the wood is changed, a separate correction is required.

〔Example〕

The figure shows an embodiment of this invention, where 1 is a thyristor converter, 2 is a motor, and 3 is a pulse generator (PLG).
, 4 is F/V that converts the output of PLG3 to analog voltage.
converter; 5 is a speed setting device; 6 is a D/A converter that converts the digitally set speed setting value into an analog voltage;
7 is a speed regulator. Note that everything up to this point is the same as the conventional one, and therefore, the present invention includes multipliers 81A, 81B, contacts 82A-82D, and frequency dividers 83A, 8! It is characterized by the addition of a low-speed compensator 8 consisting of an IB.

The low speed compensator 8 closes the contacts 82A and 82D when the speed is high, and performs the same operation as before, and when the speed is low, the contacts 82B and 82D close.
82C is closed, and the speed setting value given through the setting device 5 is multiplied by n, while the pulse signal corresponding to the speed detection value given through the PLG 3 is divided by 1/1, so that the normal n (natural number) is ) to obtain double the number of pulses to obtain sufficient speed accuracy.

In this case, it is necessary to increase the resolution of the PLG 3 by n times in advance, and since the gain of the speed regulator 7 changes between high speed and low speed, this can be corrected separately using an appropriate method. It becomes necessary. Furthermore, a means for determining daytime speed and low speed is also required, but this is omitted in and.

〔Effect of the invention〕

According to this invention, the resolution of the PLG is increased by n times, and when the speed is low, the output of ° from this PLG is set to ix, and the speed setting value is increased by n times, so the conventional speed control device is significantly modified. Sufficient accuracy can be maintained even at low speeds.

[Brief explanation of the drawing]

The figure is a block diagram showing an embodiment of the invention. Description of symbols 1...Thyristor converter, 2...Motor, 6...Pulse generator, 4...
・F/V converter, 5...Speed setting device, 6...
...D/A (digital/analog) converter, 7.
... speed regulator, 8 ... low speed compensator,
81A, 81B... Multiplier, 82A to 82D.
... Contact, 83A, 831a ... Frequency divider. Agent Patent Attorney Akio Namiki Agent Patent Attorney Kiyoshi Matsuzaki

Claims (1)

[Scope of Claims] A first conversion circuit that converts a digitally adjustable speed set value of the electric motor into an analog quantity, and a second conversion circuit that converts a pulse signal from a pulse generator proportional to the actual speed value into an analog quantity. A speed control device for an electric motor, comprising: a conversion circuit; and a regulator that performs a predetermined adjustment calculation based on the deviation between the output of the first conversion circuit and the output of the second conversion circuit, wherein the resolution of the pulse generator is a first output means for multiplying the set value by n (a natural number) and dividing the output pulse by either 1/1 or 1/n; a second output means for outputting either one of the multiplied speeds, and when the speed is low, the first output means divides the output pulse from the pulse generator by 1/1, and the second output means outputs the speed setting value. A speed control device for an electric motor, characterized in that the speed is controlled by multiplying the speed by n.