JPH02178739A - System for avoiding fault of micro processor - Google Patents

Abstract

PURPOSE:To avoid the fixed fault of a micro program by exchanging a micro program step with a micro program step which has been set in a fault microregister when the fixed fault of the micro program occurs. CONSTITUTION:When the fixed fault has occurred in the micro program, the check bit of a check register 2 concerned is made effective, and the normal microprogram is set in the fault microregister 12. The check bit is referred to when the micro processor is operated and the microprogram of a fault part is executed. Thus, the fault microregister 12 is selected in a fault microselector 5, and the content of the fault microregister 12 is executed instead of the microprogram where the fault has occurred, whereby the fault can be avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for avoiding fixed failures in a microprocessor, and more particularly to a method for avoiding fixed failures in a microprogram built into a microprocessor.

[Prior Art] Conventionally, in a microprocessor with a built-in microprogram, even if a fixed failure occurs in the microprogram, no measures are taken to avoid the problem.

[Problem to be solved by the invention] For this reason, when a -degree fixed failure occurs, if the system is in operation, the system structure must be changed to one that does not use the microprogram routine where the failure has occurred, or the system operation itself must be changed. It has to be stopped. Furthermore, if a fixed failure occurs during evaluation, it becomes difficult to proceed with the evaluation because it becomes impossible to move the microprogram beyond the failure location.

In this way, when a fixed fault occurs in the microprogram of a conventional microprocessor, there is no workaround, so the only way to remove the fixed fault is to rework the microprogram, which takes a long time. As a result, system operation and evaluation are greatly hindered.

[Means for Solving the Problems] A fault avoidance method for a microprocessor according to the present invention includes a microprocessor that has a microprogram built into its main body and has a microprogram latch that latches one step of the microprogram corresponding to a microaddress. a check register that can be rewritten by the microprogram and has check bits corresponding to each step of the microprogram; a check selector that selects one check bit in the check register from the microaddress; a check latch that holds a checked check bit for a certain period of time; a fault microregister that can be rewritten by the microprogram and has the same bit width as one step of the microprogram and that holds a fault avoidance microprogram; A failure micro selector receives the contents of the register and the contents of the microprogram latch, and selectively outputs the contents of the failure microregister when the contents of the check latch are valid, and selectively outputs the contents of the microprogram latch when the contents are invalid. and when a fixed fault occurs in the microprogram, enable the corresponding check bit in the check register, set a normal microprogram in the faulty microregister, and then operate the microprocessor to eliminate the fault. When executing the microprogram at the location,
By referring to the check bit, the faulty microregister is selected by the faulty microselector, and the contents of the faulty microregister are executed in place of the faulty microprogram, thereby making it possible to avoid the fault. It is characterized by being configured as follows.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. Check register 1 is a microprogram ROM
This register has a number of bits equal to the number of steps of 7, and if the data length of MBUS42 used as a data bus for reading and writing check register 1 is, for example, 32 bits, then the register
Consists of 0 pieces. The check register controller 2 controls the check registers CHK RO to CHK R (n-1) specified by the MD-bus 39 indicating the destination register specified by the microprogram or by the MS-bus 40 indicating the source register.
It controls reading and writing from BUS42. Each bit of the check register is checked by check selector 3.
One bit selected by the micro address (MA) 34 is held in the check latch circuit 4,
It is input to the failure micro selector 5 as a FAIL signal 24.

In addition, a signal (MLCH signal) 36 obtained by latching one step of the microprogram corresponding to the micro address (MA) 34 and the contents of the fault micro register (FMREG) 12 are input to the fault micro selector 5 . The failure micro selector 5 outputs the MLCH signal 36 to the data line 27 when the FAIL signal 24-0 is present,
When the FAIL signal 24-1 occurs, the contents of FMREG are output to the data line 27.

A buffer (BUFFER) 11 holds the microprogram output to the data line 27 for one clock,
This retained microprogram is distributed to various parts of this microprocessor through the MD bus 6. Predecoder 10 decodes the contents of data line 27 and provides control signals 25, 37, 38 for controlling the present microprocessor.
generate.

The micro address controller (MARCNT) 6 is
Every time a microprogram is executed, a microaddress for the next microprogram to be executed is generated, and the address line (MA) 34 is used to store the microprogram ROM (
It becomes an input to MROM) 7 and ROM selector (MSEL) 8, and selects one step in MROM 7.

Now, when there are no fixed faults and normal operation is performed, check register 1 is all 0'', which causes the MST
FA output from check latch circuit 4 by 828
The IL signal 24 is always "0". After all, the faulty micro selector 5 always sends the output from the micro latch 9 to the predecoder 10 and buffer 11, so that the MROM
The 7-width microprogram is executed sequentially to perform normal operation.

Next, we will show the operation when a fixed failure occurs. Now, suppose that a fixed failure occurs at address 100 of the microprogram. At this time, from the microprogram initialization routine or software initialization routine, “l” is sent to bit O of CHKR8 of check register 1 via MBUS42.
”.

Furthermore, a new fault avoidance microprogram to be executed at address 100 is set in the fault microregister 12 by the same means.

When trying to execute microprogram address 100 after system startup, first, microaddress MA-
100, and the microprogram at address 100 from MROM7 is selected. At the same time, the check selector 3 selects bit 0 of CHKR8 as shown in FIG.
828 works, and the microprogram and check bit at address 100 are latched into MLCH9 and CHKLCH4. The check pit latched to CHKLCH4 is '
1'', the fault micro selector 5 is set to F.
The contents of MREG 12 are selected and the failure avoidance microprogram set in FMREG 12 is output to predecoder 10 and buffer 11. The predecoder 10 and buffer 11 judge and operate this fault avoidance microprogram as if it were a normal microprogram.

In this way, fixed fault avoidance processing can be performed by replacing the microprogram step in which the fixed fault has occurred with the microprogram in the faulty microregister.

[Effects of the Invention] As explained above, when a fixed fault occurs in a microprogram, the present invention replaces this microprogram step with a microprogram step set in the faulty microregister, thereby eliminating the fixed fault in the microprogram. This has the advantage that the operation of a system using this microprocessor and the evaluation of this microprocessor can be continued without any hindrance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a truth table showing the operation of a check selector. DESCRIPTION OF SYMBOLS 1...Check register, 2...Check register controller, 3...Check selector, 4...Check latch, 5...Failure micro selector, 6...
・Micro address controller, 7...Micro R
OM, 8...Micro ROM selector, 9...Micro ROM latch, 10...Predecoder, 11...
・Microbuffer.

Claims (1)

[Scope of Claims] 1. A microprocessor that has a microprogram built into its main body and has a microprogram latch that latches one step of the microprogram corresponding to a microaddress, which can be rewritten by the microprogram and that can be rewritten by the microprogram. A check register having a check bit corresponding to each step, a check selector that selects one check bit in the check register from a microaddress, and a check latch that holds the check bit selected by the check selector for a certain period of time. , a failure microregister that can be rewritten by the microprogram, has the same bit width as one step of the microprogram, and holds a failure avoidance microprogram, and receives the contents of the failure microregister and the contents of the microprogram latch. ,
and a fault micro selector that selectively outputs the contents of the fault micro register when the contents of the check latch are valid, and selectively outputs the contents of the micro program latch when the contents are invalid, and a fixed fault has occurred in the micro program. Sometimes, after enabling the corresponding check bit of the check register and setting a normal microprogram in the faulty microregister, when operating the microprocessor and executing the faulty microprogram,
By referring to the check bit, the faulty microregister is selected by the faulty microselector, and the contents of the faulty microregister are executed in place of the faulty microprogram, thereby making it possible to avoid the fault. A failure avoidance method for a microprocessor, characterized in that it is configured as follows.