JPH02178715A - Control system for reactive power compensator - Google Patents

Abstract

PURPOSE:To reduce a higher harmonic by phase-controlling a device based on a control signal which is biased so that it subtracts the added value of signals equivalent to respective capacities of certain compensators when plural numbers of reactive power compensators are operated. CONSTITUTION:Plural reactive power compensators are constituted, and a reactive power detection signal from a fluctuation load 4 is used as it is for the phase control of a thyristor 12 in the compensator in the first reactive power compensator SV, and the control signal which is biased so that it subtracts the signal equivalent to the capacity of the first reactive power compensator SVC 1 from the reactive power detection signal is used for the phase control of the thyristor 22 of the compensator in the second reactive power compensator SVC 2. Thus, the generating higher harmonic which occurs can be reduced by sequentially and simultaneously executing said operation.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a reactive power compensator (hereinafter abbreviated as SVC) for the purpose of suppressing flicker and voltage fluctuations generated from arc furnaces, welding machines, and other fluctuating loads. When operating multiple SVCs, the flicker suppression effect remains the same as before, but
The present invention relates to a control method for a reactive power compensator that can reduce harmonics generated by SVC.

[Prior Art] Fig. 5 shows a control block diagram in the case of conventional 5V (1!2 unit operation).

1 is a power supply, 2 is a power supply impedance, and 3 is a system bus to which flicker and voltage fluctuations (hereinafter referred to as flicker) are to be suppressed, to which equipment 5YCI%5VC2 shown at 10.20 is connected. 5 is C that detects the current of the fluctuating load shown in 4.
6 is an FT that detects the voltage of the system bus 3.

5vct and 5YC2 have exactly the same configuration.

Reference numerals 13 and 23 denote reactive power Q detectors, which are circuits that detect the Q of a fluctuating load at high speed at a DC level. 14.24 is Q
SvC based on the Q signal detected by the detector 13.23
A circuit that determines the thyristor firing phase of Is, 25
is the pulse generation circuit that actually fires the thyristor shown at 12.32, and the pulse signal 16.28 is the pulse generation circuit that actually fires the thyristor shown at 12.32.
．． It is sent to gate 32 and ignited.

In this case, the phase of the thyristor 12.32 is controlled so that the combination of the variable load Q and the SVC Q is constant.

In the above example, the two 5VC1 and 5VC2 are as if they were 1
It operates like a standard SVC and suppresses flicker. However, phase control of the thyristor current inevitably generates harmonics. The amount of harmonics generated is
Although it varies depending on the capacity of each SYC, harmonics are generated in the same proportion relative to the rated capacity of each SYC.

[Structure of the Invention] As described above, when multiple SYCs are operated for the purpose of suppressing flicker and voltage fluctuations generated from fluctuating loads, the present invention is capable of controlling the conventional multiple thyristor control system as described above. This was done for the purpose of reducing harmonic components generated by the thyristor, and from a different perspective,
When suppressing flicker and voltage fluctuations by SYC operation of multiple units, it is possible to reduce harmonic components by dividing and using multiple units of SvC.
Sv with a capacity that can cope with the flicker and voltage control in C
In the control of the first SYC, the load detection signal is used as it is based on the load detection signal, and in the control of the second SvC, a signal corresponding to the capacity of the first SVC is subtracted from the load detection signal. Based on the biased control signal, the phase of the SvC is controlled based on the biased control signal so that in the next SvC control, the sum of the signals corresponding to each capacitance of the previous SVC is subtracted. It is.

The present invention will be explained below with reference to embodiments shown in the drawings.

FIG. 1 shows an embodiment of the invention. The same parts as in FIG. 5 are given the same reference numerals.

A system bus 3 to be suppressed is connected to a power supply 1 having a power supply impedance 2, and equipment 5VCI and 5VC2 are connected corresponding to the variable load 4 connected to the bus 3. The control circuits of this 5m'CI and 5VC2 are P
Equipped with a reactive power Q detector 13.23 that receives voltage and current from T8 and C70, the output Q signals are respectively input to pulse phase determination circuits 14.24, and the output signals are gate pulse generation circuits Is and 25. The output signal from the gate pulse generating circuit Is, 25 is the ignition of the SVC main circuit which is connected in series with the high impedance transformer 2, 21 or the reactor and the thyristor 12, 22 connected in pure anti-parallel. given to the pole. Up to this point, there is no difference from the one in FIG. 5, but in this example, between the 5VC2 reactive power Q detector 23 and the pulse phase determining circuit 24, a DC bias equivalent to a 5VC1 capacity is applied from the bias setting device 27. It is biased to be subtracted from the output signal of the Q detector 23 of the variable load 4.

This bias setting device 27 may be connected to the 5VCI side. However, in this case, the bias setting value is determined by the capacitance of 5VC2.

Here, in the case of the two SVCs explained above, 5VCI and 5Y
The description will be made assuming that the capacities of C2 are equal and the total capacity of the two units is equal to the maximum ineffective capacity of the load.

Figure 3 (Mu), (B), (C), (D), (E), (F
) indicates an example of operation.

In (m), ■ indicates the reactive power fluctuation of the load, and SVC
controls the phase of SvC to generate the @ part.

As a result, as shown in (B), reactive power is generated from the SyC, but in conventional control, the reactive power in (B) was generated by two units as shown by the dotted line.

(C) is a 5vci Q control signal (pulse phase determination circuit 1
4 input signal). 5YCI controls to generate the reactive power indicated by the oblique line O based on this signal.

The results are shown in (D).

(E) is a Q control signal of 5YC2, and in order to bias the signal corresponding to the capacitance of svct as described above, such a signal is input to the pulse phase determining circuit 24. Therefore, the phase of 5YC2 is controlled so as to generate the reactive power shown in (E) (■), and as a result, the reactive power shown in (F) is generated.

5VCI (7) reactive power (D) and 5VC2 reactive power (
F) (0 or exactly the same as the reactive power (B) of the conventional SvC, so the reactive power compensation, that is, the flicker suppression effect, is the same as the conventional one.

However, when considered from the perspective of harmonic generation, the fourth
As shown in Figures (A) and (B), the point at 50% of the total SvC capacity [(1) in Figure 3 (B) and (D) and (F) (
Looking at the schematic diagram of the current waveform of (eye) + (eye 1), in the conventional example, the SVC capacity cannot be reduced unless the firing angle β is increased, but in this example, the SVC1 has a current waveform of is zero, and 5VC2 is fired when β=small. β is close to the small fundamental wave current, so harmonics can be reduced.

If β of full current is β = 34°, at the 50% current point, the third harmonic is approximately 70% of the conventional value, and the fifth harmonic is approximately 25% of the conventional value.
%, and can be reduced to about 60% for the seventh harmonic.

The embodiment shown in FIG. 2 shows control by three SVCs; therefore, one series of Q detectors 33, pulse phase determining circuit 34,
, a 5YC in which the gate pulse generation circuit 35 consists of a high impedance transformer 31 and a pure anti-parallel connected thyristor 33.
The bias setting device 37 is prepared for the main circuit of No. 3 and connected to the Q detector 33 and the pulse phase determining circuit 34.
A DC bias equivalent to VCI +'5 VC2 capacity is set.

5VCI without Q signal from fluctuating load.

5VC2 and 5VC3 are operated at the maximum allowable capacity,
As the Q signal increases, thyristor phase control is performed only on svc+, and when the Q signal further increases, 5YCI is paused, and thyristor phase control is performed only on 5YC2, and when the Q signal further increases, 5YCI, 5YC2 is stopped, and only 5VC3 is operated on the phase side of the thyristor.

Looking at the operating conditions of 5yct, 5YC2, and 5ycs between the two, the syc whose variable phase is controlled at a certain point by a change in the Q signal is either 5YCI - 5YC3, and excluding this < SVC is full state or in a state of rest. Therefore, since this state is always maintained, harmonic generation is reduced in the entire device.

[Effects of the Invention] As explained above, according to the control method of the present invention, the SVC
Flicker control is the same as before by operating multiple units, but harmonics generated by SYC can be reduced.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 and 2 show embodiments of the present invention. 3(A) to 3(F) show diagrams for explaining the operation of the apparatus shown in FIG. 1. Figure 4 (A) shows the SVC at point (1) in Figure 3 (B).
3B shows the SVC current waveform at point 01) in FIG. 3D and point 1 in FIG. 3F. FIG. 5 shows a control explanatory diagram of a conventional reactive power compensator using a plurality of units. 3...System bus, 4 river fluctuating load, 10, 20.30.
...5VC1,2,3,11,21,31...High impedance transformer, 11.21.31...Thyristor with pure anti-parallel connection, 13,23.33...Reactive power Q detector, 14,24.34...Pulse phase determining circuit, I
s, 25.35...Pulse generation circuit, 18.28,3
18... Thyristacate pulse, 27.37...
Bias setting device. To SV 2 Juicuzu: 3V%;

Claims (1)

[Claims] (1) A plurality of reactive power compensators are configured to operate for the purpose of suppressing flicker and voltage fluctuations. The second reactive power compensator outputs a biased control signal so as to subtract a signal corresponding to the capacity of the first reactive power compensator from the reactive power detection signal to the thyristor of the second reactive power compensator. It is used for phase control, and furthermore, in the next reactive power compensator, a biased control signal is sent to the thyristor of the device so as to subtract the sum signal of the signals corresponding to the capacities of the previous reactive power compensator. A control method for a reactive power compensator characterized by reducing harmonics generated from its own equipment (SVC) using a phase control method.