JPH02176975A - Automatic wiring method for printed board - Google Patents

Abstract

PURPOSE:To enable efficient wiring by detecting an empty cell amount four cell groups which constitute a search-directional square area including a wired cell, correcting wiring passed through the empty cell into a wired state, and rewriting the cell which is already wired into an empty cell. CONSTITUTION:Wiring information showing a connection relation with an adjacent cell, wiring inhibition information, and emptiness information are written in each cell and when a state wherein a search can not be made because the wired cell C1 is present in the search direction is detected, the cell groups C1 - C4 which constitute the square area in the search direction including the wired cell C1 are extracted. The empty cell C4 is detected among those cell groups, the wiring passed through the empty cell C4 is corrected into a wired state, and the wired cell C1 is rewritten into an empty cell. Consequently, even if there is wiring which causes the trouble of a search, a search point is advanced avoiding the wiring, so high-density printed board wiring can be generated.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method for automatically searching for wiring routes in a printed board CAD device.

To explain further, the purpose is to improve the wiring rate in automatic wiring.

<Conventional technology> Printed board CA that automatically designs printed circuit board wiring
The D device inputs component data and connection data of the electronic circuit mounted on the printed circuit board, and forms cells on the storage device by dividing the printed circuit board into meshes based on the input data. A cell is a small square area created by equally dividing the wiring area of a printed circuit board vertically and horizontally at the wiring grid interval (2.5415+ui when passing two wires between IC bins), and is the minimum unit for route searching. be. For each cell, check whether there is already wiring on the component side and solder side of the printed circuit board.

The presence or absence of pins, the presence or absence of through holes, the presence or absence of wiring prohibition, and information on vacancies are written from the CPU of the printed board C^0 device. The set of cells formed in this way is expressed as a cell map (
Route searching in a printed circuit board CAD device (also called a board model) is to find a series of empty cells that connect two given points, that is, a cell at a starting point and a cell at an end point.

FIG. 12 and FIG. 13 are examples in which a part of the Japanese pine 1 is extracted. In Figure 12, there is a series of empty cells connecting the starting point and the ending point, so you can search for the route indicated by the dotted line in the figure.
In FIG. 13, there is no series of empty cells connecting the starting point and the ending point due to the existing wiring found in the previous search.

In addition, in a normal printed board CAD device, for example, all wiring patterns applied to the component side of the printed board are oriented horizontally (or vertically), and all wiring patterns applied to the solder side are oriented vertically (or horizontally). ) (that is, all patterns formed on the same surface are parallel), the CAD apparatus described in this specification is also assumed to be a similar apparatus.

However, even if we say that the entire pattern is in the horizontal direction (or vertical direction), it is possible for the pattern to fluctuate within the width of several cells (corresponding to the search width) rather than in the strict horizontal direction (#1 direction). It is something. FIG. 14 shows a width of 3 cells, and although the wiring pattern indicated by dotted lines has a vertical component, it falls within the scope of the horizontal pattern referred to here.

<Problems to be Solved by the Invention> The conventional automatic wiring method as described above, as shown in FIG. He concluded that there was no way to do so. Therefore, even if the existing wiring discovered in the previous route search step is not appropriate and the route to be searched this time is obstructed by the existing wiring, the search is made impossible. Therefore, even if there are many empty cells, it may not be possible to search them, and there is room for improvement in wiring efficiency.

An object of the present invention is to provide a printed circuit board automatic wiring method that can push aside a pre-wired route that becomes an obstacle on the way between a starting point and an end point and proceed with the route search. be.

Means for Solving the Problems> In order to solve the above problems, the present invention provides information for inputting component data and connection data of an electronic circuit mounted on a printed circuit board to a central processing unit (hereinafter referred to as CPU). An input device, a storage device, and a collection area of cells obtained by subdividing the printed circuit board into a mesh based on the input data are written in the storage device, two cells to be connected are selected, and the two cells are connected. In an apparatus for automatically creating a wiring pattern of a printed circuit board, the apparatus is equipped with a CPU that determines a search direction for a route to search for, and writes wiring information and component placement information to each cell, and automatically creates a wiring pattern for a printed circuit board. Existing wiring information (a cell to which this information is written is called an existing wiring cell) that represents the connection relationship between The first step is to write into each cell a blank cell indicating that it can be wired (a cell with a fixed fault is called a fixed fault cell), and empty information indicating that it can be wired (a cell in which this information is written is called a blank cell). Step 2 of detecting that the search cannot proceed because of (C1) ，
Step 3 of extracting cell group (C3, C4) and this cell group (C1,
Step 4: Detecting a blank cell (C4) from among C2, C3, C4), modifying the existing wiring to route through this blank cell (C4), and rewriting the already wired cell (C1) to a blank cell. and step 5 of proceeding with the search route to this newly rewritten blank cell.

The following measures were taken.

Effect> In the present invention, in step 1, connection information to adjacent cells is also written in each cell. Therefore, the CPU can know the mutual connections among the four cells extracted in step 3.

Then, if one of the four cells is a blank cell, in step 4, the existing wiring is corrected to the wiring that passes through this blank cell, and the already-wired cell causing the problem is rewritten to a blank cell.

Therefore, there are no faulty cells and the search can proceed.

<Example> Hereinafter, the present invention will be explained in detail using the drawings.

Fig. 1 is a flowchart showing a printed circuit board automatic wiring method according to the present invention, Fig. 2 is a diagram showing an embodiment of a printed board CAD device to which the method of the present invention is applied, and Fig. 3 is a diagram showing a cell map and storage of each cell. FIG. 4 is a diagram illustrating an example of the connection relationship in each cell, and FIGS. 5 and 6 are diagrams illustrating an example of a case where it becomes an obstacle to route search. , FIGS. 7 to 10 are diagrams showing the steps of proceeding with route searching according to the present invention.

The configuration of a printed board CAD device to which the present invention is applied will be described with reference to FIG. In the figure, reference numeral 1 denotes an information input device, which inputs component data and connection data of an electronic circuit mounted on a printed circuit board to a central processing unit (CPtl) 3 via an input/output interface 2. To describe this information input device 1 as a specific example, it can be composed of, for example, a keyboard, a tablet, and a cursor. When the electronic component name of the code number, which is component data, is entered from the keyboard, the CPU 3 can determine the installation of the electronic component from this code number by reading the dimensions between the bins from a table prepared in advance. Further, connection data between bins of each electronic component can also be input using the information input device 1 while viewing the CRT 5.4 Normally, a series of terminals connected at the same potential is managed by the CPU 3 as net data. The placement position of the input electronic component on the printed circuit board may be determined automatically by a printed circuit board CAD device, or a cursor may be artificially displayed on the CRT S to indicate the component position. You may.

Based on the input data, the CPU 3 writes a collection area of cells obtained by subdividing the printed circuit board into a mesh into the storage device, selects two cells (starting point and ending point) to be connected, and connects these two cells. The CPU 3, which performs the operation of instructing the search direction of the route to be searched, can know the two points of cells to be connected from the input data. It is also possible to specify the search direction from the starting point to the ending point.

In the storage device 4, cell maps shown in FIG. 3 and subsequent figures are written.

The printed circuit board CAD device is equipped with a COT 5, on which a wiring diagram of the designed printed circuit board can be displayed, and a cursor can be displayed to input the component data and wiring data. Further, an output device 6 can be provided. As this output device 6, for example, a photoplotter or the like can be used, and it is possible to output a photo original for creating an actual printed circuit board from the created printed circuit board wiring data.

The CPU 3 shown in FIG. 2 as described above can horizontally build a cell map as shown in FIG. 3 (1) on the storage device 4. As described above, a cell is a small square area created by dividing the wiring area vertically and horizontally at wiring grid intervals, and is the smallest unit for route searching. In Figure 3 (1), the parts bin (
The white circle) indicates a bin for mounting electronic components, and normally this position cannot be moved when searching for a route.The through hole (black circle) is a hole that connects the component side and the solder side of the printed circuit board. The wiring prohibited area (dotted line block), which cannot be moved when searching for a route, is
For example, this pattern is necessary for attaching an electronic component (not shown) to a printed circuit board, and its position cannot be moved.Therefore, cells that cannot be moved are marked with diagonal lines and shown as fixed faulty cells (component placement information).

Furthermore, the cells marked with arrows are cells that have already been selected as wiring routes, and these cells are also cells that will become an obstacle when searching for a route from now on.

Furthermore, a cell in which nothing is written is an empty cell (blank cell), and the route search is performed by tracing this cell and finding a route from the starting point to the ending point. As mentioned above, in this specification, it is assumed that all wiring patterns applied to the component side of the printed board are in the horizontal direction, so FIG. 3(1) shows a wiring diagram of the component side.

Wiring information is written into each cell of the present invention.

Wiring information can be divided into the following three types.

(+) Existing wiring information This is information representing the connection relationship between the cell and the cells adjacent to each other vertically and horizontally.

(2) Wiring prohibition information This is information that means that wiring cannot be done to the cell in question. That is, it is route failure information in which the positions of parts bins, through holes, etc. are fixed.

(3) Availability information This information indicates that wiring is available for the current route search.

The information of each cell as described above is written in each address of the storage device 4 as shown in FIG. 3(2).
Cell M in 1) is written to address ADO100, and cell N is written to address ^00101. The contents are whether there is a parts bin in the bit ■ (“1” if there is a parts bin),
The presence or absence of a through pole is written to the bit (2), and the presence or absence of wiring prohibition is written to the bit (2). Furthermore, the existing wiring information on the component side is written in the bit portion (for example, 4 bits) indicated by ■, and the existing wiring information on the solder side side is written in the portion indicated by ■. The data contents of ■ and ■ in Figure 3 (2) are shown in Figure 3 (3) and 4.
This will be explained with reference to the figures.

FIG. 4 is a diagram showing an example of a connection state between cells adjacent to each other in the upper, lower, left, and right directions on the component side and the cell. In the case of FIG. 4, since the component side is shown, the connection pattern is in principle horizontal, and each cell is usually connected to adjacent cells on the left and right sides. Therefore, to represent the connection information on the component side, 1
Each cell is divided into left and right (see (2) in FIG. 3), and the vertical and horizontal directions of adjacent cells connected to the left and right halves are indicated by arrows in FIG. In FIG. 4, X represents unconnected; for example, in the cell of FIG. 4 (1), the left side is unconnected, and the cell on the right side is connected. That is, this means that this cell is the end point of the connection pattern. The cell in FIG. 4(8) shows that it is connected to the left side adjacent cell and the upper side adjacent cell.

The connection relationship information shown in FIG. 4 is shown in ■ in FIG. 3.

■Written to each address. FIG. 3 (3) is a diagram explaining the bit contents of the 0.0 part in FIG. CPt1
3 can easily know the connection state with adjacent cells by reading the information stored in the address of the cell.

The above description describes the adjacency state on the component side. On the other hand, since the connection pattern on the solder side is in principle vertical, each cell is connected to adjacent cells on the upper and lower sides. Therefore, in order to represent the connection information on the solder side, one cell is divided into upper and lower parts, and each code signal is associated with the connection direction as shown in FIG. 3(3).

Using the cell map with the above information, C in Figure 2
PU 3 performs the route search of the present invention.

First, an example of a typical search stop of conventional means will be shown using FIGS. 5 and 6.

In FIG. 5, the search proceeds from the direction of the dotted line, and the search point has progressed to the cell indicated by the double circle. Here, the cells in the search direction are already connected to existing wiring, and the upper side is a fixed fault W (wiring prohibited) cell. Therefore, since the search position cannot be advanced to the right of the search point in the diagram, it is not possible to connect, for example, to an end point (not shown) on the right side of the search point in the diagram.

In Figure 6, the search proceeds from the direction of the dotted line until it reaches the cell indicated by the double circle, but there is a fixed faulty cell in the search direction, and the cell above it is also connected to the existing wiring, so the search will not proceed any further to the right side. The present invention is a method that allows the search point to be advanced to the right cell by the following steps even in cases such as those shown in FIGS. 5 and 6. First, the case of FIG. 5 will be explained with reference to FIG. 1.

(1) Step 1 Existing wiring information, wiring prohibition information, and vacant information are written in each cell. Using the cell map in which these pieces of information are written, the search is performed as shown in FIG. 7.

Figure 7 (1) shows the search proceeding from the dotted line direction and the coordinate value (x
It is a figure which shows the place which reached the position of (o, yo).

(11) Step 2 CPU 3 moves one point toward the search direction (X
C, VC) = (xo+1.vo) If you read the contents of Nocerno, you will know that it is already wired and you cannot proceed with the search.

(2) Step 3 Point moved by one position toward the search direction (XC,'IIC
) = (XO+1.YO) as the cell extraction origin, (xc
, vc) , (XC+1, VC) , (XC, VC
-1), (XC+t, VC-1) ノ4 nocells (
4 cells constituting a square area) are extracted. Let these extracted cells be C1, C2, C3, and C4.

Furthermore, the cell status indicating the connection information corresponding to each cell C1, C2, C3, and C4 is St, 82, 83.34. Each cell C1, C2, C3, C4 in Fig. 7 (1)
The cell status of is as shown in FIG. 7 (4).

(To) Step 4 CPU 3 reads the contents of this cell status and selects cell C.
You can see that 4 is a blank cell. and C
PU 3 rewrites each cell status to new values SL", S2', 83°, and S4° shown in FIG. Rewrite cell C1 to a blank cell.

(V) Step 5 Move the search point (double circle) to this newly rewritten blank cell (XO+1.YO).

As a result, as shown in Figure 7 (2), if you try to proceed further with the search in the direction of the dotted line, the cell with the coordinate value (xO÷2.YO) shown in Figure 7 (2) will block your search. The CPU 3 knows that the cell will be a cell that
U3 uses the cell with this coordinate value (XO+2.YO) as the extraction origin in the same way as in step 3 above, and extracts new cells C1, C2, C3, and C4 as shown in FIG. This new cell 1,1. The cell status of C2, C3, and C4 is
The CPU 3 rewrites these cell statuses as shown in FIG. ), the search point can be advanced like this.

By repeating the above steps, the present invention can proceed with the search as if displacing the existing wiring.

The above is an example where there is only one existing wiring that blocks the search.

That is, this is a case where cell C4 among the four extracted square cells is a blank cell.

FIG. 8 shows an example in which there are two existing wirings to be blocked, and in this case as well, the search can proceed as if the existing wirings are pushed aside, as described above.

In Figure 8 (+), the cell extraction origin is set as (XO+1.'10) = (XC, YC) in the same way as in Figure 7 (1).
Then, the cell C4 shown in FIG. 7(1) is
In figure (1), CPU 3 confirms that it is not a blank cell.
can be known.

Therefore, the CPU 3 moves the cell extraction origin from (xc, vc) to (XC+1.VC-1) and extracts the four cells shown in FIG. 8(1) from this coordinate point, and cell C4 becomes a blank cell. You can know that. Therefore, by using the above-mentioned step 4, the existing wiring can be rewritten as shown in FIG. Hereinafter, when the above-mentioned steps 2 to 4 are repeated for the cells C1, C2, C3, and C4 shown in FIG. 8Q), the results are as shown in FIG. 8(3).

According to FIG. 8(3), a blank cell area is created next to the existing wiring, so the relationship is the same as FIG. 7(1). Therefore, the search point can be advanced by repeating the steps explained in FIGS. 7(1) to (3).

In the present invention, the number of existing wirings that become an obstacle to the search (two in the example of Fig. 8) may be any number, but the search width for route searching is, for example, the width of eight cells (that is, the width of the obstacle). Normally, the number of wires is limited to 8).

Therefore, if the existing wiring and fixed faults are so crowded that there are no blank cells within the width of these eight cells, the above-described search operation of the present invention cannot be performed.

In the case of Figure 6, there is a fixed obstacle in the search direction, so it cannot be pushed away.
It operates as shown in Figure 7.

By applying the process explained in FIG. 8, the search point can be advanced.

In Figure 9 (1), if the search point is (XO, YO), (XC + 1. YO) indicates that it is a fixed fault.
U 3 can know. In this case, the existing wiring is pushed up in the direction perpendicular to the search direction, that is, it is pushed up by 1 from the search point (XO, YO) in the direction perpendicular to the search direction.
The point moved by (XC, VC) = (XO, YO+1) is set as the cell extraction origin, and (XC-1, VC), (XC,
VC), (XC+1.VC).

(XC-1, VC+1), (XC, VC+1),
(XC+1.VC+1) Extract cQ6 cells. If each cell is designated as 01 to CG as shown in FIG. 9(1), its cell status 31 to S6 is as shown in FIG. 9(4).CPU 3 has cells C4, C5, and C.
You can know that 6 is a blank cell, in this case,
Each cell status is rewritten as shown in FIG. 9 (5). That is, the existing wiring is modified to route through blank cells C4, C5, and CO, and (XC, VC) = (XO, YO+1) No 1 Nil is rewritten to a blank cell. Then, as shown in FIG. 9(2), the search point is advanced to (XO, YQ÷1).

The resulting state shown in FIG. 9(2) is the same as the state shown in FIG. 7(1) since there is no fixed obstacle in the search direction.

Therefore, by applying the process explained in FIG. 7, the search point can be moved to the right.

Next, when two existing wiring lines and a fixed fault are blocking the search as shown in FIG. 10, the search point can be advanced by operating as follows. In the case of FIG. 10 (1), cells C4, C5, and CO shown in FIG. 9 are not blank cells.
In this case, the cell extraction origin is shown in Figure 9 (1) (XC,
VC) to (XC, YC+1) t,, after sono,
By performing the operations explained in FIGS. 9(1) to (3), the existing wiring on the upper side can be modified as shown in FIG. 10 (2). In this case, each time the cell extraction origin position is moved perpendicularly to the search direction, the number of cells to be extracted increases by four as both ends swell.

In the case of Figure 10 (1), cells C6, C7° C8, CIO
Since is a blank cell, the existing wiring on the upper side can be lifted up as shown in FIG. Then, by lifting the lower existing wiring to the blank cell created by lifting, (xc,
yc) can be made a blank cell. Then, move the search point to this (XC, VC) (Fig. 10 (2)
)reference).

The resulting state in FIG. 10 is the same as the state in FIG. 8 (+) because there is no fixed obstacle in the search direction.

Therefore, by applying the process explained in FIG. 8, the search point can be moved to the right.

As described above, according to the present invention, even if there is already wiring,
Since the search point can be advanced by pushing this away, efficient wiring can be performed.

FIG. 11 is a diagram showing a line segment search method, and it will be explained that the method of the present invention can be applied to this search method. The line segment search method is
Possible routes are generated alternately in the horizontal and vertical directions from the starting point S and ending point E in Figure 11 (1) to be connected, and each time they are generated, it is checked whether or not they intersect with the other side's possible route, and the intersection points are checked. This is a method to make the search successful at the point where the attachment is issued (see Figure 11 (2).
), if the present invention is used for such a line segment search method, even if the destination is blocked by an existing wiring, the existing wiring can be pushed aside and the possible route can be extended, so that the route between two points can be extended. can increase the likelihood of finding a route that connects the

Effects of the Present Invention> As described above, according to the present invention, even if there is existing wiring that becomes an obstacle to the search, it is possible to push it aside and advance the search point, thereby creating high-density printed circuit board wiring. be able to.

[Brief explanation of the drawing]

Fig. 1 is a flowchart showing a printed circuit board automatic wiring method according to the present invention, Fig. 2 is a diagram showing an embodiment of a printed board CAD device to which the method of the present invention is applied, and Fig. 3 is a diagram showing a cell map and storage of each cell. FIG. 4 is a diagram illustrating an example of the connection relationship in each cell, and FIGS. 5 and 6 are diagrams illustrating an example of a case where it becomes an obstacle to route search. , FIGS. 7 to 10 are diagrams showing the process of proceeding with the route search according to the present invention, FIG. 11 is a diagram showing the line segment search method, and FIGS. 12 and 13 are diagrams explaining the conventional example.
FIG. 14 is a diagram illustrating the straight line width of the wiring pattern. 1... Information input device, 3... CPt1.4... Storage device. Diagram (A) (9+ (ll) (/2) 10 left FA-Fyo cell and T Maki benuke.

Claims (1)

[Scope of Claims] An information input device for inputting component data and connection data of an electronic circuit mounted on a printed circuit board to a central processing unit (hereinafter referred to as CPU), a storage device, and an information input device based on the input data. A collection area of cells obtained by subdividing the printed circuit board into a mesh is written in the storage device, two cells to be connected are selected, a search direction for a route connecting these two cells is determined, and wiring information and information are written to each cell. In a device that automatically creates a wiring pattern for a printed circuit board and is equipped with a CPU that writes component placement information, existing wiring information (this information is used to write (The cell in question is called a wired cell), the wiring prohibition information that means that wiring cannot be done to the cell (the cell in which this information is written is called a fixed fault cell), and the cell that says that wiring is possible. Step 1 of writing meaning empty information (cells written with this information are called blank cells) into each cell, and detecting that the search cannot proceed because there is an already wired cell (C1) in the search direction. step 2, and a cell group (C1, C2,
Step 3 of extracting C3, C4), detecting a blank cell (C4) from this cell group (C1, C2, C3, C4), and modifying the existing wiring to route through this blank cell (C4). A printed circuit board automatic wiring method using the following steps: a step 4 of rewriting the already wired cell (C1) to a blank cell; and a step 5 of advancing a search route to the newly rewritten blank cell.