JPH02174249A - Ecl type gate array integrated circuit device - Google Patents

Abstract

PURPOSE:To enable a high-speed ECL circuit part and a low-speed ECL circuit part to be formed easily within a same gate array integrated circuit by preparing two types of resistors for determining the logic amplitude within a cell in a ECL type gate array integrated circuit device and selecting either resistor depending on whether the cell is for high speed or not. CONSTITUTION:There are three regions, namely a low-speed block region 11 where a cell for low speed 17 is placed, a high-speed block region 12 where a cell for high speed 18 is placed, and a low-speed/high-speed logic amplitude conversion block region 13 where a cell for low-speed/high-speed logic amplitude conversion 19 is placed. Then, A reference voltage bus for low speed 15 connected to a reference voltage generation circuit 14 is placed at the low-speed block region 11 and the low-speed/high-speed logic amplitude conversion block region 13. Also,a reference voltage bus for high speed 16 connected to the reference voltage generation circuit 14 is placed at the high-speed block region 12.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention is an ECL type gate array, and in particular, an ECL gate array in which the resistance value of a load resistor that determines the logic amplitude can be selected.
relates to a gate array integrated circuit device.

[Prior Art] Conventionally, the internal cells of this heel integrated circuit device are shown in FIG.
As shown in a), one end of the resistor 21 is connected to the higher side power supply bus 2.
8, the other end of the resistor 24 is connected to the collector of the transistor 22, one end of the resistor 24 is connected to the emitter of the transistor 23, and the other end is connected to the lower power supply bus 29 using aluminum wiring. The equivalent circuit is shown in FIG. 6(b). Figure 6 (b
), parts corresponding to those in FIG. 6(a) are given the same reference numerals. In this circuit, a signal input to the input signal input terminal 25 and a reference voltage input to the reference voltage input input terminal 26 are compared, and an output is taken out from the collector of the transistor 22. The logic amplitude V of this circuit is given by V=IR. However, ■ is the constant current transistor 24
R is the current flowing through the resistor 21, and R is the resistance value of the resistor 21.

[Problems to be Solved by the Invention] The internal cells of the conventional semiconductor integrated circuit device described above operate with a constant logic amplitude determined by the precision of the switching current and the value of the load resistance. By the way, one way to achieve faster circuit operation is to lower the logic amplitude, and by this means, you can partially reduce the speed of each block that is faster than the other blocks that make up the circuit. In order to increase the speed, it is necessary to lower the logic amplitude within the block to be increased in speed.However, in the conventional internal cell configuration described above, the logic amplitude is kept constant, so this cannot be changed. could not.

[Means for solving the problems] The ECL type gate array 4A integrated circuit device according to the present invention has the following features:
a constant current source transistor; a pair of bipolar transistors that receive current from the constant current source transistor and operate differentially; and a pair of bipolar transistors connected to the collector of one of the pair of bipolar transistors to extract a logical amplitude output. The device is equipped with a plurality of unit cells each having a resistor, and the resistor is configured in 114 so that it can be selected from resistors with different resistance values.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a plan view showing an embodiment of the present invention. As shown in the figure, in this embodiment, the integrated circuit device includes a low-speed block area 3411 in which low-speed cells 17 are arranged,
It has three areas: a high-speed block area 12 in which high-speed cells 18 are arranged and a low-speed/high-speed logic amplitude conversion block area 13 in which low-speed/high-speed logic amplitude conversion cells 19 are arranged.

Among these, the low speed/high speed theory 111i amplitude conversion cell 19 is
This cell converts the logic amplitude of the low speed cell 17 to that of the high speed cell 18. And low-speed block area 11 and low-speed/high-speed theory] 11! A low-speed reference voltage bus 15 connected to the reference voltage generation circuit 14 is arranged in the amplitude conversion block area 13, and a high-speed reference voltage bus 15 connected to the reference voltage generation circuit 14 is arranged in the high-speed block area 12. 16 are arranged. Each of the cells 17 to 19 and the reference voltage generation circuit 14 will be described in more detail below.

First, the low-speed cell 17 will be explained with reference to FIGS. 2(a) and 2(b), which are a plan view thereof and an equivalent circuit diagram thereof. In these figures, Figures 6(a) and (b)
The same reference numerals are given to the same parts as those in the conventional example shown in FIG. 21a and resistor 21b are connected in series. That is, one end of the resistor 21a is connected to the high-level power supply bus 28, one end of the resistor 21b is connected to the collector of the transistor 22, and the other ends of the resistors 21a and 21b are connected by aluminum wiring.

The logic amplitude V of this circuit is roughly given by the following equation, where the resistance values of the resistors 21a and 21b are Ra and Rb, respectively, and the current flowing through the transistor 24 is .

V'L = (Ra + Rb) 1Figure 2 (a)
The cell structure shown in FIG. 2(C) may be modified as shown in FIG. 2(C). In the example of FIG. 2(C), the load resistance of the transistor 22 is one resistor 21c. However, an internal contact 21d is formed in this resistor.

Next, the high speed cell 18 will be explained. Although illustration of this cell is omitted, in this cell, in FIG. 2(a), the resistor 21b is shortened by t,n, or in FIG. 2(c), the internal contact 21d of the resistor 21c is is connected to the collector of the transistor 22. Logic amplitude V 1 when resistor 21b is short-circuited
1 is roughly given by V, , -Ral, which is the logic amplitude of the low-speed cell 17.
It is smaller than L by Rbl.

Next, the low-speed/high-speed logic amplitude conversion cell 19 will be explained with reference to FIG. FIG. 3 is an equivalent circuit diagram of one cell, in which a resistor (for example, Ra) that determines the high-speed logic amplitude is connected as the load resistance of the transistor 22, and the output of the low-speed cell is connected to the input signal input terminal 25. When the low-speed reference voltage is applied to the reference voltage input input terminal 26, the high-speed voltage T! is input from the output terminal 27. 1! Amplitude signals can be obtained.

Although not used in this embodiment, transistor 2 is used to convert high-speed logic amplitude to low-speed logic amplitude.
The second load resistor may be one for low speed (for example, Ra + Rb), and a signal for high speed may be input to each input terminal.

Next, the reference voltage generation circuit will be explained with reference to FIG. 4, which is a circuit diagram thereof. In this circuit, a series circuit of a resistor 41, 43 and a transistor 42 is inserted between a high-level power supply bus 48 and a low-level power supply bus 49. A constant current determined by the resistance value of the resistor 43 flows, and the resistance value of the resistor 41 is set to a value that sets the high-distance reference voltage to a predetermined value. The collector voltage of the transistor 42 is transmitted to the emitter follower section 44, and the emitter voltage of the emitter follower attractor or the voltage obtained by dividing this voltage by resistance is output to the high speed reference voltage output terminal 45 or the low speed lip/lens voltage output terminal 46.
is output from.

Next, another embodiment of the present invention will be described with reference to FIG. As shown in the figure, in this embodiment, both a low-speed reference voltage bus 15 and a high-speed reference voltage bus 16 connected to the reference voltage generation circuit 14 are arranged in each cell column. Here, each cell is
Low-speed cell 17 and high-speed cell 18 explained in the previous embodiment
Or any of the logic amplitude conversion cells! It is assumed that the According to this embodiment, since both low-speed and high-speed reference voltage buses run in each cell, a cell at an arbitrary position can be used for high-speed or low-speed use.

[Effects of the Invention] As explained above, the present invention provides two types of resistors for determining the logic amplitude in the cell in an ECL type game gray integrated circuit device, and the resistance is adjusted depending on whether the cell is for high speed or not. , one of the resistors can be selected, so according to the present invention, a high-speed ECL circuit portion and a low-speed ECL circuit portion can be easily provided in the same gate array integrated circuit.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing one embodiment of the present invention, and FIG.
) and (c) are plan views showing a part of FIG. 1, FIG. 2(b) is an equivalent circuit diagram of FIG. 2(a), and FIGS. The equivalent circuit diagram of a part of the figure, Fig. 5, is as follows.
FIG. 6(a) is a plan view showing another embodiment of the present invention, FIG. 6(a) is a plan view showing a conventional example, and FIG. 6(b) is an equivalent circuit diagram of FIG. 6(a). 11...Low speed block area, 12...High speed block area, 13...Low speed/high speed logic amplitude conversion block area, 14... Reference voltage generation circuit. 15...Low speed reference voltage bus, 16...
・High-speed reference voltage bus, 17...
f = le for low m, 18...cell for high speed, 19...
Low speed/high speed logic amplitude conversion cell, 21.21a, 21
b, 21c, 24.41.43...Resistance, 22.2
342...Transistor, 28.48...High-level side power supply bus, two, 49...Low-level side power supply bus, 44.
...Emitter follower section, 45...High speed reference voltage output terminal, 46...Low speed reference voltage output terminal.

Claims (1)

[Claims] a constant current source, a pair of bipolar transistors that receive current from the constant current source and operate differentially, and a resistor connected to the collector of one of the pair of bipolar transistors to take out a logical amplitude output. 1. An ECL type gate array integrated circuit device comprising a plurality of unit cells having a plurality of unit cells, wherein the resistor is configured to be selectable from resistors having different resistance values.