JPH02173998A - Self-refresh device for field memory - Google Patents

Abstract

PURPOSE:To execute the self-refresh operation only in the transfer time independently of the period of a fundamental clock or the like by performing the self- refresh operation based on a row address strobe signal for refresh and a refresh address in the non-transfer time. CONSTITUTION:When a row address strobe signal RASREF for refresh is in the active state, a row address strobe signal switching means 4 outputs this row address strobe signal in the active state as a row address strobe signal RAS; but when a row address strobe signal RASOP for transfer is in the active state, the means 4 outputs this row address strobe signal for transfer in the active state as the row address strobe signal RAS. Consequently, the field memory is self-refreshed only in the non-transfer time even though the device is in the stand-by state or the period of the fundamental clock is long. Thus, storage information in the memory cell is held.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a field memory self-refresh device.

<Prior Art> The memory cell structure of a field memory is the same as that of a RAM (random access memory), and stored information is held in the memory cell in the form of charges. Therefore, the charge accumulated in the memory cell due to leakage current or the like decreases with time. Therefore, in order to retain the information stored in the memory cells for a long time, it is necessary to perform refresh periodically within a certain period of time by amplifying the charges and writing them into the memory cells again.

Conventionally, refresh methods for dynamic RAM include RAS only refresh method and CAS before R.
An AS refresh method, an auto-refresh method, a self-refresh method, etc. have been implemented.

In each of the above refresh methods, it is necessary to supply a row address strobe signal, a column address strobe signal, a refresh clock signal, etc. from the outside.

<Problems to be Solved by the Invention> Incidentally, in a field memory, memory cells are accessed serially based on a basic clock during screen scanning, so the result is the same as that of automatic refreshing.

However, the field memory has the above dynamic r
Unlike tAM, the memory block is on standby except during the transfer period during read transfer of one line of data from the memory block to the read register or write transfer of data from the write register to one line within the memory block. state. In other words, data transfer between the input/output board and the read register or write register operates based on the basic clock, but after the transfer period has passed, the memory block enters a standby state and the field memory The basic clock for the system stops completely.

Therefore, there is a problem in that refreshing cannot be performed within a certain period of time, resulting in information destruction in the memory cells. Therefore, a self-refresh device that performs refresh at a timing different from the basic clock is required.

Therefore, an object of the present invention is to generate a refresh row address strobe signal and refresh row address data, and automatically perform a self-refresh operation based on the generated refresh row address strobe signal and refresh row address data. An object of the present invention is to provide a field memory self-refresh device that performs self-refreshing of field memory.

Means for Solving the Problems> In order to achieve the above object, a field memory self-refresh device of the present invention includes a refresh row address strobe signal generation means for generating a refresh row address strobe signal, and a transfer row address strobe signal generator. During the transfer period in which data is transferred between the transfer row address strobe signal generating means that generates the strobe signal and the memory cells and registers of the field memory, the refresh low address is set to inhibit the self-refresh operation. refresh row address strobe signal modification means for inactivating the refresh row address strobe signal generated by the address strobe signal generation means; and refresh address generation means for generating a refresh address based on the refresh row address strobe signal. When the row address strobe signal for refresh is in the active state, the row address strobe signal for refresh in the active state is output, while when the row address strobe signal for transfer is in the active state, the row address strobe signal for refresh is in the active state. The device is characterized in that it includes a row address strobe signal switching means for outputting a row address strobe signal for transfer, and performs a self-refresh operation in a non-transfer period based on the row address strobe signal for refresh and the refresh address. .

<Operation> A refresh row address strobe signal is generated by the refresh row address strobe signal generation means and input to the refresh row address strobe signal modification means. Then, the refresh row address strobe signal modification means corrects the refresh row address strobe signal during the data transfer period in which data is transferred between the memory cell of the field memory and a register such as a read register or a write register. make it inactive.

On the other hand, a transfer row address strobe signal is generated by the transfer row address strobe signal generating means.

When the refresh row address strobe signal is in an active state, the row address strobe signal switching means outputs the refresh row address strobe signal in the active state as a row address strobe signal, and outputs the row address strobe signal for transfer as a row address strobe signal. When is in the active state, the transfer row address strobe signal in the active state is output as the row address strobe signal.

By doing this, during the non-transfer period, a self-refresh operation is performed based on the refresh row address strobe signal and the refresh address generated by the refresh address generation means in accordance with the refresh row address strobe signal.

Therefore, even in the standby state, even if the basic clock cycle changes, the self-refresh operation is performed based on the refresh row address strobe signal only during the non-transfer period.

<Example> Hereinafter, the present invention will be explained in detail with reference to illustrated embodiments.

FIG. 1 is a block diagram showing an embodiment of a field memory self-refresh device of the present invention. The refresh row address strobe signal generation circuit 1 generates a refresh row address strobe signal RA S pre based on the output signal no from the ring oscillator 2.
generate. The refresh row address strobe signal modification circuit 3 receives the refresh row address strobe signal RA S pre output from the refresh row address strobe signal generation circuit 1, and
When the transfer signal TRN from the outside indicating whether or not the field memory is in the above-mentioned transfer period is at level "L", this manually input row address strobe signal RA S pre for refresh is used as the row address strobe for refresh as it is. It is output as a modified signal RA S REF. On the other hand, when the transfer signal TRN is at level "H", the refresh row address strobe correction signal ττ37 is outputted as a level "H" signal without outputting the input refresh row address strobe signal RA S pre. Output.

The row address strobe signal switching circuit 4 transmits the transfer row address strobe signal W output from the transfer row address strobe signal generation circuit 5 when the field memory is in the transfer period, and when the field memory is in the non-transfer period. switches and selects the refresh row address strobe correction signal n A S REF output from the refresh row address strobe signal correction circuit 3 and outputs it as the row address strobe signal It A S .

The refresh address counter 6 receives the refresh row address strobe correction signal RA output from the refresh row address strobe signal correction circuit 3.
When S_REP is input, refresh row address data is output.

The address multiplexer 7 uses a read row address counter 8 when reading data from the field memory.
The read row address data output from
When writing data to the field memory, the write row address data output from the write row address counter 9 is used, and when performing a self-refresh operation, the refresh row address data output from the refresh address counter 6 is used. Select and output as row address data.

Then, according to the row address strobe signal RAS output from the row address strobe signal switching circuit 4, the refresh row address data, read row address data, or write row address data selected by the address multiplexer 7 is latched, Executes a self-refresh operation, a data write operation, or a data read operation.

Hereinafter, the refresh row address strobe signal generation circuit 1, the refresh row address strobe signal modification circuit 3, and the row address strobe signal switching circuit 4 will be explained in more detail.

Low address strobe signal generation circuit 1 for reflexology
As shown in FIG. 2, it consists of a nine-stage binary counter, a Nant gate 22, and a Knot gate 23. Approximately 30M1 (output signal Ro of z) output from ring oscillator 2
is divided by 11512 using a 9-stage binary counter, and the 6th stage
7th stage, 8th stage and 9th stage flip-flop 21,
21. ..., the output signal CTB3 from each terminal Q of 21
．． CTBt, CTB1 and CT B o are input to the Nantes gate 22.

Then, the output signal of this Nant gate 22 is
1 and 23 to output a refresh row address strobe signal RA S pre.

The refresh row address strobe signal modification circuit 3 includes a NOT gate 3133, an AND gate 32, and a NOR gate 3435, as shown in FIG. The above-mentioned transfer signal TRN is transmitted through the NOT gate 31 and the NOAH gate 35.
The refresh row address strobe signal RA S pre is input to the AND gate 32 . That is, during the transfer period, the transfer signal TRN of level "I-t" is applied to the NOT gate 31 and the NOR gate 3-5.
is input. Then, the output of the NOT gate 31 becomes the level "L", and at the same time, the output signal of the AND gate 32 becomes the refresh row address strobe signal RA S
The level is "L" regardless of pre. The output signal "L" of this AND gate 32 is input to the NOR gate 34, and as a result, the row address strobe correction signal WX for refresh becomes level "H" and becomes inactive.

On the other hand, in the case of a non-transfer period that is not a transfer period, a transfer signal TrtN of level "OFF" is input to the NOT gate 31 and the NOR gate 35. Then, the output of the not gate 31 becomes level "G". Therefore, the refresh row address strobe signal RA Sp inputted from the refresh row address strobe signal generation circuit 1
When re is at level "■4", the output signal of AND gate 32 is at level "H".

As a result, the refresh row address strobe correction signal WX3T becomes level "L" and becomes active.

In other words, during the transfer period, the refresh row address strobe correction signal πWRET is made inactive, while during the non-transfer period, the refresh row address strobe correction signal RA S REF is made active.

The row address strobe signal switching circuit 4 consists of Nant gates 41, 42, 4344 and a NOR gate 45, as shown in FIG. The refresh row address strobe correction signal RAS REF from the refresh row address strobe signal correction circuit 3 becomes “L”, or the transfer row address strobe signal n generated by the transfer row address strobe signal generation circuit 5 When A S op goes to level "L", row address strobe signal RAS shows level "L" and becomes active.

That is, the transfer row address strobe signal RASo
When p becomes active (i.e., during the transfer period),
A transfer row address strobe signal positive π is output as the row address strobe signal 3-. on the other hand,
Refresh row address strobe correction signal RA
S REF is active! At t3 (that is, non-transfer period), the refresh row address strobe correction signal RA is output as the row address strobe signal RAS.
S REF is output.

Therefore, the row address strobe switching circuit 4 selects the transfer Kawaguchi-address strobe signal n A S op output from the transfer row address strobe signal generation circuit 5 during the transfer period, while selecting the refresh low address strobe signal n A S op during the non-transfer period. Address strobe signal generation circuit! and the refresh row address strobe correction signal flAs, which is generated by the refresh row address signal correction circuit 3.

Then, during the transfer period, according to the row address strobe signal RAS (that is, the transfer row address strobe signal nAsop) output by the row address strobe signal switching circuit 4, the read row address counter 8 selected by the address multiplexer 7 The read row address data or the write row address data from the write row address counter 9 is latched and a transfer operation begins.

On the other hand, during the non-transfer period, the refresh address counter 6 selected by the address multiplexer 7 is It latches the refresh row address data and enters a self-refresh operation.

In this way, by the selection operation of the row address strobe signal switching circuit 4, the transfer row address strobe signal flAs based on the basic clock is changed during the transfer 1υI.
op is selected and data transfer is executed based on the transfer row address strobe signal flAsop and the read row address data or write row address data selected by the address multiplexer 7. On the other hand, during the non-transfer period, the refresh row address strobe correction signal RA S REF based on the output signal RO from the ring oscillator 2 is selected, and the refresh row address strobe correction signal RA
A self-refresh operation is performed based on S REF and the refresh row address data selected by the address multiplexer 7.

Therefore, the self-refresh operation can be performed only during the transfer period, regardless of the period of the basic clock.

<Effects of the Invention> As is clear from the above, the device mounting structure of the present invention includes refresh row address strobe signal generation means, refresh row address strobe signal modification means, and row address strobe signal switching means. ,
A refresh row address strobe signal is generated by the refresh row address strobe signal generation means, and during the transfer period, the refresh row address strobe signal is made inactive by the refresh row address strobe signal modification means, and the refresh row address strobe signal is inactivated. The strobe signal switching means selects the transfer row address strobe signal generated by the transfer row address strobe signal generation means as the row address strobe signal during the transfer period, while selecting the above-mentioned row address strobe signal during the non-transfer period. By selecting the refresh row address strobe signal as the row address strobe signal, the self-refresh operation is executed based on the refresh row address strobe signal and the refresh address generated by the refresh address generation means. ,
Even during standby or when the basic clock cycle is long,
The field memory can be self-refreshed only during non-transfer periods, and the information stored in the memory cells can be retained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the field memory self-refresh device of the present invention, FIG. 2 is a circuit diagram of a refresh row address strobe signal generation circuit, and FIG. 3 is a refresh row address strobe signal modification. FIG. 4 is a circuit diagram of a row address strobe signal switching circuit. l... Row address strobe signal generation circuit for refresh, 2... Ring oscillator, 3... Row address strobe signal modification circuit for refresh, 4... Row address strobe signal switching circuit, 5...
・Transfer row address strobe signal generation circuit, 6...
- Refresh address counter, 7 - Address multiplexer, 8... Row address counter for read, 9... Row address counter for write.

Claims (1)

[Claims] (1) Refresh row address strobe signal generation means that generates a refresh row address strobe signal, transfer row address strobe signal generation means that generates a transfer row address strobe signal, and memory cells and registers of the field memory. During the transfer period during which data is transferred between address strobe signal modification means; refresh address generation means for generating a refresh address based on the refresh row address strobe signal; A row address strobe signal switching means is provided which outputs an address strobe signal and, when the transfer row address strobe signal is in an active state, outputs the transfer row address strobe signal in the active state, during a non-transfer period. is based on the above refresh row address strobe signal and refresh address,
A field memory self-refresh device characterized by performing a self-refresh operation.