JPH02173856A - Buffer control system - Google Patents

Abstract

PURPOSE:To convert the transfer data width by comparing the value of an output counter with a high-order bit train of an input counter corresponding to the output counter and outputting the input data from a buffer while no coincidence of comparison is detected. CONSTITUTION:An input counter 10 of a control part 20 points successively the memory positions of a buffer 5, and an input control circuit 11 updates the input count value based on the counter value and the input data width. An output counter 21 points a high-order bit train decided by excluding the low-order bit train having the bit number decided in response to the output data width from the bit train showing the memory positions of the buffer 5 for the data to be outputted next. A comparator 22 compares the value of the counter 21 with the high-order bit train of the counter 10 corresponding to the counter 21 and outputs a discordance signal 24. An output control circuit 23 controls an output selector 6 so that the input data is outputted from a memory position decided by the counter 21 of the buffer 5 by a prescribed amount of output data width while the discordance signal is kept turned on. As a result, the transfer data width can be converted in an economical constitution.

Description

[Detailed Description of the Invention] [Summary] Regarding a buffer provided for converting the transfer data width in an electronic circuit, the basic data width is In a device that outputs input data input to a buffer with an input data width that is an integral multiple of , and may be different from an output data width, into a constant output data width that is a power of 2 times the basic data width. , the buffer having a data storage location that is an integral multiple of the output data width; an input counter that sequentially indicates the storage location of the input data on the buffer using the basic data width as a unit; an output counter that indicates a high-order bit string obtained by removing a low-order bit string of a number of bits determined according to the output data width from a bit string representing a storage position on the buffer, the value of the output counter, and the output counter of the input counter; and a comparison means for comparing the corresponding upper bit strings, and while a mismatch is detected by the comparison means, the input data is output from the buffer, and the buffer is
In the case where the input data is multiplied by a power of , the buffer is configured to output the input data of the output data width from the buffer every time a carry signal from a predetermined bit position of the input counter is detected.

[Industrial application field]

The present invention relates to a control method for a buffer provided for converting transfer data width in an electronic circuit.

The integration of semiconductor electronic circuits is rapidly progressing, and the number of pins required to serve as input/output terminals for the chips on which the circuits are mounted also tends to increase. Because it is relatively difficult structurally to do so, it is often necessary to reduce the number of pins required by changing the data width transferred between chips to the data width within the chip. As one method in such a case, data width conversion via a buffer is used.

[Conventional technology]

FIG. 4 is a block diagram showing an example of the configuration of a buffer circuit for data width conversion.

Data is input from data line 1 to input selector 3, and at the same time, data width is specified via control line 2. Control unit 4
controls the input selector 3 and buffer 5 at the input cuff needs, and stores data of the specified input data width in the continuous position of the buffer 5 following the previously input data.

The buffer 5 normally has a storage capacity that is more than twice the maximum data width of input or output data, and is made up of registers, etc. that constitute a storage circuit that can input and output data in the minimum unit of the basic data width, for example, an 8-bit byte. Become.

The control unit 4 monitors the amount of data stored in the buffer 5 as described above, and when data exceeding a certain output data width determined by the output data is stored, the control unit 4 starts the next output phase. controls the output selector 6 and the buffer 5, reads out data in a constant output data width in the order of input to the buffer 5, and outputs it to the data line 7.

In order to perform the above control, the control unit 4 is provided with, for example, an input counter 10 and an input control circuit 11.
indicates the byte position on the buffer 5 that stores the first byte of input data, and is initially set to 0 to indicate the Oth byte.

In this state, in the power phase, when the input data width is specified by the number of bytes from the control line 2, the value of the input counter 10 and the number of bytes of the control line 2 are input to the input control circuit 11. The input control circuit 11 generates a signal that controls the input selector 3 to pass the input data from the designated byte position to the byte position of the number of bytes designated by the number of bytes. Under this control, the input selector 3 sets input data to each byte of the buffer 5 corresponding to each byte position.

Next, the control unit 4 advances the value of the input counter 10 by the number of bytes of the control line 2 so that the input counter 10 points to the beginning of the next input data storage position.

The input counter 10 is configured so that after the maximum value indicating the rightmost byte position of the buffer 5, it returns to 0 and points to the Oth byte position.

An output counter 12 is provided for output control, and has the same configuration as the input counter 10, and is initialized to O in the same way.

The comparison control circuit 14 has an input counter 10 and an output counter 1.
2 is compared to determine the number of bytes from the byte position indicated by the output counter 12 to the hide position indicated by the input counter 10, and this difference in number of bytes is greater than or equal to the predetermined output data width value. When the output signal 16 is turned on.

The output control plate circuit 15 outputs the output signal 1 in the output phase.
6 is on, it generates a signal that controls the output selector 6 to pass the data on the buffer 5 of the number of bytes of the predetermined output data width set from the byte position indicated by the output counter 12. , the data of the output data width is output from the buffer 5 to the data line 7, and then the value of the output counter 12 is advanced by the number of bytes of the output data width to point to the beginning of the next output data storage position.

While the output signal 16 is on, the output control circuit 15 continues to perform the above output control for each output phase, and sequentially outputs the data on the buffer 5 in the input order with a constant output data width.

When the comparison control circuit 14 turns off the output signal 16 because the difference Hyde number calculated from the values of the output counter 12 and the input counter 10 becomes smaller than the value of the output data width, the output control circuit 15 stops the above output control. .

(Problems to be Solved by the Invention) Data width conversion is possible as described above, but more economical data width conversion control is desired, and the present invention enables transfer data width conversion with an economical configuration. The objective is to provide a buffer control method for

[Means to solve the problem]

FIG. 1 is a block diagram showing the configuration of the present invention.

FIG. 1(a) shows a first configuration of a buffer device for data width conversion, in which human data is stored in a buffer 5 via an input selector 3, and sequentially outputted with a predetermined output data width via an output selector 6. In order to do this, the control unit 20 includes an input counter 10 that controls data input, an input control circuit 11, and an output counter 2 that indicates the upper bit string of the output data position.
1. A comparison circuit 22 for comparing the output counter 21 and the input counter 10 and an output control circuit 23 are provided. 2 is a data line for inputting data, 2 is a control line for indicating the data width of input data, and 7 is a data line for outputting data.

Further, FIG. 1(b) shows a second configuration of the buffer device,
Similarly, in order to sequentially output input data via the buffer 5, the control section 30 is provided with an output control circuit 33 that detects and controls a carry signal of a predetermined bit of the input counter 31.

[For production]

The buffer device uses an input selector 3, a buffer 5, an output selector 6, an input control circuit 11 that controls them, and an output control circuit 23 to control the input data width, which is an integral multiple of the basic data width and may be different from the output data width. Assume that the input data input to the buffer 5 is outputted with a constant output data width having a power of 2 times the basic data width.

For this purpose, in the first configuration, the input counter 10 of the control unit 20 sequentially instructs the storage location on the buffer 5 in units of basic data width, and at the input cuff needs, the input control circuit 11 inputs data according to the count value and the input data width. Control the selector 3 and update the input count value.

The output counter 21 is a buffer 5 for data to be output next.
The comparator circuit 22 is configured to indicate the upper bit string by removing the lower bit string of the number of focuses determined according to the output data width from the bit string representing the upper storage position, and the comparison circuit 22 compares the value of the output counter 21 and the output of the input counter 10. It compares the upper bit string corresponding to the counter 21 and outputs a mismatch signal 24.

The output control circuit 23 controls the output counter 21 of the buffer 5 while the comparison circuit 22 detects a mismatch and the mismatch signal is on.
The output selector 6 is controlled to output the input data from the storage location determined by the predetermined output data width.

In the second configuration, the buffer 5 has a data storage position that is a power of 2 times the output data width, and the output control unit 33 detects a carry signal from a predetermined bit position of the input counter 31 as described above. Each time, input data corresponding to the output data width is output from the buffer 5.

The above control method simplifies the configuration of the output counter and comparison circuit, and allows the buffer device to be configured economically.

〔Example〕

FIG. 2 is a block diagram showing an embodiment of the first invention. For example, in order to output data input with an input data width of 1.2 or 4 bytes with an output data width of 2 bytes,
An 8-byte buffer 5a is provided, and therefore the input counter 10a of the control section 20a is constituted by a 3-bit counter.

Further, the output counter 21a is composed of 2 bits excluding 1 bit corresponding to the 2-byte output data width.

As in the conventional case, the input counter 10a starts operation by initializing it to O, and in the input phase, the input counter 10a
, the input control circuit 11a sets the data of the input data width indicated by the control line 2 from the data line 1 to the buffer 5a via the manual selector 3, and inputs the input counter 10a by the same control as in the conventional case. Advance by the number of bytes.

The output counter 21a is also initialized to 0, and the comparison circuit 22
A compares the upper two bits of the output counter 21a and the input counter 10a, and turns on the mismatch signal 24 when a mismatch between the two is detected.

When the mismatch signal 24 is on in the output phase, the output control circuit 23a controls the output selector 6 to pass the data on the buffer 5 of 2 bytes determined as the output data width from the byte position indicated by the output counter 21a.
A control signal is generated as in the conventional method, and 2-byte data is output from the buffer 5a to the data line 7. Note that since the output counter 21a indicates only the upper two bits of the byte position of the output data, the output control circuit 23a is always 0.
The lower 1 bit of is supplemented and this is treated as the position of the first byte.

Next, the output counter 21a is incremented by 1 to indicate the upper bit of the next output data storage position.

As in the conventional case, the output control circuit 23a continues the above output control for each output phase while the mismatch signal 24 is on, and sequentially outputs the data on the buffer 5a in the input order with a data width of 2 bytes. , when a match is detected in the comparison circuit 22a and the mismatch signal 24 is turned off, output control is stopped.

FIG. 3 is a block diagram showing an embodiment of the second invention. For example, in order to output data input with an input data width of 1.2 or 4 bytes with an output data width of 4 bytes, 8-byte buffer 5b, which is twice the data width
Therefore, the input counter 31b of the control section 30b is 3.
Let it be a bit counter.

In this way, the input counter 31b is initialized to O and starts operating as in the conventional case, and performs data input control operation together with the input control circuit 11b in the same manner as the input counter 10a and the input control circuit 11a.

The output control circuit 33b extracts and monitors the carry signal 34 of the second bit from the input counter 31b, and when the count value advances from "3" to "4" and from "7" to 1.
When a carry that occurs when the count advances and is reset to "0" is detected, by controlling the output selector 6, the output is 4 bytes from the Oth byte of the buffer 5b, then 4 bytes from the 4th byte, and so on. , only 4 bytes equal to the output data width are sequentially output every time a carry is detected.

In the above example, the input data width is less than or equal to the output data width, but even if the input data width is larger, it can be controlled in the same way.If necessary, the buffer should be set to four times the output data width.
It is clear that similar control can be achieved by increasing the number of times, for example, by eight times.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, in a buffer device provided for converting the transfer data width in an electronic circuit, a remarkable industrial effect is achieved in that the transfer data width can be converted with an economical configuration. be.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a bronc diagram showing the configuration of the present invention, FIG. 2 is a bronc diagram showing an embodiment of the invention, and FIG. 3 is a bronc diagram showing another embodiment of the invention. FIG. 4 is a block diagram showing an example of a conventional configuration. In the figure, 1.7 is a data line, 2 is a control line, 3 is an input selector, 4.20.20a, 30.30b are control parts, 5.5a,
5b is a buffer, 6 is an output selector, 10.1.0a,
31.31b is an input counter, 11, lla, llb is an input control circuit, 12.21.21a is an output counter, 14 is a comparison control circuit, 15.23.23a, 33.33b is an output control circuit, 2
2.22a is a comparison circuit, 24 is a mismatch signal, and 34 is a carry signal. Patent applicant: Director of the Agency of Industrial Science and Technology Kozo Iizuka, 2nd, A
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Claims (1)

[Claims] 1. Input data input to the buffer (5) with an input data width that is an integral multiple of the basic data width and may be different from the output data width is a power of 2 of the basic data width. In a buffer device that outputs data with a constant output data width, the buffer (5) has a data storage location that is an integral multiple of the output data width, and the storage location of the input data on the buffer (5) is An input counter (10
), and an output counter (21) that indicates the upper bit string obtained by removing the lower bit string of the number of bits determined according to the output data width from the bit string representing the storage position on the buffer (5) of the data to be output next. , a comparison means (22) is provided for comparing the value of the output counter (21) and the upper bit string corresponding to the output counter of the input counter (10), and a mismatch is detected by the comparison means (22). A buffer control system characterized in that the input data is output from the buffer (5) (23) while the input data is being output from the buffer (5). 2. Input data input to the buffer (5) with an input data width that is an integer multiple of the basic data width and may be different from the output data width is converted into a fixed data width that is a power of 2 times the basic data width. In a buffer device that outputs data with an output data width, the buffer (5) has a data storage location that is a power of 2 times the output data width, and the storage location of the input data on the buffer (5) is set to the basic data. An input counter (31
), and each time a carry signal from a predetermined bit position of the input counter (31) is detected, the input data corresponding to the output data width is output from the buffer (5) (33). A buffer control method characterized by: