JPH02173793A - Envelope waveform generating device - Google Patents

Abstract

PURPOSE:To generate envelope waveform data exactly as a user images by performing arithmetic for generating the envelope waveform data after shifting a target value temporarily. CONSTITUTION:The arithmetic which shifts the target value until the smallest target value becomes 0 and generates the envelope waveform data according to the shifted target value is carried out. Then the generated envelope waveform data is shifted by the same quantity in the opposite direction to compensate the shift in the target value. In this case, there are initial level data IL, attack level data Al, 1st decay level data 1DL, and 2nd decay level data 2DL as parameter data for setting levels. Namely, the target values IL, AL, 1DL, and 2DL are shifted temporarily up to a maximum and then the envelope waveform data are generated. Consequently, specially when an envelope is varied curvedly, the envelope is generated exactly as the user images.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to an envelope waveform generator used in electronic musical instruments and the like.

``Prior art'' As a conventional envelope waveform generator,
The one described in Japanese Patent No. 125990 (title of invention: envelope control device) is known.

``Problem to be Solved by the Invention'' By the way, in the conventional device described above, since the size and average level of the envelope waveform data during envelope calculation differs for each envelope waveform, it is particularly difficult for the user to set the envelope depending on the screen. There was a problem in which the envelope scheduled on the screen and the actual envelope may differ in such cases.

The present invention has been made in view of the above-mentioned circumstances, and it is an object of the present invention to provide an envelope waveform generator that can generate an envelope waveform that does not differ greatly from the user's image.

"Means for Solving the Problem" This invention repeatedly calculates first rate data, and when the calculation result reaches a first target value, then repeatedly calculates second rate data, and When the result reaches the second target value, the envelope waveform generator repeatedly calculates the third rate data and forms envelope waveform data by repeating the above calculation,
a first shifting means for shifting the target value in a direction in which the target value becomes smaller by an amount such that the minimum target value becomes O;
It is characterized by comprising a second shift means for shifting the formed envelope waveform data in a direction in which the value of the data increases by the shift amount of the first shift means.

"Operation" According to the present invention, the target value is shifted by an amount such that the minimum target value becomes O, and then calculation is performed to form envelope waveform data based on the shifted target value. Next, the formed envelope waveform data is shifted in the opposite direction by the same amount to correct the shift amount of the target value.

"Embodiment" Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an envelope waveform generator 10 according to an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of the configuration of an electronic musical instrument to which this envelope waveform generator 10 is applied.

First, referring to FIG. 2, the keyboard 11 is equipped with a plurality of keys for specifying the pitch of musical tones to be generated, and a key pressed on the keyboard 11 is detected by a key press detection circuit 12. Further, the speed of key depression is detected by the touch detection circuit 17. The pressed key detection circuit 12 outputs the detected pressed key key code KC and a key-on signal KON, and outputs the detected pressed key key code KC and the key-on signal KON.
is outputted to the musical tone signal generation circuit 13, and a key-on signal KON is outputted to the envelope waveform generation device 10, respectively.

The touch detection circuit 17 outputs touch data TD indicating the detected key press speed to the envelope parameter generation circuit 15. The musical tone signal generation circuit 13 generates a digital musical tone signal CD having a tone pitch corresponding to the given key code KC and having a tone selected by the tone color selection circuit 14.

The envelope parameter generation circuit 15 generates an attack part A1, a first decay part ID, a second decay part 2D, and a release part R1 of the envelope waveform (see FIGS. 3(a) and 4) generated by the envelope waveform generator IO. Various parameter data for setting the change rate and level of each part of the sing dump section F are generated according to the tone selected by the tone color selection circuit 14 and the touch data TD output from the touch detection circuit 17. Parameter data for setting the change rate includes attack rate data AR.

First decay rate data IDR, second decay rate data 2DR, release rate data RR.

There is forcing dump rate data FDR.

These change rate data are shown in Figures 3 (a) and 4.
This is data that determines the slope of each part of the envelope waveform shown in the figure. Parameter data for setting the level includes:
Initial level data IL.

There are attack level data AL, first decay level data IDL, and second decay level data 2DL. These level data determine the level at each change point of the envelope waveform (see FIG. 3(a)). Here, each level data IL, AI7. Both IDL and 2DL represent the amount of attenuation from the reference level Lb, as shown in the figure. Note that when the envelope level is the reference level Lb, the envelope waveform data becomes A1212 "0". Furthermore, as another parameter, which level is the maximum among the activation level, the first decay level, the second decay level, and the initial level, in other words,
Level data AL, IDL, 2DL, which are output at the same time,
There is maximum value selection data MO, M1 (2 bits) indicating which parameter in IL is the maximum. The relationship between the maximum value selection data MO, Ml and the level at which the maximum value is taken is shown in Table 1 below.

Table 1 is given for bellow waveform generator lO. Note that each of the above parameter data is logarithmic data.

The envelope waveform generator 10 generates envelope waveform data ED based on various parameter data and a key-on signal KON. The multiplier 16 multiplies the digital musical tone signal GD by the envelope waveform data ED to give a volume amplitude envelope to the musical tone signal. This digital musical tone signal is converted into an analog musical tone signal by a digital/analog conversion circuit 18 and supplied to a sound system 19.

Next, the envelope waveform generator 10 shown in FIG. 1 will be explained.

In this envelope waveform generator 10, an arithmetic circuit 20 includes an attack part A1 shown in FIG. 3(A), a first decay part ID, a second decay part 2D, a sustain part S, a release part R1, and Attack rate data AR, first decay rate data IDR, and second decay rate data 2DR correspond to each part such as the forcing dump part F.

By repeatedly adding or subtracting the release rate data RR and the turning damp rate data FDR at the timing of the clock pulse φ, for example, as shown in FIG.
Envelope waveform data ENVD that changes as shown in
Form B. This envelope waveform data ENVDB
is logarithmic data and indicates the amount of attenuation from the reference level Lb. Therefore, when each bit power A12fl of this data ENVDB is ``0'', the envelope level becomes the reference level Lb, and when A1212'' is ``1'', the envelope level becomes 0 level.

The control signal for controlling the arithmetic circuit 20 described above is the third
It is created based on the key-on signal KON shown in FIG. The key-on signal KON is the AND circuit 21 (lower part of Figure 1)
The key-on signal KON is applied to the rising/falling differentiation circuit 22 via the key-on signal KON at the rising edge (when the key is pressed) and at the falling edge (when the key is pressed).
A key-on pulse KONP+(c) in FIG. 3 and a key-off pulse KOFP ((d) in FIG. 3) are generated respectively. The output of the flip-flop 23 applied to the other input of the AND circuit 21 is normally "1", and becomes "O" when one of the conditions for performing a forcing dump is satisfied.

Envelope waveform data E output from the arithmetic circuit 20
All the bits of NVDB are given to the AND circuit 24, and the output signal of the AND circuit 24 when all the bits are "1" is "
l” is the AQQ “1” detection signal and the flip-flop 2
A set of 3 is given to S. Also, this Aff12
A signal obtained by inverting the “1” detection signal is applied to the AND circuit 25. A key-off pulse KOFP is given to the other input of the AND circuit 25, and its output is sent to the flip-flop 2.
3 is given to the reset human power R. When the envelope waveform level becomes 0 before the key is released (before the key-off pulse KOFP is generated), the AND circuit 24 outputs Au"l".
A detection signal ("l" signal) is output, and a signal "0" which is the inversion of this signal makes the AND circuit 25 inoperative, and even if a key-off pulse KOFP is generated by subsequent key release, the flip-flop block 23 is not reset. . In this case, the conditions for performing a forcing dump do not hold.

On the other hand, if the key is released before the envelope waveform level reaches 0, the key-off pulse KOFP is generated before the A1212 "1" detection signal has been generated, and the output of the AND circuit 25 becomes "1". Flip-flop 23 is reset. This causes flip-flop 2
The output of 3 becomes "0", which closes the AND circuit 21, and the inverted signal "1" causes the AND circuit 26 to open. The key-on signal ON is input to the other input of the AND circuit 26. flip flop 2
In response to the output "0" of 3, "l" is supplied to one of the AND circuits 26, and when the next new key is pressed, the rise of the new key-on signal KOH causes the AND circuit 26 to
The output of becomes "1". The output signal "1" of this AND circuit 26 is the forcing dump signal FD. On the other hand, if the envelope I-type level of the previous note becomes O before the next new key is pressed, the flip-flop 23 is set by the Aff12 "l" detection signal, so forcing damping is performed. Signal FD is not generated.

Then, on the condition that the key is released before the envelope waveform level becomes 0 and the next new key is pressed, the forcing dump signal FD is generated, and in response to this forcing dump signal FD, the forcing dump signal FD is generated. Then, a forcing dump operation (see reference numeral F in FIG. 4) is performed.

The key-on pulse KONP and key-off pulse KOFP generated from the rising and falling differentiating circuit 22 are applied to a counter 27 for controlling the calculation mode of the calculation circuit 20. The counter 27 is a 2-bit binary counter, and is set to “0,0” by the key-on clock KONP.
”, the count is increased by 1 at the timing of the signal applied to the clock terminal CLK, and “1.1” is loaded by the key-off/(russe KOFP). The 2-bit output of this counter 27 is the mode signal MDI, MD.
Used as O. The relationship between the mode signals MDI and MDO and the calculation mode is as shown in the table below (Figure 3 (E) to (E)).
(see g)). Note that the sustain section only holds the second decay level and does not perform any calculations.

It is added to the second table 28 and allows the counter 27 to be counted up only when attacking or declining. The other input of the AND circuit 28 is connected to the rising differentiation circuit 2.
Nine output pulses are provided.

The selector 31 (upper left in Figure 1) receives attack rate data AR and first decay rate data IDR output from the envelope parameter generation circuit 15 (Figure 2).
, second decay rate data 2DR, and release rate data RR are input.

This selector 31 selects one of attack rate data AR, first decay rate data ID, R, second decay rate data 2DR, and release rate data RR according to mode signals MDI and MDO, and selects one of attack rate data AR, first decay rate data ID, R, second decay rate data 2DR, and release rate data RR.
give to input. The single-manpower selector 32 is given forcing damp rate data FDR. and,
In accordance with the forcing dump signal FD, the selector 32 selects the one-manpower forcing dump rate data FDR in the forcing dump operation mode, and selects the output of the zero-manpower selector 31 in other cases. The upper bits of the output of the selector 32 are added to the adder circuit 33 . The lower (mk) bits are directly supplied to the logarithmic/linear conversion circuit 35 via the OR circuit 34, where they are converted into linear rate data RATE and output to the arithmetic circuit 20. .

The other input of the adder circuit 33 is supplied with the upper bit of the envelope waveform data ENVDB via the gate circuit 36. This gate circuit 36 is "open" when the output of the OR circuit 37 is "L", and "closed" when the output is "0", and
A signal MI outputted from the comparison circuit 30 and a forcing stamp signal FD outputted from the AND circuit 26 are applied to the input terminal of the OR circuit 37. When the output of the gate circuit 36 is "0", that is, when the output of the OR circuit 37 is "0", this adder circuit 33 outputs the bit as it is to the higher order of the output of the selector 32, and also outputs the bit as it is to the higher order of the output of the selector 32. When the output is 1', the upper bit of the envelope waveform data ENVDB is added to the upper bit of the output of the selector 32, and the addition result is output. Note that both the output of the selector 32 and the envelope waveform data ENVDB are logarithmic data, so the above addition is equivalent to multiplication of linear data. Furthermore, when the above addition result overflows, an "1" signal is output from the carry terminal CO. The OR circuit 34 normally supplies the output of the adder circuit 33 as is to the logarithmic/linear converter circuit 35, and also supplies the output of the adder circuit 33 as it is to the carry-out terminal Co of the adder circuit 33.
When the "l" signal is output from A12g, "l" is output.

Therefore, when the output of the OR circuit 37 is "0", the logarithmic rate data output from the selector 32 is converted into linear rate data RA in the log/linear conversion circuit 35.
It is converted into TE and supplied to the arithmetic circuit 20. In this case, if there is no change in the mode signals MDI, MDo and forcing dump signal FD, the rate data RATE is also constant.

On the other hand, when the output of the OR circuit 37 is "1", the selector 3
The upper bits of the envelope waveform data are added to the upper bits of the rate data outputted from 2, and the result of this addition is converted into linear rate data RATE. That is, even when the mode signal MD 1°MDO and the forcing stamp signal FD do not change, the rate data RATE changes sequentially according to changes in the envelope waveform data ENVDB, and when the value of the data ENVDB is large (the level of the envelope is If it is small) HA L/-
1-Data RΔTE also becomes large, and when the value of data ENVDB is small, rate data RATE also becomes small. The rate data RATE described above is then supplied to the arithmetic circuit 20.

Next, the selector 40 (left side in FIG. 1) receives attack level data AL and first decay level data 1D output from the envelope parameter generation circuit 15 (FIG. 2).
L1 to the second decal shape data 2DL and data “1”
1...11"(Au"l") is input. This selector 40 selects any of the above-mentioned human power data according to the mode signals MD1 and MDO, and applies it to the 0 human power of the selector 41. 41, the initial level I output from the envelope parameter generation circuit 15
L is input. Then, the selector 41 outputs the initial level [L when the key-on pulse KONP is 1'', and outputs the output data of the selector 40 when it is "O" to the inverting circuit 42 as level data LD. Inverting circuit 42 is the level data LD output from the selector 41
Each bit is inverted and output to the adder circuit 43.

The selector 44 contains upper J attack level data A L
, first decay level data IDL, twelfth decay level data 2DL, and initial level IL are input, respectively. Then, the selector 44 selects the maximum value selection data Ml output from the envelope parameter generation circuit 15,
One of the above-mentioned input data is selected according to MQ and outputted to the adder circuit 43 via the AND circuit 45 as maximum level data MAXLV. AND circuit 45 is controlled to open/close by key-on signal KOH.

The adding circuit 43 adds the output of the inverting circuit 42 and the output of the AND circuit 45, and outputs the addition result. Incidentally, the output of the inversion circuit 42 is data obtained by inverting each bit of the level data LD. Therefore, the output data DD of the adder circuit 43 indicates the result of the following calculation when the key-on signal KON is "1".

DD=MAXLV-LD-,-(LD-MAXLV) Here, (LD-MΔXLV) is the following data. That is, assume that the envelope parameter generation circuit 15 outputs level data IL, AL, IDL, and 2DL having the sizes shown in FIG. 3(A). In this case, the maximum value selection data Ml.

MO becomes “0,0” indicating attack level AL, and maximum level data MAXLV or attack level data AL
becomes. As a result, (LD-MAXLV)if becomes the value obtained by subtracting the level data AL from the level data LD.

The data DD described above is then supplied to the inversion circuit 45 and comparison circuit 30 of the arithmetic circuit 20. On the other hand, when the key-on signal KON is "O", DD=-LD.

The comparison circuit 30 is composed of an adder circuit 50 and a NOR circuit 51 that performs a NOR operation on each bit of the output of the adder circuit 50. The adder circuit 50 receives the envelope waveform data E.
NVDB and output data DD of the adder circuit 43 are added. Therefore, this adder circuit 50 performs the following calculation.

ENVDB-(LD-MAXLV) Then, the comparison circuit 30 outputs ENVDB and (LDMAX
The next signal is output depending on the magnitude of LV).

■If ENVDB<(LD-MAXLV), adder circuit 5
0 from the carry terminal Co as the signal MI.
”Output a signal.

■If ENVDB>(LD-MAXLV), adder circuit 5
0 from the carry terminal CO to “1” as the signal Ml.
”Output a signal.

■When ENVDB=(LD-MAXLV) In this case,
The output of the adder circuit 50 becomes AQQ "0", and therefore the NOR circuit 51 outputs a "1" signal as the signal EQ.

Next, in the arithmetic circuit 20, the inversion control circuit 55
It consists of exclusive OR gates, and the signal M
When l is "0", the rate data RATE is output as is, and when the signal Ml is "1", each bit of the rate data RATE is inverted and output. The adder circuit 56 adds the envelope waveform data ENVDB and the output of the inversion control circuit 55, and outputs the addition result to the O input of the n-bit selector 57. The inverting circuit 45 inverts each bit and node of the data DD mentioned above and outputs it to the -L bit of the selector 57. This selector 57's one-person lower order (n
-) "1" is supplied to the bit.

The selector 57 outputs the output data of the adder circuit 56 which is normally supplied to the O input, and selects the key-on/<rus KON
Outputs data by one person only when P occurs. When the output of the AND circuit 59 is "1", the selector 58 outputs the envelope generation data ENVDB to the selector 60, and outputs "
0", the output data of the selector 57 is output to the selector 60. Here, the output of the AND circuit 59 is mode 2.
(See FIG. 3(g)), and becomes an "l" signal only when the output signal EQ of the comparator circuit 30 is "1". When the output of the AND circuit 61 is "1", the selector 60 selects A12.
12 Outputs data “1” to register 62 and outputs “0”
At this time, the output data of the selector 58 is output to the register 62. Here, the output of the AND circuit 61 becomes an "L" signal only in mode 3 and when the output signal EQ of the comparator circuit 30 is "1". Read the output data and output it as envelope waveform data ENVDB.

The adder circuit 65 to which the above-mentioned envelope waveform data ENVDB is supplied adds the supplied data ENVDB and the output data of the adder circuit 66, and outputs the addition result to the logarithmic/linear converter circuit 67. Here, the addition circuit 6
6 adds the aforementioned maximum level data MAXLV and the output data (digital data) VOL of the volume adjustment operator (the path shown), and outputs the addition result. Logarithm/
The linear conversion circuit 67 converts the output data of the addition circuit 65 into linear data and outputs the linear data. The output data of this logarithmic/linear conversion circuit 67 is supplied to the multiplier 16 in FIG. 2 as envelope data ED.

Next, the overall operation of the envelope waveform generating circuit 10 described above will be explained.

First, when the key-on signal rises, the differentiating circuit 22 outputs the key-on pulse KONP.

As a result, the initial level data IL supplied to the selector 41 is outputted from the selector 41, inverted by the inverting circuit 42, and supplied to the adding circuit 43. On the other hand, when the key-on signal KON becomes "1", the AND circuit 45 becomes open and the maximum level data M
ΔXLV is supplied to the adder circuit 43 via the AND circuit 45. Here, for example, as shown in FIG. 3(a), there is an attack level, a first decay level, and a second decay level.

Assuming that the attack level is the maximum among the initial levels, the maximum value selection data M1, MO are "0°0", and the attack level data AL is outputted from the selector 44 as the maximum level data MAXLV. As a result,
From the adder circuit 43, data r-(l L-MAXLV)
J is output, and the inversion circuit 45 inverts the signal (7)f'--to become data (IL-MAXLV).

This data is then supplied to the register 62 via the selectors 57, 58, and 60.

Next, when the system clock φ rises, the above-mentioned data (IL-MAXLV) is read into the register 62 and output to each section as envelope waveform data ENVDB. At this time, the key-on pulse KONP falls, the counter 27 is cleared at this fall, and the mode signals MDI and MDO become "0, 0" (
mode O). As a result, attack level data AL is output from the selector 40 and supplied to the adder circuit 43 via the selector 41 and the inversion circuit 42. As a result, the output data DD of the adder circuit 43 is rAL-AL=0.
This data “0” is supplied to the adder circuit 50.

Furthermore, when the mode signals MDI and MDO become "0, 0", the selector 31 outputs acturate data AR, and the selector 32. Addition circuit 33. The signal is supplied to a logarithmic/linear conversion circuit 35 via an OR circuit 34. The logarithmic/linear conversion circuit 35 converts the supplied data into linear data, and outputs the data as rate data RATE to the inversion control circuit 55.
Output to.

(For convenience of explanation, in the following explanation, it is assumed that the output of the AND circuit 36 is always "0".) At this point, ENVDB>LD-MAXLV=0, and therefore, from the comparator circuit 30 The output signal Ml is an "l" signal. As a result, each bit of the rate data RΔTE applied to the inversion control circuit 55 is inverted and supplied to the addition circuit 56. The adder circuit 56 performs the calculation ENVDB-RATE, and sends the result of this calculation to the selectors 57, 58.
60 to register 62.

Next, when the system clock φ rises again, the above data is read into the register 62 and output as envelope waveform data ENVDB. Thereafter, each time the system clock φ rises, the rate data RATE is subtracted from the data in the register 62, and the result of this subtraction is written in the register 62 and output as envelope waveform data ENVDB. In this way, the envelope waveform data ENVDB is the data (I) at the key-on point.
After that, the rate data RATE is subtracted every time the system clock φ rises and decreases sequentially (see attack part A in FIG. 3(H)).

Then, when the upper m bits of the envelope waveform data ENVDB match rO(=LD-'MAXLV)J,
The output signal EQ of the comparison circuit 30 rises to "L". When the signal EQ rises to 1'', a pulse signal is output from the differentiator circuit 29 at this rise, and the AND circuit 2
8 to the clock terminal of the counter 27.

As a result, the counter 27 counts up, and the mode signals MDi and MDO become "0, 1" (mode 1).

In mode 1, the selector 40 outputs the first decay level data IDL, and the selector 41 and the inverting circuit 4 output the first decay level data IDL.
2 to the adder circuit 43. As a result, the adder circuit 43 outputs the data DD as follows: DD=-(LD-MAXLV)=-(IDL-AL), and is supplied to the adder circuit 50. Furthermore, when the mode 1 is entered, first decay rate data IDR is output from the selector 31, this data IDR is converted into linear rate data RATE in the logarithmic/linear conversion circuit 35, and is supplied to the inversion control circuit 55. At this point, the upper m bits of the envelope waveform data ENVDB are "0", while the data (IDL-AL) is positive data, and the relationship (IDL-AL)>ENVDB is established. As a result, the comparison circuit 30 outputs a "0" signal as the signal Ml. Signal MI is “0”
”, the inversion control circuit 55 outputs the shade data RATE as is to the addition circuit 56.
E and the result is supplied to the register 62 via selectors 57, 58, and 60.

Next, when the system clock φ rises, register 6
2, ENVDB+RATE is read, and thereafter, the rate data RATE is added to the data in the register 62 every time the system clock φ rises. That is, the envelope waveform data ENVDB increases sequentially at the timing of the system clock φ after the time when its upper M bits become "0" (see the first decay section ID in FIG. 3(H)).

Then, -L position- of the envelope waveform data ENVDB
When the bit matches the data (] DL-AL), the signal EQ (“1”) is output from the comparison circuit 30 again and is supplied to the differentiation circuit 29. The differentiating circuit 29 generates a pulse signal at the rise of this signal EQ, and the AND circuit 2
8 to the clock terminal of the counter 27. As a result, the counter 27 counts up, and therefore, the mode signals MDI and MDO become "1.0" (mode 2).

In mode 2, the selector 40 outputs the second decay level data 2DL, and therefore the adder circuit 42 outputs the second decay level data 2DL.
Then, the data DD=-(LD-MAXLV)=-(2DL-AL) is output and supplied to the adder circuit 50. Now, if 2DL<lDL, then at this point ENVDB(IDL-AL)>2DL-AL, so the comparator circuit 30 outputs a "1" signal as the signal Ml. .

In addition, in mode 2, second decay rate data 2DR is output from the selector 31, this data 2DR is converted into linear rate data RATE in the logarithmic/linear conversion circuit 35, and is supplied to the inversion control circuit 55.

At this point, the signal Ml is "0" as described above, and the inversion control circuit 55 has the rate data RATE.
is inverted and output to the adder circuit 56. The adder circuit converts the rate data RATE from the envelope waveform data ENVDB.
and the result is supplied to the register 62 via the selector 57.58.60.

From then on, each time the system clock φ rises, the envelope waveform data E N 'J D B decreases (
(See second decay section 2D in FIG. 3(g)). Then, when the upper bits of the envelope waveform data ENVDB match the data (2DL-AL), the signal EQ (“1”) is output again from the comparator circuit 30, and at the rising edge of the second signal EQ, a pulse is output from the differentiator circuit 29. A signal is output. However, at this point, the mode signal MDI is "1", the output of the inverter 28a is '0', and the AND circuit 28 is in the closed state.
In this case, the counter 27 will not be counted up by the output pulse of the differentiating circuit 29.

On the other hand, at this point, the first . The second inputs are both supplied with l'', and therefore the signal E supplied with their third input.
When Q becomes "1", the output of the AND circuit 59 becomes "1", and the data generated by the selector 58 alone, that is, the envelope waveform data ENVDB, is output from the selector 58 and output to the register 62 via the selector 60. be done.

Then, at the rising edge of the secondary system clock φ, the data ENVDB is read into the register 62. Thereafter, the data in the register 62 is read into the same register 62 every time the system clock φ rises. That is, in mode 2, the signal E from the comparator circuit 30
When Q is output, the envelope waveform data EN
VDB does not change and the same data continues (Figure 3 (ch)
(See Sustain part S).

Next, when the key-on signal KON falls, the key-off pulse KO is output from the differentiating circuit 22 at this falling point.
FP is output and supplied to the load terminal LD of the counter 27. As a result, the data “1, 1” is stored in the counter 27.
are loaded and therefore the mode signals MDI, MDO
becomes “1, 1” (mode 3).

In mode 3, the selector 40 outputs data AI2 &"1', and the data is passed through the selector 41 to the inverting circuit 4.
2, and in this inversion circuit 42, A(!12"
0'' and is supplied to the adder circuit 43.

At this time, the key-on signal KON is "O", so the output of the AND circuit 45 is rOJ. As a result,
The output data DD of the adder circuit 43 becomes "0", and this data "0" is supplied to the adder circuit 50. At this point, the envelope waveform data ENVDB is still available (2D
Therefore, ENVDB<LD-MAXLV=id"1", and the signal Ml becomes "0".

In addition, when mode 3 is entered, release rate data RR is output from the selector 31, and this data RR is converted into linear rate data RATE in the logarithmic/linear conversion circuit 35.
and is supplied to the inversion control circuit 55. At this point, the signal Ml is "0" as described above, and the inversion control circuit 55 outputs the rate data RATE E as it is to the addition circuit 5G. The adder circuit adds the envelope waveform data ENVDB and the rate data RATE, and supplies the result to the telesistaro 2 via selectors 57, 58, and 60. Thereafter, each time the system clock φ rises, the envelope waveform data ENVDB increases sequentially (see release part R in FIG. 3 (H)).
. Then, when the same data ENVDB becomes A (IQ "1", the signal EQ is "1") is output from the comparator circuit 3o.

When the signal EQ rises, a pulse signal is output from the differentiating circuit 29 at this rising edge, but in this case too, the AND circuit 28 is in an open state and the counter 27 is not counted up. On the other hand, in mode 3, the signal E
When Q becomes "F', the AND circuit 61 in the arithmetic circuit 20
The output of A12ρ becomes "1", and A12ρ "1" supplied to the 1 input of the selector 60 is supplied to the register 62 via the selector 60. From then on, every time the system clock φ rises, this data A is stored in the register 62.
1212″1″ is read. That is, from now on, the envelope waveform data ENVDB continues to be Af2d"1".

In addition, the envelope waveform data ENVDB is AQ(1"
When the signal becomes 1', the AND circuit 24 outputs a "1" signal. As a result, the flip-flop 23 is set, the AND circuit 21 is opened, and the AND circuit 26 is closed.

In the manner described above, envelope waveform data ENVDB that changes as shown in FIG. Adder circuit 65 adds the output of adder circuit 66, ie, MAXLV+VOL, to data ENVDB. This data is MAX!
, V, the envelope waveform data returns to the state shown in FIG. 3 (A). That is, in this envelope waveform generator 10, as shown in FIG. Certain level data IL, AL
, IDL, and 2DL are shifted by the smallest data among them to form envelope waveform data ENVDB, and the final adder circuit 65 returns the shifted data to the original value. Furthermore, adding the data VOL means controlling the overall level of the envelope waveform according to the adjustment position of the volume adjustment volume. Then, the output data of the adder circuit 65 is converted into linear data in a logarithmic/linear conversion circuit 67 and output to the multiplier 16 in FIG. 2.

Next, a case will be described in which the next key is turned on when the envelope is in the released state. When the envelope is in the released state, the flip-flop 23 is not yet set and the AND circuit 26 is in the open state. As a result, when the key-on signal KON becomes "1" based on the next key-on, a four-sync stamp signal FD ("1" signal) is output from the AND circuit 26 and supplied to the selector 32. As a result, selector 3
In place of the release rate data RR that was output from 1, forcing damp rate data FDR is output from the selector 32. This forcing rate data FDR has a larger value than the release rate data RR, and therefore, thereafter, the envelope rapidly descends as shown in forcing dump section F in FIG. 4.

Next, the AND circuit 36, the OR circuit 37 and the addition circuit 3
I will explain the function of 3. As mentioned above, when the output of the AND circuit 36 is "0", the mode signal MDI
, MDO or the forcing dump signal FD changes, and as a result, the envelope waveform data ENVDB changes linearly as shown in FIG. 3 (H). On the other hand, the AND circuit 36,
When the OR circuit 37 and the addition circuit 33 are inserted,
Forcing dump signal FD or signal M I h<“
1", the AND circuit 36 is opened and the upper bit of the envelope waveform data ENVDB is added to the output of the selector 32. As a result, as shown by the broken line in FIG. In the dump part F, the envelope waveform data ENVDB changes in a curved manner, and the lower the envelope level is (
The larger the value of envelope waveform data ENVDB)
The slope of the curve becomes steeper.

Note that in the above explanation, the envelope waveform is
The shape shown in Figure (a) was used, but the envelope waveform was
In addition, there are various shapes as shown in FIG.

The details of one embodiment of the present invention have been described above. According to the above embodiment, the target values (level data IL, AL.

IDL, 2DL) are shifted to the maximum limit, and then envelope waveform data is formed. This makes it possible to form an envelope exactly as the user (envelope setter) imagines, especially when changing the envelope in a curved manner. In other words, if such software is not used, the envelope judgment data E
, NVDB levels are not known, and therefore it is not possible to judge how steep the curve will be (depending on the data ENVDB). On the other hand, in the above embodiment, since the target value is shifted, the approximate level of the envelope waveform data ENVDB can be known, and therefore the slope of the curve can also be roughly determined.

"Effects of the Invention" As explained above, according to the present invention, the target value is shifted once and then the calculation to form the envelope waveform data is performed, so that the user (envelope setter)
Envelope waveform data can be created exactly as imagined. Further, according to the present invention, it is possible to calculate envelope waveform data down to a level smaller than that of the conventional method, and as a result, it is possible to obtain the effect of improving the lingering sound of generated musical tones.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of an envelope waveform generator 10 according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of an electronic musical instrument to which the same embodiment is applied, and FIGS.
The figures are waveform diagrams for explaining the operation of the same embodiment.
The figure is a diagram showing another example of the envelope waveform. 20... Arithmetic circuit, 3o... Comparison circuit, 4o, 41.44... Selector, 42...
...Inverting circuit, 43...Addition circuit, 65...
...Addition circuit. Figure 2 Figure 4

Claims (1)

[Claims] The first rate data is repeatedly calculated, and when the calculation result reaches the first target value, the second rate data is repeatedly calculated, and when the calculation result reaches the second target value, the next In an envelope waveform generator that repeatedly calculates third rate data and forms envelope waveform data by repeating the above calculation, the target value is reduced by an amount such that the minimum target value becomes 0. a first shift means for shifting in the direction, and a second shift means for shifting the formed envelope waveform data in the direction in which the value of the data increases by the shift amount of the first shift means. Envelope waveform generator.