JPH02172899A - Composite semiconductor substrate - Google Patents

Abstract

PURPOSE:To form the high-quality compd. semiconductor substrate by providing a specific intermediate layer and a strain superlattice layer and adding specific impurities to a single crystal layer of the compd. semiconductor at the time of growing the single crystal of the compd. semiconductor consisting of group III-V elements or II-VI elements of periodic law table on the single crystal substrate consisting of Si, Ge, etc. CONSTITUTION:The following constitution is adopted at the time of forming the compd. semiconductor material formed by providing the single crystal layer of the compd. semiconductor consisting of the group III-V elements or II-VI elements of periodic law table which are different in component compsn. from the component compsn. of the single crystal substrate on the prescribed single crystal substrate: The 1st intermediate layer as an initial growth layer consisting of the above-mentioned compd. semiconductor is first formed as the intermediate layer to be introduced between the single crystal substrate and the single crystal layer of the compd. semiconductor, then the 2nd intermediate layer consisting of the strain superlattice layer composed of at least one kind among InGaAs/GaAs, InAsP/InP, etc., is provided on this 1st intermediate layer. The impurities of at least one kind selected from Si, S, Zn, Mg, In, and Al are added at >=2X10<18>cm<-3> to the whole or a part of the single crystal layer of the magnetic compd. semiconductor.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a composite semiconductor substrate, and in particular, to a single crystal substrate,
The present invention relates to a high-quality semiconductor heteroepitaxial substrate having an extremely low dislocation density, on which a single crystal layer of a compound semiconductor made of elements from Groups ■-■ or II-VI of the Periodic Table of Elements is grown.

[Conventional technology]

A composite semiconductor substrate is manufactured by growing a single crystal layer of a compound semiconductor such as GaAs, InP, or Zn5a having a composition different from that of the single crystal substrate on a single crystal semiconductor substrate such as Si or Ge. In order to realize high-performance semiconductor devices using these composite semiconductor substrates, it is required that the semiconductor single crystal layer has few lattice defects. However, in conventional composite semiconductor substrates, because the lattice constant and thermal expansion coefficient of the single crystal substrate material made of semiconductor and the semiconductor single crystal layer material are different, mismatched dislocations caused by lattice mismatch and dislocations caused by thermal stress occur. occurs, so 10@~10”
There has been a problem in that high-density dislocations on the order of cm-'' exist within the semiconductor single crystal layer.

Conventionally, attempts have been made to reduce the dislocation density within the semiconductor single crystal layer by using thermal annealing treatment or introducing an intermediate layer such as a strained superlattice layer between the single crystal substrate and the semiconductor single crystal layer. . Here, problems in the prior art regarding reduction of dislocations in a semiconductor single crystal layer will be explained using as an example a conventional composite semiconductor substrate in which GaAs single crystal acid is formed on a Si single crystal substrate.

FIG. 3 shows an example of the configuration of a conventional composite semiconductor substrate.
Metal organic chemical vapor phase epitaxy (OM) is applied onto a single crystal substrate such as Si.
When forming a single crystal growth layer 2 of GaAs or the like using VPE) method, etc., in order to reduce the dislocation density in the single crystal growth layer 2, a low temperature crystal growth layer with a crystal growth temperature of about 400°C and a low temperature crystal growth layer of about 700°C are used. After forming the first intercalary layer 3 consisting of a high temperature crystal growth layer of t-700-9
The second intermediate layer 4 made of InGaAs/GaAs was formed by repeating thermal annealing several times at temperatures up to 00°C [Yamaguchi et al., Applied Physics Letters].
etters) Volume 53, No. 21, 1988 (page unknown)].

Regarding the composite semiconductor substrate made of GaAs/Si produced by this conventional method, the effect of the second intermediate M4 composed of the InGaAs/GaAs strained superlattice layer on the reduction of dislocation density in the GaAs single crystal growth layer 2 was investigated. Shown in Figure 4. In the figure, by introducing the second intermediate layer 4, GaAs
Stress that depends on the composition and layer thickness of the InGaAs/GaAs strained superlattice layer is applied to the single crystal growth WJ2, and dislocation propagation is suppressed by coalescence of dislocations within the single crystal. This results in a reduction in dislocation density. However, as shown in Figure 4, the stress value is 10
Up to 'dyn/am', the reduction in the dislocation density in the single crystal growth layer 2 is remarkable, but at 10'dyn/cm2 or more, the dislocation generation critical stress is exceeded, so the dislocation density in the GaAs single crystal growth layer 2 is reduced. Thus, in the conventional technology, the dislocation density in the GaAs single crystal growth layer 2 was limited to about 10'cn-''.

[Problem to be solved by the invention]

As mentioned above, in conventional composite semiconductor substrates, in order to reduce the dislocation density in the semiconductor single crystal layer provided on the single crystal substrate, attempts have been made to introduce intermediate layers such as thermal annealing and strained superlattice layers. However, there was a limit to the reduction of dislocation density within a semiconductor single crystal layer.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and to provide a composite semiconductor substrate having a high quality semiconductor heteroepitaxial single crystal growth layer with extremely low dislocation density.

[Means to solve the problem]

In order to achieve the objects of the present invention, on a predetermined single crystal substrate made of Si, Ge, etc., elements of Group III and Group V of the periodic table, such as GaAs and InP, whose composition is different from that of the single crystal substrate. Alternatively, in the case of manufacturing a composite semiconductor substrate provided with a single crystal layer of a compound semiconductor made of elements of group II and group VI such as Zn5e, 5 is introduced between the single crystal substrate and the single crystal layer of the compound semiconductor. As an intermediate layer, a first intermediate layer made of the compound semiconductor as an initial growth layer is formed on the single crystal substrate, and the first intermediate layer m
On top, InGaAs/GaAs, InGaAs/GaA
sP.

AffiGaAs/GaAg, InAsP/InP, I
nP/InGaP, Zn5e/ZnSSe, ZnSeT
A second intermediate layer made of at least one strained superlattice layer selected from e/ZnSe, etc., and a single crystal layer and/or the first intermediate layer of the compound semiconductor to be formed; SL, S,
At least one impurity selected from Zn, Mg, In, AM, etc.

2 x 10" am-" or more.

In the process of forming the intermediate layer of the composite semiconductor substrate of the present invention, the substrate temperature is lowered to 700 to 900° C. before or after the introduction of the first intermediate layer and the second intermediate layer.
from the temperature range of 0 to 300℃, 1
By repeating the thermal annealing treatment up to 200 times, a high quality semiconductor heteroepitaxial substrate with even lower dislocation density can be obtained.

Here, an example of the basic configuration of a composite semiconductor substrate according to the present invention will be given and explained in more detail based on the drawings.

As shown in FIG. 1, GaA
When forming the single crystal growth layer 2 of S, InP, Zn5e, etc., in order to reduce the dislocation density in the single crystal growth layer 2, a low temperature crystal growth layer with a growth temperature of about 400°C and a high temperature crystal growth layer with a growth temperature of about 700°C are used. The first intercalary (initial growth, I
After forming 3, heat from 0 to 300℃ to 700 to 900℃.
By repeating thermal annealing several times to ℃, InGaAs/
A second intermediate layer (strained superlattice layer) 4 made of GaAs or the like is formed. Up to this point, the configuration is common to the conventional technology, but in the present invention, the single crystal growth n2 or a part thereof (as illustrated in FIG. 1(a)), the initial growth layer, the strained superlattice layer, etc. The first and second intermediate layers 3.4 or a part thereof (FIG. 1(b)), or the single crystal growth layer 2. In the growth report area of the first intermediate RIJ 3 and the second intermediate scrap 4 [Figure 1 (C)], Si and S are present.

Impurities such as Zn, Mg, In, and Al 2XLO”c
Single crystal growth layer 2' doped with impurities by adding m-' or more
, a first doped intermediate layer 3', a second doped intermediate layer 3', and a second doped intermediate layer 3'.
This is a composite semiconductor substrate characterized by comprising an intermediate layer 4'.

FIG. 2 shows the stress effect of the strained superlattice layer on the reduction of dislocation density in the single crystal growth layer 2 in the GaAs/Si composite semiconductor substrate of the present invention in comparison with the conventional technique. By introducing the second intermediate WJ4 made of a strained superlattice layer, stress depending on the composition and layer thickness of the strained superlattice layer is applied within the single crystal growth layer 2.

As a result of suppressing the propagation of dislocations by coalescence of dislocations within the single crystal, etc., the dislocation density within the single crystal growth M2 is reduced. In the prior art, dislocations occur in the single crystal growth layer 2 because the critical stress for generating dislocations is exceeded at 107 dyn/12 or more. As a result, in the conventional technology, the dislocation density in the single crystal grown WJ2 was limited to about 1061-2, whereas in the present invention, as shown in FIG. si, s, etc.
Zr+, Mg+ In.

Because more than 2X10"■1 of impurities such as Al were added,
The critical stress for dislocation generation in the impurity-doped single-crystal growth layer 2' can be improved by about one order of magnitude, and as a result, the dislocation density in the single-crystal growth layer 2 can be reduced to 10'an-'' or less, by more than one order of magnitude. Dislocation density can be reduced.

〔Example〕

An embodiment of the present invention will be described below in more detail based on the drawings.

(Example 1) FIG. 1 shows an example of the structure of a composite semiconductor substrate of the present invention made of GaAs/Si. In the figure, SL single crystal substrate 1 is grown at a growth temperature of 400 by metal organic vapor phase epitaxy.
The first intermediate layer 3 consisting of a GaAs layer grown at a low temperature of about 700°C and a GaAJj layer grown at a high temperature of about 700°C is
After forming M, thermal annealing was repeated 5 to 10 times from 20°C to 800°C.

After this, In,, 1Ga0. , Si was added as an impurity to a strained superlattice M consisting of a 10-periodic structure with each layer of As/GaAs having a thickness of 1000 layers, about 5 x 10" cm-
' was added to form a second intermediate layer 4 ' doped with impurities. Furthermore, a single crystal R2' of GaAs doped with impurities was grown at 700°C, and Si was added as an impurity to approximately 5×10"
(1) While adding -3, a 1 μm thick layer was formed. In this way, based on the present invention (G of a composite semiconductor substrate made of GaAs/Si)
When the dislocation density in the aAs single crystal grown NJ2 was investigated using a transmission electron microscope and an etch pit evaluation method, it was found to be approximately 10'CI.
I+", and the dislocation density was reduced by about one order of magnitude compared to the conventional method, and a remarkable effect was observed.

In the prior art, In0. , Ga, , As/Ga, Aq
When using a strained superlattice ephemeris, the optimal structure is a 10-periodic structure with each ephemeris having a thickness of 100 people, and the stress applied to the GaAs single crystal growth layer 2 is limited to 10'dyn/cm'', and higher stress is not possible. In other words, dislocations occur when the thickness of the strained superlattice M is greater than the above.In contrast, in the present invention, dislocations occur in the impurity-doped single crystal growth layer 2' or the impurity-doped strained superlattice layer 4'. As a result of increasing the critical stress for dislocation generation by approximately one order of magnitude by adding impurities at a high concentration, the strained superlattice layer thickness can be increased, resulting in a high-quality composite semiconductor substrate with a dislocation density approximately one order of magnitude lower than that of conventional technology. In addition, the types and concentrations of impurities were determined.

By optimizing the structure and layer thickness of the strained superlattice layer.

Furthermore, a high quality composite semiconductor substrate can be obtained.

(Example 2) A composite semiconductor substrate of the present invention made of InP/Si having the configuration shown in FIG. 1 was manufactured by the procedure shown below.

On the St single crystal substrate 1, by organometallic vapor phase epitaxy,
Low-temperature grown aaAs layer with a growth temperature of about 400°C and 70%
First intermediate layer 3 made of GaAsWI grown at a high temperature of about 0°C
After forming about 1 μm of
Thermal annealing was repeated 10 times. After this, InAs,
, , P, , , Si is added as an impurity to the strained superlattice layer consisting of an lθ periodic structure with a thickness of 500 in each layer of InP.
The impurity-doped second intermediate layer 4' was formed by doping about 5×10"01 m-' of InP. Further, the single crystal growth layer 2', which was doped with InP at 600°C, was grown with Al as an impurity.
1 was added to a thickness of 2 μm while adding about 5×10”×−3.

When the dislocation density in the InP single crystal growth history 2 of the InP/Si composite semiconductor substrate manufactured in this way based on the present invention was investigated using a transmission electron beam microscope and an etch pit evaluation method, it was found that approximately 3 x 10'an'', and the dislocation density was reduced by about one order of magnitude compared to the conventional technology, and a remarkable effect was observed.

In the conventional technology, when an InAsP/InP strained superlattice layer is used, a 10-period structure with each layer having a thickness of 150 layers is optimal, and the stress applied to the InP single crystal growth layer 2 is also 10'dy.
The limit is about n/■2, and the stress is higher than this.

In other words, dislocations occur when the strained superlattice layer is thicker than this. In contrast, in the present invention, the impurity-doped single crystal growth layer 2' and the impurity-doped strained superlattice layer 4
As a result of increasing the critical stress for dislocation generation by approximately one order of magnitude by adding a high concentration of impurities to A semiconductor substrate was obtained. Furthermore, the type and concentration of impurities,
Structure of strained superlattice layer and 2. By optimizing the thickness, etc., a composite semiconductor substrate of even higher quality can be obtained.

In the above embodiments, GaA is used as the single crystal growth layer.
A case has been described in which a compound semiconductor material made of elements of the ■-■ group such as s and InP is used.

It can be similarly applied to ternary and quaternary mixed crystal materials such as InGaAs and InGaAsP, and compound semiconductor materials made of II-VI group elements such as Zn5e, Zn, and SSe. Furthermore, it goes without saying that the single crystal substrate is not limited to the Si single crystal substrate, and other single crystal substrates such as Ge can be suitably used.

〔Effect of the invention〕

As explained in detail above, in the composite semiconductor substrate according to the present invention, the thickness of the strained superlattice layer increases as a result of adding impurities to the single crystal growth layer and the intermediate layer to increase the critical stress for generating dislocations in these layers. Even if the thickness is increased, dislocations do not occur.
It is possible to reduce propagation of dislocations into the single crystal growth layer. Regarding the impurities to be added, GaAs/Si
In this case, not only electrically active impurities such as Si and Zn but also electrically inactive impurities such as A2 and In can be used, so no problems arise in terms of device configuration or process. Therefore, it is possible to provide a high-quality composite semiconductor substrate, which can be used as a semiconductor substrate for high performance, low cost, lightweight, large diameter, and high strength optical devices, M1 child devices, and optical/electronic integrated circuits. Can be widely used.

[Brief explanation of the drawing]

FIGS. 1(a), (b), and (c) are schematic diagrams showing an example of the basic structure of a composite semiconductor substrate of the present invention, and FIG. Graph showing the relationship between dislocation density and stress in a crystal layer; FIG. 3 is a schematic diagram showing an example of the structure of a conventional composite semiconductor substrate; FIG.
The figure shows the G of a conventional GaAs/Si composite semiconductor substrate.
3 is a graph showing the relationship between dislocation density and stress in an aAs single crystal layer. 1...Single crystal substrate 2...Single crystal growth layer 2'...Single crystal growth layer doped with impurities 3...First intermediate N (initial growth 2) 3'...Single crystal growth layer doped with impurities 1 intermediate layer 4... Second intermediate layer ff1 (strained superlattice layer) 4'... Second layer doped with impurities
Middle class (a) 1--Appearance for patents handled by Nippon Telegraph and Telephone Corporation Junnosuke Nakamura (b) (C) Figure 1

Claims (1)

[Claims] 1. On a predetermined single crystal substrate, an element of Group III and V of the periodic table, or I
In a composite semiconductor substrate provided with a single crystal layer of a compound semiconductor made of elements of group I and group VI, as an intermediate layer introduced between the single crystal substrate and the single crystal layer of the compound semiconductor, on the single crystal substrate. A first intermediate layer made of the above compound semiconductor is formed as an initial growth layer, and on the first intermediate layer, InGaAs/GaAs, InGaAs/GaAsP, AlGaAs/GaAs,
InAsP/InP, InP/InGaP, ZnSe/
A second intermediate layer made of at least one strained superlattice layer selected from ZnSSe, ZnSeTe/ZnSe is provided, and Si, S, Zn, At least one impurity selected from Mg, In, and Al is added to 2×10^1
A composite semiconductor substrate characterized by adding three or more ^8cm^-^. 2. On a predetermined single crystal substrate, an element of group III and V of the periodic table or I
In a composite semiconductor substrate provided with a single crystal layer of a compound semiconductor made of elements of group I and group VI, as an intermediate layer introduced between the single crystal substrate and the single crystal layer of the compound semiconductor, on the single crystal substrate. A first intermediate layer made of the above compound semiconductor is formed as an initial growth layer, and on the first intermediate layer, InGaAs/GaAs, InGaAs/GaAsP, AlGaAs/GaAs,
InAsP/InP, InP/InGaP, ZnSe/
A second intermediate layer made of at least one strained superlattice layer selected from ZnSSe and ZnSeTe/ZnSe is provided, and the first intermediate layer or the second intermediate layer, or the first intermediate layer and At least one type of impurity selected from Si, S, Zn, Mg, In, and Al is added to all or a part of the second intermediate layer in an amount of 2×10^1^8 cm-^3 or more. A composite semiconductor substrate characterized by: 3. On a predetermined single-crystal substrate, an element of Group III and V of the periodic table or I
In a composite semiconductor substrate provided with a single crystal layer of a compound semiconductor made of elements of groups I and VI, as an intermediate layer introduced between the single crystal substrate and the single crystal layer of the compound semiconductor,
A first intermediate layer made of the compound semiconductor as an initial growth layer is formed on the single crystal substrate, and on the first intermediate layer, InGaAs/GaAs, InGaAs/GaAsP, AlGaAs/GaAs,
InAsP/InP, InP/InGaP, ZnSe/
A second intermediate layer made of at least one strained superlattice layer selected from ZnSSe and ZnSeTe/ZnSe is provided, and all or part of the single crystal layer of the compound semiconductor and the first intermediate layer are provided. All or part of the second intermediate layer contains Si, S, Zn, Mg, In, Al.
At least one impurity selected from among
A composite semiconductor substrate characterized in that three or more of 10^1^8cm^-^ are added. 4. In the composite semiconductor substrate according to claim 1, 2, or 3, before or after introducing the first intermediate layer or the second intermediate layer, the substrate temperature is lowered to 700°C.
A composite semiconductor substrate characterized in that it has been subjected to thermal annealing treatment repeated 1 to 200 times between a temperature range of ~900°C to a temperature range of 0 to 300°C.