JPH02172319A - Analog switch circuit - Google Patents

Analog switch circuit

Info

Publication number
JPH02172319A
JPH02172319A JP63326204A JP32620488A JPH02172319A JP H02172319 A JPH02172319 A JP H02172319A JP 63326204 A JP63326204 A JP 63326204A JP 32620488 A JP32620488 A JP 32620488A JP H02172319 A JPH02172319 A JP H02172319A
Authority
JP
Japan
Prior art keywords
gate
terminal
resistance
analog switch
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63326204A
Other languages
Japanese (ja)
Inventor
Tatsuo Shibuya
渋谷　龍夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kokusai Electric Corp
Original Assignee
Kokusai Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kokusai Electric Corp filed Critical Kokusai Electric Corp
Priority to JP63326204A priority Critical patent/JPH02172319A/en
Publication of JPH02172319A publication Critical patent/JPH02172319A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To make the ON-resistance of an analog switch constant with the adjustment of a gate voltage by providing a gate terminal controlling ON/OFF of the analog switch and a gate terminal controlling the ON-resistance of the analog switch. CONSTITUTION:With an ON/OFF gate terminal t2 at logical L, since a terminal t3 goes to H, a transmission gate T is latched to the OFF state and TRs Q1, Q2 are turned off. When the terminal t2 goes to H, the terminal t3 goes to L, the transmission gate T is turned ON and a variable voltage V for adjusting the ON-resistance is applied to the gate of the TRs Q1, Q2 to turn ON the TRs Q1, Q2 thereby adjusting the ON-resistance of the TRs Q1, Q2 by the adjustment of the voltage V. In the case of forming many analog switches on the same semiconductor wafer, the control gate voltage is used in common to make the switch-ON resistance equal to each other.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明はゲート電圧の調整によりオン抵抗を可変できる
アナログスイッチ回路に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an analog switch circuit whose on-resistance can be varied by adjusting gate voltage.

（従来技術） ＭＯＳ）ランジスタを用いたアナログスイッチのオン抵
抗のバラツキによる入出力信号変動を補正する方法とし
て、従来は外部抵抗によって入出力信号レベルを調整し
ていた。したがって、扱う信号数だけ調整が必要になる
欠点があった。(Prior Art) Conventionally, as a method of correcting input/output signal fluctuations due to variations in on-resistance of analog switches using MOS transistors, input/output signal levels have been adjusted using external resistors. Therefore, there is a drawback that adjustment is required for the number of signals to be handled.

（発明の目的） そこで本発明は、アナログスイッチのオン抵抗をゲート
電圧の調整により一定にすることができるアナログスイ
ッチ回路を提供することを目的とする。(Object of the Invention) Therefore, an object of the present invention is to provide an analog switch circuit that can make the on-resistance of the analog switch constant by adjusting the gate voltage.

（発明の構成） 本発明のアナログスイッチ回路はアナログスイッチのオ
ン　オフを制御するゲート端子と、上記アナログスイッ
チのオン抵抗を制御するゲート端子とを備えていること
を特徴とする。(Structure of the Invention) The analog switch circuit of the present invention is characterized in that it includes a gate terminal that controls on/off of the analog switch, and a gate terminal that controls the on-resistance of the analog switch.

（実　施　例） 以下、本発明の一実施例を示す図面を参照して本発明を
説明する。(Example) The present invention will be described below with reference to drawings showing an example of the present invention.

図において、Ｑｌ、Ｑ２はＮチャンネルＭＯＳトランジ
スタで、トランジスタＱ１のソースにはスイッチ入力が
印加される。トランジスタＱ１ドレインはトランジスタ
Ｑ２のソースに接続され、このトランジスタＱ２のドレ
インからスイッチ出力が導出される。ＴはＰチャンネル
ＭＯ３）ランジスタＱ３とＮチャンネルＭＯＳトランジ
スタＱ４とによって構成されたトランスミッションゲー
トで、その入力端子ｔ１が本発明のアナログスイノ子回
路のコントロールゲート端子となっており、そこにオン
抵抗調整用の可変電圧Ｖの電源が接続されている。トラ
ンスミソションゲ−１−Ｔの正極性側制御電圧端子Ｌ２
はスイッチのオン　オフゲト端子となっており、この端
子ｔ２はインハークＩを介してｌ・ランスミッションゲ
ートＴの逆極性側制御電圧端子（３に接続されている。In the figure, Ql and Q2 are N-channel MOS transistors, and a switch input is applied to the source of the transistor Q1. The drain of transistor Q1 is connected to the source of transistor Q2, and the switch output is derived from the drain of transistor Q2. T is a transmission gate constituted by a P-channel MO3) transistor Q3 and an N-channel MOS transistor Q4, and its input terminal t1 is the control gate terminal of the analog switchover circuit of the present invention, and the on-resistance adjustment is performed there. A variable voltage V power supply is connected. Positive polarity side control voltage terminal L2 of transmission transmission game 1-T
is the on/off gate terminal of the switch, and this terminal t2 is connected to the reverse polarity side control voltage terminal (3) of the transmission gate T through the in-hake I.

またトランスミッションゲートＴの出力端子ｔ４はトラ
ンジスタＱｌ、Ｑ２のゲートに接続されている。Further, the output terminal t4 of the transmission gate T is connected to the gates of the transistors Ql and Q2.

さらに」二記端子Ｌ３には２個のＮチャンネルＭＯＳト
ランジスタＱ５、Ｑ６のゲートが接続されている。そし
てトランジスタＱ５のドレインはトランジスタＱ１のド
レインとＱ２のソースとの接続点に接続され、ソースは
接地されている。またトランジスタＱ６のドレインはｌ
・ランジスタＱ１、Ｑ２のゲーｌ−に接続され、ソース
は接地されている。Further, the gates of two N-channel MOS transistors Q5 and Q6 are connected to the second terminal L3. The drain of the transistor Q5 is connected to the connection point between the drain of the transistor Q1 and the source of the transistor Q2, and the source is grounded. Also, the drain of transistor Q6 is l
- It is connected to the gate L- of transistors Q1 and Q2, and its source is grounded.

以上の構成にまり、オン・オフゲート端子ｔ２が「１、
］のときは端子ｔ３が「Ｈ」となるので、トランスミッ
ションゲー１〜ＴはＯＦＦ状態に保持され、トランジス
タＱ１、Ｑ２もオフになっている。そこで端子ｔ２がｒ
ＨＪになれは端子む３が「Ｌ」となり、トランスミソシ
ョンゲ−１−’　Ｔがオンになって、トランジスタＱ］
、Ｑ２のゲートにオン抵抗調整用の可変電圧■が印加さ
れてトランジスタＱ１、Ｑ２がオンになり、かつこの電
圧■の調整によってトランジスタＱｌ、Ｑ２のオン抵抗
を調整することができる。With the above configuration, the on/off gate terminal t2 is “1,”
], the terminal t3 becomes "H", so the transmission gates 1 to T are held in the OFF state, and the transistors Q1 and Q2 are also turned off. Therefore, terminal t2 is r
When it becomes HJ, terminal 3 becomes "L", transmission gate 1-'T turns on, and transistor Q]
, Q2 are applied with a variable voltage (2) for adjusting the on-resistance to turn on the transistors Q1, Q2, and by adjusting this voltage (2), the on-resistances of the transistors Q1, Q2 can be adjusted.

（発明の効果） 本発明によれば、同一半導体ウェーハ上に多数のアナロ
グスイッチを構成した場合、コントロールゲート電圧が
共通になり、スイッチオン抵抗を同一にすることができ
る。(Effects of the Invention) According to the present invention, when a large number of analog switches are configured on the same semiconductor wafer, the control gate voltage becomes common, and the switch-on resistance can be made the same.

【図面の簡単な説明】[Brief explanation of the drawing]

図面は本発明の実施例の回路図である。 ０１〜Ｑ　６−−Ｍ　ＯＳ　トランジスタＴ−）ランス
ミッションゲート ！　−インパークThe drawing is a circuit diagram of an embodiment of the present invention. 01~Q 6--M OS transistor T-) Transmission gate! −Inpark

Claims (1)

【特許請求の範囲】[Claims] 　アナログスイッチのオン・オフを制御するゲート端子
と、上記アナログスイッチのオン抵抗を制御するゲート
端子とを備えたアナログスイッチ回路。An analog switch circuit comprising a gate terminal that controls on/off of the analog switch, and a gate terminal that controls the on-resistance of the analog switch.
JP63326204A 1988-12-26 1988-12-26 Analog switch circuit Pending JPH02172319A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63326204A JPH02172319A (en) 1988-12-26 1988-12-26 Analog switch circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63326204A JPH02172319A (en) 1988-12-26 1988-12-26 Analog switch circuit

Publications (1)

Publication Number Publication Date
JPH02172319A true JPH02172319A (en) 1990-07-03

Family

ID=18185170

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63326204A Pending JPH02172319A (en) 1988-12-26 1988-12-26 Analog switch circuit

Country Status (1)

Country Link
JP (1) JPH02172319A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014078677A1 (en) * 2012-11-15 2014-05-22 Texas Instruments Incorporated Wide common mode range transmission gate

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014078677A1 (en) * 2012-11-15 2014-05-22 Texas Instruments Incorporated Wide common mode range transmission gate
US8975948B2 (en) 2012-11-15 2015-03-10 Texas Instruments Incorporated Wide common mode range transmission gate
CN104769844A (en) * 2012-11-15 2015-07-08 德州仪器公司 Wide common mode range transmission gate

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